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ARM: imx25: set default phy_type and dr_mode for usbotg port
[mirror_ubuntu-focal-kernel.git] / arch / arm / boot / dts / imx25.dtsi
CommitLineData
5658a68f
SH		 1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
f4db4bc5 12#include "imx25-pinfunc.h"
5658a68f
SH		 13
14/ {
7f107887
FE		 15 #address-cells = <1>;
16 #size-cells = <1>;
a971c554
FE		 17 /*
18 * The decompressor and also some bootloaders rely on a
19 * pre-existing /chosen node to be available to insert the
20 * command line and merge other ATAGS info.
21 * Also for U-Boot there must be a pre-existing /memory node.
22 */
23 chosen {};
24 memory { device_type = "memory"; reg = <0 0>; };
7f107887 25
5658a68f 26 aliases {
22970070 27 ethernet0 = &fec;
6ed1a0e5
SH		 28 gpio0 = &gpio1;
29 gpio1 = &gpio2;
30 gpio2 = &gpio3;
31 gpio3 = &gpio4;
32 i2c0 = &i2c1;
33 i2c1 = &i2c2;
34 i2c2 = &i2c3;
9e3a424b
SH		 35 mmc0 = &esdhc1;
36 mmc1 = &esdhc2;
70f97128
MKB		 37 pwm0 = &pwm1;
38 pwm1 = &pwm2;
39 pwm2 = &pwm3;
40 pwm3 = &pwm4;
5658a68f
SH		 41 serial0 = &uart1;
42 serial1 = &uart2;
43 serial2 = &uart3;
44 serial3 = &uart4;
45 serial4 = &uart5;
6ed1a0e5
SH		 46 spi0 = &spi1;
47 spi1 = &spi2;
48 spi2 = &spi3;
5658a68f
SH		 49 usb0 = &usbotg;
50 usb1 = &usbhost1;
51 };
52
070bd7e4 53 cpus {
d447dd88 54 #address-cells = <1>;
070bd7e4
FE		 55 #size-cells = <0>;
56
d447dd88 57 cpu@0 {
070bd7e4
FE		 58 compatible = "arm,arm926ej-s";
59 device_type = "cpu";
d447dd88 60 reg = <0>;
070bd7e4
FE		 61 };
62 };
63
5658a68f
SH		 64 asic: asic-interrupt-controller@68000000 {
65 compatible = "fsl,imx25-asic", "fsl,avic";
66 interrupt-controller;
67 #interrupt-cells = <1>;
68 reg = <0x68000000 0x8000000>;
69 };
70
71 clocks {
72 #address-cells = <1>;
73 #size-cells = <0>;
74
75 osc {
76 compatible = "fsl,imx-osc", "fixed-clock";
4b2b4043 77 #clock-cells = <0>;
5658a68f
SH		 78 clock-frequency = <24000000>;
79 };
80 };
81
82 soc {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "simple-bus";
86 interrupt-parent = <&asic>;
87 ranges;
88
89 aips@43f00000 { /* AIPS1 */
90 compatible = "fsl,aips-bus", "simple-bus";
91 #address-cells = <1>;
92 #size-cells = <1>;
93 reg = <0x43f00000 0x100000>;
94 ranges;
95
96 i2c1: i2c@43f80000 {
97 #address-cells = <1>;
98 #size-cells = <0>;
99 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
100 reg = <0x43f80000 0x4000>;
101 clocks = <&clks 48>;
102 clock-names = "";
103 interrupts = <3>;
104 status = "disabled";
105 };
106
107 i2c3: i2c@43f84000 {
108 #address-cells = <1>;
109 #size-cells = <0>;
110 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
111 reg = <0x43f84000 0x4000>;
112 clocks = <&clks 48>;
113 clock-names = "";
114 interrupts = <10>;
115 status = "disabled";
116 };
117
118 can1: can@43f88000 {
119 compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
120 reg = <0x43f88000 0x4000>;
121 interrupts = <43>;
122 clocks = <&clks 75>, <&clks 75>;
123 clock-names = "ipg", "per";
124 status = "disabled";
125 };
126
127 can2: can@43f8c000 {
128 compatible = "fsl,imx25-flexcan", "fsl,p1010-flexcan";
129 reg = <0x43f8c000 0x4000>;
130 interrupts = <44>;
131 clocks = <&clks 76>, <&clks 76>;
132 clock-names = "ipg", "per";
133 status = "disabled";
134 };
135
136 uart1: serial@43f90000 {
137 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
138 reg = <0x43f90000 0x4000>;
139 interrupts = <45>;
140 clocks = <&clks 120>, <&clks 57>;
141 clock-names = "ipg", "per";
142 status = "disabled";
143 };
144
145 uart2: serial@43f94000 {
146 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
147 reg = <0x43f94000 0x4000>;
148 interrupts = <32>;
149 clocks = <&clks 121>, <&clks 57>;
150 clock-names = "ipg", "per";
151 status = "disabled";
152 };
153
154 i2c2: i2c@43f98000 {
155 #address-cells = <1>;
156 #size-cells = <0>;
157 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
158 reg = <0x43f98000 0x4000>;
159 clocks = <&clks 48>;
160 clock-names = "";
161 interrupts = <4>;
162 status = "disabled";
163 };
164
165 owire@43f9c000 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 reg = <0x43f9c000 0x4000>;
169 clocks = <&clks 51>;
170 clock-names = "";
171 interrupts = <2>;
172 status = "disabled";
173 };
174
175 spi1: cspi@43fa4000 {
176 #address-cells = <1>;
177 #size-cells = <0>;
178 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
179 reg = <0x43fa4000 0x4000>;
7a87e9cb 180 clocks = <&clks 78>, <&clks 78>;
37523dc5 181 clock-names = "ipg", "per";
5658a68f
SH		 182 interrupts = <14>;
183 status = "disabled";
184 };
185
9223dd87 186 kpp: kpp@43fa8000 {
5658a68f
SH		 187 #address-cells = <1>;
188 #size-cells = <0>;
9223dd87 189 compatible = "fsl,imx25-kpp", "fsl,imx21-kpp";
5658a68f
SH		 190 reg = <0x43fa8000 0x4000>;
191 clocks = <&clks 102>;
192 clock-names = "";
193 interrupts = <24>;
194 status = "disabled";
195 };
196
53110aa0 197 iomuxc: iomuxc@43fac000 {
5658a68f
SH		 198 compatible = "fsl,imx25-iomuxc";
199 reg = <0x43fac000 0x4000>;
200 };
201
ec2ea8c1 202 audmux: audmux@43fb0000 {
5658a68f
SH		 203 compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
204 reg = <0x43fb0000 0x4000>;
205 status = "disabled";
206 };
207 };
208
209 spba@50000000 {
210 compatible = "fsl,spba-bus", "simple-bus";
211 #address-cells = <1>;
212 #size-cells = <1>;
213 reg = <0x50000000 0x40000>;
214 ranges;
215
216 spi3: cspi@50004000 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
220 reg = <0x50004000 0x4000>;
221 interrupts = <0>;
37523dc5
JA		 222 clocks = <&clks 80>, <&clks 80>;
223 clock-names = "ipg", "per";
5658a68f
SH		 224 status = "disabled";
225 };
226
227 uart4: serial@50008000 {
228 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
229 reg = <0x50008000 0x4000>;
230 interrupts = <5>;
231 clocks = <&clks 123>, <&clks 57>;
232 clock-names = "ipg", "per";
233 status = "disabled";
234 };
235
236 uart3: serial@5000c000 {
237 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
238 reg = <0x5000c000 0x4000>;
239 interrupts = <18>;
240 clocks = <&clks 122>, <&clks 57>;
241 clock-names = "ipg", "per";
242 status = "disabled";
243 };
244
245 spi2: cspi@50010000 {
246 #address-cells = <1>;
247 #size-cells = <0>;
248 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
249 reg = <0x50010000 0x4000>;
37523dc5
JA		 250 clocks = <&clks 79>, <&clks 79>;
251 clock-names = "ipg", "per";
5658a68f
SH		 252 interrupts = <13>;
253 status = "disabled";
254 };
255
256 ssi2: ssi@50014000 {
6ff7f51e 257 #sound-dai-cells = <0>;
5658a68f
SH		 258 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
259 reg = <0x50014000 0x4000>;
260 interrupts = <11>;
7803c620
DC		 261 clocks = <&clks 118>;
262 clock-names = "ipg";
263 dmas = <&sdma 24 1 0>,
264 <&sdma 25 1 0>;
265 dma-names = "rx", "tx";
5658a68f
SH		 266 status = "disabled";
267 };
268
269 esai@50018000 {
270 reg = <0x50018000 0x4000>;
271 interrupts = <7>;
272 };
273
274 uart5: serial@5002c000 {
275 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
276 reg = <0x5002c000 0x4000>;
277 interrupts = <40>;
278 clocks = <&clks 124>, <&clks 57>;
279 clock-names = "ipg", "per";
280 status = "disabled";
281 };
282
92f651f3
DC		 283 tscadc: tscadc@50030000 {
284 compatible = "fsl,imx25-tsadc";
285 reg = <0x50030000 0xc>;
5658a68f
SH		 286 interrupts = <46>;
287 clocks = <&clks 119>;
288 clock-names = "ipg";
92f651f3
DC		 289 interrupt-controller;
290 #interrupt-cells = <1>;
291 #address-cells = <1>;
292 #size-cells = <1>;
5658a68f 293 status = "disabled";
92f651f3
DC		 294
295 adc: adc@50030800 {
296 compatible = "fsl,imx25-gcq";
297 reg = <0x50030800 0x60>;
298 interrupt-parent = <&tscadc>;
299 interrupts = <1>;
300 #address-cells = <1>;
301 #size-cells = <0>;
302 status = "disabled";
303 };
304
305 tsc: tcq@50030400 {
306 compatible = "fsl,imx25-tcq";
307 reg = <0x50030400 0x60>;
308 interrupt-parent = <&tscadc>;
309 interrupts = <0>;
310 fsl,wires = <4>;
311 status = "disabled";
312 };
5658a68f
SH		 313 };
314
315 ssi1: ssi@50034000 {
6ff7f51e 316 #sound-dai-cells = <0>;
5658a68f
SH		 317 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
318 reg = <0x50034000 0x4000>;
319 interrupts = <12>;
7803c620
DC		 320 clocks = <&clks 117>;
321 clock-names = "ipg";
322 dmas = <&sdma 28 1 0>,
323 <&sdma 29 1 0>;
324 dma-names = "rx", "tx";
5658a68f
SH		 325 status = "disabled";
326 };
327
328 fec: ethernet@50038000 {
329 compatible = "fsl,imx25-fec";
330 reg = <0x50038000 0x4000>;
331 interrupts = <57>;
332 clocks = <&clks 88>, <&clks 65>;
333 clock-names = "ipg", "ahb";
334 status = "disabled";
335 };
336 };
337
338 aips@53f00000 { /* AIPS2 */
339 compatible = "fsl,aips-bus", "simple-bus";
340 #address-cells = <1>;
341 #size-cells = <1>;
342 reg = <0x53f00000 0x100000>;
343 ranges;
344
345 clks: ccm@53f80000 {
346 compatible = "fsl,imx25-ccm";
347 reg = <0x53f80000 0x4000>;
348 interrupts = <31>;
349 #clock-cells = <1>;
350 };
351
352 gpt4: timer@53f84000 {
353 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
354 reg = <0x53f84000 0x4000>;
5363dcab 355 clocks = <&clks 95>, <&clks 47>;
5658a68f
SH		 356 clock-names = "ipg", "per";
357 interrupts = <1>;
358 };
359
360 gpt3: timer@53f88000 {
361 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
362 reg = <0x53f88000 0x4000>;
5363dcab 363 clocks = <&clks 94>, <&clks 47>;
5658a68f
SH		 364 clock-names = "ipg", "per";
365 interrupts = <29>;
366 };
367
368 gpt2: timer@53f8c000 {
369 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
370 reg = <0x53f8c000 0x4000>;
5363dcab 371 clocks = <&clks 93>, <&clks 47>;
5658a68f
SH		 372 clock-names = "ipg", "per";
373 interrupts = <53>;
374 };
375
376 gpt1: timer@53f90000 {
377 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
378 reg = <0x53f90000 0x4000>;
5363dcab 379 clocks = <&clks 92>, <&clks 47>;
5658a68f
SH		 380 clock-names = "ipg", "per";
381 interrupts = <54>;
382 };
383
384 epit1: timer@53f94000 {
385 compatible = "fsl,imx25-epit";
386 reg = <0x53f94000 0x4000>;
387 interrupts = <28>;
388 };
389
390 epit2: timer@53f98000 {
391 compatible = "fsl,imx25-epit";
392 reg = <0x53f98000 0x4000>;
393 interrupts = <27>;
394 };
395
396 gpio4: gpio@53f9c000 {
397 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
398 reg = <0x53f9c000 0x4000>;
399 interrupts = <23>;
400 gpio-controller;
401 #gpio-cells = <2>;
402 interrupt-controller;
403 #interrupt-cells = <2>;
404 };
405
406 pwm2: pwm@53fa0000 {
407 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
408 #pwm-cells = <2>;
409 reg = <0x53fa0000 0x4000>;
7ecd0bde 410 clocks = <&clks 106>, <&clks 52>;
5658a68f
SH		 411 clock-names = "ipg", "per";
412 interrupts = <36>;
413 };
414
415 gpio3: gpio@53fa4000 {
416 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
417 reg = <0x53fa4000 0x4000>;
418 interrupts = <16>;
419 gpio-controller;
420 #gpio-cells = <2>;
421 interrupt-controller;
422 #interrupt-cells = <2>;
423 };
424
425 pwm3: pwm@53fa8000 {
426 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
427 #pwm-cells = <2>;
428 reg = <0x53fa8000 0x4000>;
7ecd0bde 429 clocks = <&clks 107>, <&clks 52>;
5658a68f
SH		 430 clock-names = "ipg", "per";
431 interrupts = <41>;
432 };
433
ba97eed2
ST		 434 scc: crypto@53fac000 {
435 compatible = "fsl,imx25-scc";
436 reg = <0x53fac000 0x4000>;
437 clocks = <&clks 111>;
438 clock-names = "ipg";
439 interrupts = <49>, <50>;
440 interrupt-names = "scm", "smn";
441 };
442
5658a68f
SH		 443 esdhc1: esdhc@53fb4000 {
444 compatible = "fsl,imx25-esdhc";
445 reg = <0x53fb4000 0x4000>;
446 interrupts = <9>;
447 clocks = <&clks 86>, <&clks 63>, <&clks 45>;
448 clock-names = "ipg", "ahb", "per";
449 status = "disabled";
450 };
451
452 esdhc2: esdhc@53fb8000 {
453 compatible = "fsl,imx25-esdhc";
454 reg = <0x53fb8000 0x4000>;
455 interrupts = <8>;
456 clocks = <&clks 87>, <&clks 64>, <&clks 46>;
457 clock-names = "ipg", "ahb", "per";
458 status = "disabled";
459 };
460
c770f7c0
MW		 461 lcdc: lcdc@53fbc000 {
462 compatible = "fsl,imx25-fb", "fsl,imx21-fb";
5658a68f
SH		 463 reg = <0x53fbc000 0x4000>;
464 interrupts = <39>;
465 clocks = <&clks 103>, <&clks 66>, <&clks 49>;
466 clock-names = "ipg", "ahb", "per";
467 status = "disabled";
468 };
469
470 slcdc@53fc0000 {
471 reg = <0x53fc0000 0x4000>;
472 interrupts = <38>;
473 status = "disabled";
474 };
475
476 pwm4: pwm@53fc8000 {
477 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
f90d3f0d 478 #pwm-cells = <2>;
5658a68f 479 reg = <0x53fc8000 0x4000>;
7ecd0bde 480 clocks = <&clks 108>, <&clks 52>;
5658a68f
SH		 481 clock-names = "ipg", "per";
482 interrupts = <42>;
483 };
484
485 gpio1: gpio@53fcc000 {
486 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
487 reg = <0x53fcc000 0x4000>;
488 interrupts = <52>;
489 gpio-controller;
490 #gpio-cells = <2>;
491 interrupt-controller;
492 #interrupt-cells = <2>;
493 };
494
495 gpio2: gpio@53fd0000 {
496 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
497 reg = <0x53fd0000 0x4000>;
498 interrupts = <51>;
499 gpio-controller;
500 #gpio-cells = <2>;
501 interrupt-controller;
502 #interrupt-cells = <2>;
503 };
504
7803c620 505 sdma: sdma@53fd4000 {
0f429057 506 compatible = "fsl,imx25-sdma";
5658a68f
SH		 507 reg = <0x53fd4000 0x4000>;
508 clocks = <&clks 112>, <&clks 68>;
509 clock-names = "ipg", "ahb";
fb72bb21 510 #dma-cells = <3>;
5658a68f 511 interrupts = <34>;
cabd1b29 512 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin";
5658a68f
SH		 513 };
514
515 wdog@53fdc000 {
516 compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
517 reg = <0x53fdc000 0x4000>;
518 clocks = <&clks 126>;
519 clock-names = "";
520 interrupts = <55>;
521 };
522
523 pwm1: pwm@53fe0000 {
524 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
525 #pwm-cells = <2>;
526 reg = <0x53fe0000 0x4000>;
7ecd0bde 527 clocks = <&clks 105>, <&clks 52>;
5658a68f
SH		 528 clock-names = "ipg", "per";
529 interrupts = <26>;
530 };
531
684f6a23
SH		 532 iim: iim@53ff0000 {
533 compatible = "fsl,imx25-iim", "fsl,imx27-iim";
534 reg = <0x53ff0000 0x4000>;
535 interrupts = <19>;
536 clocks = <&clks 99>;
537 };
538
5658a68f
SH		 539 usbotg: usb@53ff4000 {
540 compatible = "fsl,imx25-usb", "fsl,imx27-usb";
541 reg = <0x53ff4000 0x0200>;
542 interrupts = <37>;
1b8d1ea9
PC		 543 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
544 clock-names = "ipg", "ahb", "per";
5658a68f 545 fsl,usbmisc = <&usbmisc 0>;
f415153c 546 fsl,usbphy = <&usbphy0>;
10ad0dda
UKK		 547 phy_type = "utmi";
548 dr_mode = "otg";
5658a68f
SH		 549 status = "disabled";
550 };
551
552 usbhost1: usb@53ff4400 {
553 compatible = "fsl,imx25-usb", "fsl,imx27-usb";
554 reg = <0x53ff4400 0x0200>;
555 interrupts = <35>;
1b8d1ea9
PC		 556 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
557 clock-names = "ipg", "ahb", "per";
5658a68f 558 fsl,usbmisc = <&usbmisc 1>;
f415153c 559 fsl,usbphy = <&usbphy1>;
5658a68f
SH		 560 status = "disabled";
561 };
562
563 usbmisc: usbmisc@53ff4600 {
564 #index-cells = <1>;
565 compatible = "fsl,imx25-usbmisc";
5658a68f 566 reg = <0x53ff4600 0x00f>;
5658a68f
SH		 567 };
568
569 dryice@53ffc000 {
570 compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
571 reg = <0x53ffc000 0x4000>;
572 clocks = <&clks 81>;
573 clock-names = "ipg";
f082bbff 574 interrupts = <25 56>;
5658a68f
SH		 575 };
576 };
577
41707314
SH		 578 iram: sram@78000000 {
579 compatible = "mmio-sram";
580 reg = <0x78000000 0x20000>;
581 };
582
5658a68f
SH		 583 emi@80000000 {
584 compatible = "fsl,emi-bus", "simple-bus";
585 #address-cells = <1>;
586 #size-cells = <1>;
587 reg = <0x80000000 0x3b002000>;
588 ranges;
589
be4ccfce 590 nfc: nand@bb000000 {
5658a68f
SH		 591 #address-cells = <1>;
592 #size-cells = <1>;
593
594 compatible = "fsl,imx25-nand";
595 reg = <0xbb000000 0x2000>;
596 clocks = <&clks 50>;
597 clock-names = "";
598 interrupts = <33>;
599 status = "disabled";
600 };
601 };
602 };
f415153c
FE		 603
604 usbphy {
605 compatible = "simple-bus";
606 #address-cells = <1>;
607 #size-cells = <0>;
608
609 usbphy0: usb-phy@0 {
610 reg = <0>;
611 compatible = "usb-nop-xceiv";
612 };
613
614 usbphy1: usb-phy@1 {
615 reg = <1>;
616 compatible = "usb-nop-xceiv";
617 };
618 };
5658a68f 619};
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