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Commit | Line | Data |
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241f76b2 FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // | |
3 | // Copyright 2012 Sascha Hauer, Pengutronix | |
9f0749e3 | 4 | |
61664d0b | 5 | #include "imx27-pinfunc.h" |
ea336fa8 AS |
6 | |
7 | #include <dt-bindings/clock/imx27-clock.h> | |
8 | #include <dt-bindings/gpio/gpio.h> | |
f6bd3f30 | 9 | #include <dt-bindings/input/input.h> |
6ece55b3 | 10 | #include <dt-bindings/interrupt-controller/irq.h> |
9f0749e3 SH |
11 | |
12 | / { | |
7f107887 FE |
13 | #address-cells = <1>; |
14 | #size-cells = <1>; | |
a971c554 FE |
15 | /* |
16 | * The decompressor and also some bootloaders rely on a | |
17 | * pre-existing /chosen node to be available to insert the | |
18 | * command line and merge other ATAGS info. | |
19 | * Also for U-Boot there must be a pre-existing /memory node. | |
20 | */ | |
21 | chosen {}; | |
7f08e6aa | 22 | memory { device_type = "memory"; }; |
7f107887 | 23 | |
9f0749e3 | 24 | aliases { |
22970070 | 25 | ethernet0 = &fec; |
5230f8fe SG |
26 | gpio0 = &gpio1; |
27 | gpio1 = &gpio2; | |
28 | gpio2 = &gpio3; | |
29 | gpio3 = &gpio4; | |
30 | gpio4 = &gpio5; | |
31 | gpio5 = &gpio6; | |
6a3c0b39 SH |
32 | i2c0 = &i2c1; |
33 | i2c1 = &i2c2; | |
34 | serial0 = &uart1; | |
35 | serial1 = &uart2; | |
36 | serial2 = &uart3; | |
37 | serial3 = &uart4; | |
38 | serial4 = &uart5; | |
39 | serial5 = &uart6; | |
a5a641a1 AS |
40 | spi0 = &cspi1; |
41 | spi1 = &cspi2; | |
42 | spi2 = &cspi3; | |
9f0749e3 SH |
43 | }; |
44 | ||
6189bc34 FE |
45 | aitc: aitc-interrupt-controller@e0000000 { |
46 | compatible = "fsl,imx27-aitc", "fsl,avic"; | |
9f0749e3 SH |
47 | interrupt-controller; |
48 | #interrupt-cells = <1>; | |
49 | reg = <0x10040000 0x1000>; | |
50 | }; | |
51 | ||
52 | clocks { | |
0c414b06 | 53 | clk_osc26m: osc26m { |
9f0749e3 | 54 | compatible = "fsl,imx-osc26m", "fixed-clock"; |
4b2b4043 | 55 | #clock-cells = <0>; |
9f0749e3 SH |
56 | clock-frequency = <26000000>; |
57 | }; | |
58 | }; | |
59 | ||
dc1d0f91 MP |
60 | cpus { |
61 | #size-cells = <0>; | |
62 | #address-cells = <1>; | |
63 | ||
48568be6 | 64 | cpu: cpu@0 { |
dc1d0f91 | 65 | device_type = "cpu"; |
d447dd88 | 66 | reg = <0>; |
dc1d0f91 MP |
67 | compatible = "arm,arm926ej-s"; |
68 | operating-points = < | |
98a3e804 AS |
69 | /* kHz uV */ |
70 | 266000 1300000 | |
71 | 399000 1450000 | |
dc1d0f91 | 72 | >; |
8defcb53 | 73 | clock-latency = <62500>; |
ea336fa8 | 74 | clocks = <&clks IMX27_CLK_CPU_DIV>; |
98a3e804 | 75 | voltage-tolerance = <5>; |
dc1d0f91 MP |
76 | }; |
77 | }; | |
78 | ||
9f0749e3 SH |
79 | soc { |
80 | #address-cells = <1>; | |
81 | #size-cells = <1>; | |
82 | compatible = "simple-bus"; | |
6189bc34 | 83 | interrupt-parent = <&aitc>; |
9f0749e3 SH |
84 | ranges; |
85 | ||
86 | aipi@10000000 { /* AIPI1 */ | |
87 | compatible = "fsl,aipi-bus", "simple-bus"; | |
88 | #address-cells = <1>; | |
89 | #size-cells = <1>; | |
3e24b05b | 90 | reg = <0x10000000 0x20000>; |
9f0749e3 SH |
91 | ranges; |
92 | ||
b858c34f AS |
93 | dma: dma@10001000 { |
94 | compatible = "fsl,imx27-dma"; | |
95 | reg = <0x10001000 0x1000>; | |
96 | interrupts = <32>; | |
ea336fa8 AS |
97 | clocks = <&clks IMX27_CLK_DMA_IPG_GATE>, |
98 | <&clks IMX27_CLK_DMA_AHB_GATE>; | |
b858c34f AS |
99 | clock-names = "ipg", "ahb"; |
100 | #dma-cells = <1>; | |
101 | #dma-channels = <16>; | |
102 | }; | |
103 | ||
7b7d6727 | 104 | wdog: wdog@10002000 { |
9f0749e3 | 105 | compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; |
ca26d041 | 106 | reg = <0x10002000 0x1000>; |
9f0749e3 | 107 | interrupts = <27>; |
ea336fa8 | 108 | clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>; |
9f0749e3 SH |
109 | }; |
110 | ||
ca26d041 | 111 | gpt1: timer@10003000 { |
afde1312 | 112 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
ca26d041 SH |
113 | reg = <0x10003000 0x1000>; |
114 | interrupts = <26>; | |
ea336fa8 AS |
115 | clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>, |
116 | <&clks IMX27_CLK_PER1_GATE>; | |
b700c119 | 117 | clock-names = "ipg", "per"; |
ca26d041 SH |
118 | }; |
119 | ||
120 | gpt2: timer@10004000 { | |
afde1312 | 121 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
ca26d041 SH |
122 | reg = <0x10004000 0x1000>; |
123 | interrupts = <25>; | |
ea336fa8 AS |
124 | clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>, |
125 | <&clks IMX27_CLK_PER1_GATE>; | |
b700c119 | 126 | clock-names = "ipg", "per"; |
ca26d041 SH |
127 | }; |
128 | ||
129 | gpt3: timer@10005000 { | |
afde1312 | 130 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
ca26d041 SH |
131 | reg = <0x10005000 0x1000>; |
132 | interrupts = <24>; | |
ea336fa8 AS |
133 | clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>, |
134 | <&clks IMX27_CLK_PER1_GATE>; | |
b700c119 | 135 | clock-names = "ipg", "per"; |
ca26d041 SH |
136 | }; |
137 | ||
a392d044 | 138 | pwm: pwm@10006000 { |
443b6585 | 139 | #pwm-cells = <2>; |
08f4881a GGM |
140 | compatible = "fsl,imx27-pwm"; |
141 | reg = <0x10006000 0x1000>; | |
142 | interrupts = <23>; | |
ea336fa8 AS |
143 | clocks = <&clks IMX27_CLK_PWM_IPG_GATE>, |
144 | <&clks IMX27_CLK_PER1_GATE>; | |
08f4881a GGM |
145 | clock-names = "ipg", "per"; |
146 | }; | |
147 | ||
91eca8d5 PR |
148 | rtc: rtc@10007000 { |
149 | compatible = "fsl,imx21-rtc"; | |
150 | reg = <0x10007000 0x1000>; | |
151 | interrupts = <22>; | |
152 | clocks = <&clks IMX27_CLK_CKIL>, | |
153 | <&clks IMX27_CLK_RTC_IPG_GATE>; | |
154 | clock-names = "ref", "ipg"; | |
155 | }; | |
156 | ||
6c04ad22 AS |
157 | kpp: kpp@10008000 { |
158 | compatible = "fsl,imx27-kpp", "fsl,imx21-kpp"; | |
159 | reg = <0x10008000 0x1000>; | |
160 | interrupts = <21>; | |
ea336fa8 | 161 | clocks = <&clks IMX27_CLK_KPP_IPG_GATE>; |
6c04ad22 AS |
162 | status = "disabled"; |
163 | }; | |
164 | ||
6a486b7e MP |
165 | owire: owire@10009000 { |
166 | compatible = "fsl,imx27-owire", "fsl,imx21-owire"; | |
167 | reg = <0x10009000 0x1000>; | |
ea336fa8 | 168 | clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>; |
6a486b7e MP |
169 | status = "disabled"; |
170 | }; | |
171 | ||
0c456cfa | 172 | uart1: serial@1000a000 { |
9f0749e3 SH |
173 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
174 | reg = <0x1000a000 0x1000>; | |
175 | interrupts = <20>; | |
ea336fa8 AS |
176 | clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, |
177 | <&clks IMX27_CLK_PER1_GATE>; | |
c20736f1 | 178 | clock-names = "ipg", "per"; |
9f0749e3 SH |
179 | status = "disabled"; |
180 | }; | |
181 | ||
0c456cfa | 182 | uart2: serial@1000b000 { |
9f0749e3 SH |
183 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
184 | reg = <0x1000b000 0x1000>; | |
185 | interrupts = <19>; | |
ea336fa8 AS |
186 | clocks = <&clks IMX27_CLK_UART2_IPG_GATE>, |
187 | <&clks IMX27_CLK_PER1_GATE>; | |
c20736f1 | 188 | clock-names = "ipg", "per"; |
9f0749e3 SH |
189 | status = "disabled"; |
190 | }; | |
191 | ||
0c456cfa | 192 | uart3: serial@1000c000 { |
9f0749e3 SH |
193 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
194 | reg = <0x1000c000 0x1000>; | |
195 | interrupts = <18>; | |
ea336fa8 AS |
196 | clocks = <&clks IMX27_CLK_UART3_IPG_GATE>, |
197 | <&clks IMX27_CLK_PER1_GATE>; | |
c20736f1 | 198 | clock-names = "ipg", "per"; |
9f0749e3 SH |
199 | status = "disabled"; |
200 | }; | |
201 | ||
0c456cfa | 202 | uart4: serial@1000d000 { |
9f0749e3 SH |
203 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
204 | reg = <0x1000d000 0x1000>; | |
205 | interrupts = <17>; | |
ea336fa8 AS |
206 | clocks = <&clks IMX27_CLK_UART4_IPG_GATE>, |
207 | <&clks IMX27_CLK_PER1_GATE>; | |
c20736f1 | 208 | clock-names = "ipg", "per"; |
9f0749e3 SH |
209 | status = "disabled"; |
210 | }; | |
211 | ||
5a2ecf0d | 212 | cspi1: spi@1000e000 { |
9f0749e3 SH |
213 | #address-cells = <1>; |
214 | #size-cells = <0>; | |
215 | compatible = "fsl,imx27-cspi"; | |
216 | reg = <0x1000e000 0x1000>; | |
217 | interrupts = <16>; | |
ea336fa8 AS |
218 | clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>, |
219 | <&clks IMX27_CLK_PER2_GATE>; | |
c20736f1 | 220 | clock-names = "ipg", "per"; |
9f0749e3 SH |
221 | status = "disabled"; |
222 | }; | |
223 | ||
5a2ecf0d | 224 | cspi2: spi@1000f000 { |
9f0749e3 SH |
225 | #address-cells = <1>; |
226 | #size-cells = <0>; | |
227 | compatible = "fsl,imx27-cspi"; | |
228 | reg = <0x1000f000 0x1000>; | |
229 | interrupts = <15>; | |
ea336fa8 AS |
230 | clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>, |
231 | <&clks IMX27_CLK_PER2_GATE>; | |
c20736f1 | 232 | clock-names = "ipg", "per"; |
9f0749e3 SH |
233 | status = "disabled"; |
234 | }; | |
235 | ||
ba2d1ea7 AS |
236 | ssi1: ssi@10010000 { |
237 | #sound-dai-cells = <0>; | |
238 | compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; | |
239 | reg = <0x10010000 0x1000>; | |
240 | interrupts = <14>; | |
ea336fa8 | 241 | clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>; |
ba2d1ea7 AS |
242 | dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>; |
243 | dma-names = "rx0", "tx0", "rx1", "tx1"; | |
244 | fsl,fifo-depth = <8>; | |
245 | status = "disabled"; | |
246 | }; | |
247 | ||
248 | ssi2: ssi@10011000 { | |
249 | #sound-dai-cells = <0>; | |
250 | compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; | |
251 | reg = <0x10011000 0x1000>; | |
252 | interrupts = <13>; | |
ea336fa8 | 253 | clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>; |
ba2d1ea7 AS |
254 | dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>; |
255 | dma-names = "rx0", "tx0", "rx1", "tx1"; | |
256 | fsl,fifo-depth = <8>; | |
257 | status = "disabled"; | |
258 | }; | |
259 | ||
9f0749e3 SH |
260 | i2c1: i2c@10012000 { |
261 | #address-cells = <1>; | |
262 | #size-cells = <0>; | |
5bdfba29 | 263 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; |
9f0749e3 SH |
264 | reg = <0x10012000 0x1000>; |
265 | interrupts = <12>; | |
ea336fa8 | 266 | clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>; |
9f0749e3 SH |
267 | status = "disabled"; |
268 | }; | |
269 | ||
0e7b01aa AS |
270 | sdhci1: sdhci@10013000 { |
271 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; | |
272 | reg = <0x10013000 0x1000>; | |
273 | interrupts = <11>; | |
ea336fa8 AS |
274 | clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>, |
275 | <&clks IMX27_CLK_PER2_GATE>; | |
0e7b01aa AS |
276 | clock-names = "ipg", "per"; |
277 | dmas = <&dma 7>; | |
278 | dma-names = "rx-tx"; | |
279 | status = "disabled"; | |
280 | }; | |
281 | ||
282 | sdhci2: sdhci@10014000 { | |
283 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; | |
284 | reg = <0x10014000 0x1000>; | |
285 | interrupts = <10>; | |
ea336fa8 AS |
286 | clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>, |
287 | <&clks IMX27_CLK_PER2_GATE>; | |
0e7b01aa AS |
288 | clock-names = "ipg", "per"; |
289 | dmas = <&dma 6>; | |
290 | dma-names = "rx-tx"; | |
291 | status = "disabled"; | |
292 | }; | |
293 | ||
733f6cae MP |
294 | iomuxc: iomuxc@10015000 { |
295 | compatible = "fsl,imx27-iomuxc"; | |
296 | reg = <0x10015000 0x600>; | |
297 | #address-cells = <1>; | |
298 | #size-cells = <1>; | |
299 | ranges; | |
300 | ||
301 | gpio1: gpio@10015000 { | |
302 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
303 | reg = <0x10015000 0x100>; | |
ea336fa8 | 304 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
733f6cae MP |
305 | interrupts = <8>; |
306 | gpio-controller; | |
307 | #gpio-cells = <2>; | |
308 | interrupt-controller; | |
309 | #interrupt-cells = <2>; | |
310 | }; | |
311 | ||
312 | gpio2: gpio@10015100 { | |
313 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
314 | reg = <0x10015100 0x100>; | |
ea336fa8 | 315 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
733f6cae MP |
316 | interrupts = <8>; |
317 | gpio-controller; | |
318 | #gpio-cells = <2>; | |
319 | interrupt-controller; | |
320 | #interrupt-cells = <2>; | |
321 | }; | |
322 | ||
323 | gpio3: gpio@10015200 { | |
324 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
325 | reg = <0x10015200 0x100>; | |
ea336fa8 | 326 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
733f6cae MP |
327 | interrupts = <8>; |
328 | gpio-controller; | |
329 | #gpio-cells = <2>; | |
330 | interrupt-controller; | |
331 | #interrupt-cells = <2>; | |
332 | }; | |
333 | ||
334 | gpio4: gpio@10015300 { | |
335 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
336 | reg = <0x10015300 0x100>; | |
ea336fa8 | 337 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
733f6cae MP |
338 | interrupts = <8>; |
339 | gpio-controller; | |
340 | #gpio-cells = <2>; | |
341 | interrupt-controller; | |
342 | #interrupt-cells = <2>; | |
343 | }; | |
344 | ||
345 | gpio5: gpio@10015400 { | |
346 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
347 | reg = <0x10015400 0x100>; | |
ea336fa8 | 348 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
733f6cae MP |
349 | interrupts = <8>; |
350 | gpio-controller; | |
351 | #gpio-cells = <2>; | |
352 | interrupt-controller; | |
353 | #interrupt-cells = <2>; | |
354 | }; | |
355 | ||
356 | gpio6: gpio@10015500 { | |
357 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | |
358 | reg = <0x10015500 0x100>; | |
ea336fa8 | 359 | clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>; |
733f6cae MP |
360 | interrupts = <8>; |
361 | gpio-controller; | |
362 | #gpio-cells = <2>; | |
363 | interrupt-controller; | |
364 | #interrupt-cells = <2>; | |
365 | }; | |
9f0749e3 SH |
366 | }; |
367 | ||
6e228e80 AS |
368 | audmux: audmux@10016000 { |
369 | compatible = "fsl,imx27-audmux", "fsl,imx21-audmux"; | |
370 | reg = <0x10016000 0x1000>; | |
ea336fa8 | 371 | clocks = <&clks IMX27_CLK_DUMMY>; |
6e228e80 | 372 | clock-names = "audmux"; |
1c04ab0f | 373 | status = "disabled"; |
6e228e80 AS |
374 | }; |
375 | ||
5a2ecf0d | 376 | cspi3: spi@10017000 { |
9f0749e3 SH |
377 | #address-cells = <1>; |
378 | #size-cells = <0>; | |
379 | compatible = "fsl,imx27-cspi"; | |
380 | reg = <0x10017000 0x1000>; | |
381 | interrupts = <6>; | |
ea336fa8 AS |
382 | clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>, |
383 | <&clks IMX27_CLK_PER2_GATE>; | |
c20736f1 | 384 | clock-names = "ipg", "per"; |
9f0749e3 SH |
385 | status = "disabled"; |
386 | }; | |
387 | ||
ca26d041 | 388 | gpt4: timer@10019000 { |
afde1312 | 389 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
ca26d041 SH |
390 | reg = <0x10019000 0x1000>; |
391 | interrupts = <4>; | |
ea336fa8 AS |
392 | clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>, |
393 | <&clks IMX27_CLK_PER1_GATE>; | |
b700c119 | 394 | clock-names = "ipg", "per"; |
ca26d041 SH |
395 | }; |
396 | ||
397 | gpt5: timer@1001a000 { | |
afde1312 | 398 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
ca26d041 SH |
399 | reg = <0x1001a000 0x1000>; |
400 | interrupts = <3>; | |
ea336fa8 AS |
401 | clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>, |
402 | <&clks IMX27_CLK_PER1_GATE>; | |
b700c119 | 403 | clock-names = "ipg", "per"; |
ca26d041 SH |
404 | }; |
405 | ||
0c456cfa | 406 | uart5: serial@1001b000 { |
9f0749e3 SH |
407 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
408 | reg = <0x1001b000 0x1000>; | |
409 | interrupts = <49>; | |
ea336fa8 AS |
410 | clocks = <&clks IMX27_CLK_UART5_IPG_GATE>, |
411 | <&clks IMX27_CLK_PER1_GATE>; | |
c20736f1 | 412 | clock-names = "ipg", "per"; |
9f0749e3 SH |
413 | status = "disabled"; |
414 | }; | |
415 | ||
0c456cfa | 416 | uart6: serial@1001c000 { |
9f0749e3 SH |
417 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
418 | reg = <0x1001c000 0x1000>; | |
419 | interrupts = <48>; | |
ea336fa8 AS |
420 | clocks = <&clks IMX27_CLK_UART6_IPG_GATE>, |
421 | <&clks IMX27_CLK_PER1_GATE>; | |
c20736f1 | 422 | clock-names = "ipg", "per"; |
9f0749e3 SH |
423 | status = "disabled"; |
424 | }; | |
425 | ||
426 | i2c2: i2c@1001d000 { | |
427 | #address-cells = <1>; | |
428 | #size-cells = <0>; | |
5bdfba29 | 429 | compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; |
9f0749e3 SH |
430 | reg = <0x1001d000 0x1000>; |
431 | interrupts = <1>; | |
ea336fa8 | 432 | clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>; |
9f0749e3 SH |
433 | status = "disabled"; |
434 | }; | |
435 | ||
0e7b01aa AS |
436 | sdhci3: sdhci@1001e000 { |
437 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; | |
438 | reg = <0x1001e000 0x1000>; | |
439 | interrupts = <9>; | |
ea336fa8 AS |
440 | clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>, |
441 | <&clks IMX27_CLK_PER2_GATE>; | |
0e7b01aa AS |
442 | clock-names = "ipg", "per"; |
443 | dmas = <&dma 36>; | |
444 | dma-names = "rx-tx"; | |
445 | status = "disabled"; | |
446 | }; | |
447 | ||
ca26d041 | 448 | gpt6: timer@1001f000 { |
afde1312 | 449 | compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; |
ca26d041 SH |
450 | reg = <0x1001f000 0x1000>; |
451 | interrupts = <2>; | |
ea336fa8 AS |
452 | clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>, |
453 | <&clks IMX27_CLK_PER1_GATE>; | |
b700c119 | 454 | clock-names = "ipg", "per"; |
ca26d041 | 455 | }; |
3e24b05b FE |
456 | }; |
457 | ||
458 | aipi@10020000 { /* AIPI2 */ | |
459 | compatible = "fsl,aipi-bus", "simple-bus"; | |
460 | #address-cells = <1>; | |
461 | #size-cells = <1>; | |
462 | reg = <0x10020000 0x20000>; | |
463 | ranges; | |
464 | ||
5e57b241 MP |
465 | fb: fb@10021000 { |
466 | compatible = "fsl,imx27-fb", "fsl,imx21-fb"; | |
467 | interrupts = <61>; | |
468 | reg = <0x10021000 0x1000>; | |
ea336fa8 AS |
469 | clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>, |
470 | <&clks IMX27_CLK_LCDC_AHB_GATE>, | |
471 | <&clks IMX27_CLK_PER3_GATE>; | |
5e57b241 MP |
472 | clock-names = "ipg", "ahb", "per"; |
473 | status = "disabled"; | |
474 | }; | |
475 | ||
93b331ce | 476 | coda: coda@10023000 { |
71946619 | 477 | compatible = "fsl,imx27-vpu", "cnm,codadx6"; |
93b331ce AS |
478 | reg = <0x10023000 0x0200>; |
479 | interrupts = <53>; | |
ea336fa8 AS |
480 | clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>, |
481 | <&clks IMX27_CLK_VPU_AHB_GATE>; | |
93b331ce AS |
482 | clock-names = "per", "ahb"; |
483 | iram = <&iram>; | |
484 | }; | |
485 | ||
a2e502c2 AS |
486 | usbotg: usb@10024000 { |
487 | compatible = "fsl,imx27-usb"; | |
488 | reg = <0x10024000 0x200>; | |
489 | interrupts = <56>; | |
facf47ee PC |
490 | clocks = <&clks IMX27_CLK_USB_IPG_GATE>, |
491 | <&clks IMX27_CLK_USB_AHB_GATE>, | |
492 | <&clks IMX27_CLK_USB_DIV>; | |
493 | clock-names = "ipg", "ahb", "per"; | |
a2e502c2 | 494 | fsl,usbmisc = <&usbmisc 0>; |
a2e502c2 AS |
495 | status = "disabled"; |
496 | }; | |
497 | ||
498 | usbh1: usb@10024200 { | |
499 | compatible = "fsl,imx27-usb"; | |
500 | reg = <0x10024200 0x200>; | |
501 | interrupts = <54>; | |
facf47ee PC |
502 | clocks = <&clks IMX27_CLK_USB_IPG_GATE>, |
503 | <&clks IMX27_CLK_USB_AHB_GATE>, | |
504 | <&clks IMX27_CLK_USB_DIV>; | |
505 | clock-names = "ipg", "ahb", "per"; | |
a2e502c2 | 506 | fsl,usbmisc = <&usbmisc 1>; |
3ec481ed | 507 | dr_mode = "host"; |
a2e502c2 AS |
508 | status = "disabled"; |
509 | }; | |
510 | ||
511 | usbh2: usb@10024400 { | |
512 | compatible = "fsl,imx27-usb"; | |
513 | reg = <0x10024400 0x200>; | |
514 | interrupts = <55>; | |
facf47ee PC |
515 | clocks = <&clks IMX27_CLK_USB_IPG_GATE>, |
516 | <&clks IMX27_CLK_USB_AHB_GATE>, | |
517 | <&clks IMX27_CLK_USB_DIV>; | |
518 | clock-names = "ipg", "ahb", "per"; | |
a2e502c2 | 519 | fsl,usbmisc = <&usbmisc 2>; |
3ec481ed | 520 | dr_mode = "host"; |
a2e502c2 AS |
521 | status = "disabled"; |
522 | }; | |
523 | ||
524 | usbmisc: usbmisc@10024600 { | |
525 | #index-cells = <1>; | |
526 | compatible = "fsl,imx27-usbmisc"; | |
527 | reg = <0x10024600 0x200>; | |
a2e502c2 AS |
528 | }; |
529 | ||
e4b6a056 AS |
530 | sahara2: sahara@10025000 { |
531 | compatible = "fsl,imx27-sahara"; | |
532 | reg = <0x10025000 0x1000>; | |
533 | interrupts = <59>; | |
ea336fa8 AS |
534 | clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>, |
535 | <&clks IMX27_CLK_SAHARA_AHB_GATE>; | |
e4b6a056 AS |
536 | clock-names = "ipg", "ahb"; |
537 | }; | |
538 | ||
93b331ce AS |
539 | clks: ccm@10027000{ |
540 | compatible = "fsl,imx27-ccm"; | |
541 | reg = <0x10027000 0x1000>; | |
542 | #clock-cells = <1>; | |
543 | }; | |
544 | ||
d36afcd4 AS |
545 | iim: iim@10028000 { |
546 | compatible = "fsl,imx27-iim"; | |
547 | reg = <0x10028000 0x1000>; | |
548 | interrupts = <62>; | |
ea336fa8 | 549 | clocks = <&clks IMX27_CLK_IIM_IPG_GATE>; |
d36afcd4 AS |
550 | }; |
551 | ||
0c456cfa | 552 | fec: ethernet@1002b000 { |
9f0749e3 | 553 | compatible = "fsl,imx27-fec"; |
a29ef819 | 554 | reg = <0x1002b000 0x1000>; |
9f0749e3 | 555 | interrupts = <50>; |
ea336fa8 AS |
556 | clocks = <&clks IMX27_CLK_FEC_IPG_GATE>, |
557 | <&clks IMX27_CLK_FEC_AHB_GATE>; | |
c0b357c0 | 558 | clock-names = "ipg", "ahb"; |
9f0749e3 SH |
559 | status = "disabled"; |
560 | }; | |
561 | }; | |
7b7d6727 SH |
562 | |
563 | nfc: nand@d8000000 { | |
37787360 UKK |
564 | #address-cells = <1>; |
565 | #size-cells = <1>; | |
37787360 UKK |
566 | compatible = "fsl,imx27-nand"; |
567 | reg = <0xd8000000 0x1000>; | |
568 | interrupts = <29>; | |
ea336fa8 | 569 | clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>; |
37787360 UKK |
570 | status = "disabled"; |
571 | }; | |
ff1450f6 | 572 | |
0912f594 AS |
573 | weim: weim@d8002000 { |
574 | #address-cells = <2>; | |
575 | #size-cells = <1>; | |
576 | compatible = "fsl,imx27-weim"; | |
577 | reg = <0xd8002000 0x1000>; | |
ea336fa8 | 578 | clocks = <&clks IMX27_CLK_EMI_AHB_GATE>; |
0912f594 AS |
579 | ranges = < |
580 | 0 0 0xc0000000 0x08000000 | |
581 | 1 0 0xc8000000 0x08000000 | |
582 | 2 0 0xd0000000 0x02000000 | |
583 | 3 0 0xd2000000 0x02000000 | |
584 | 4 0 0xd4000000 0x02000000 | |
585 | 5 0 0xd6000000 0x02000000 | |
586 | >; | |
587 | status = "disabled"; | |
588 | }; | |
589 | ||
ff1450f6 AS |
590 | iram: iram@ffff4c00 { |
591 | compatible = "mmio-sram"; | |
592 | reg = <0xffff4c00 0xb400>; | |
593 | }; | |
9f0749e3 SH |
594 | }; |
595 | }; |