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Merge tag 'topic/designware-baytrail-2017-03-02' of git://anongit.freedesktop.org...
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx28.dtsi
CommitLineData
bc3a59c1
DA		 1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
25fc228e 12#include <dt-bindings/gpio/gpio.h>
bc3875f1 13#include "imx28-pinfunc.h"
bc3a59c1
DA		 14
15/ {
7f107887
FE		 16 #address-cells = <1>;
17 #size-cells = <1>;
18
bc3a59c1 19 interrupt-parent = <&icoll>;
a971c554
FE		 20 /*
21 * The decompressor and also some bootloaders rely on a
22 * pre-existing /chosen node to be available to insert the
23 * command line and merge other ATAGS info.
24 * Also for U-Boot there must be a pre-existing /memory node.
25 */
26 chosen {};
27 memory { device_type = "memory"; reg = <0 0>; };
bc3a59c1 28
ce4c6f9b 29 aliases {
6bf6eb09
FE		 30 ethernet0 = &mac0;
31 ethernet1 = &mac1;
ce4c6f9b
SG		 32 gpio0 = &gpio0;
33 gpio1 = &gpio1;
34 gpio2 = &gpio2;
35 gpio3 = &gpio3;
36 gpio4 = &gpio4;
530f1d41
SG		 37 saif0 = &saif0;
38 saif1 = &saif1;
80d969e4
FE		 39 serial0 = &auart0;
40 serial1 = &auart1;
41 serial2 = &auart2;
42 serial3 = &auart3;
43 serial4 = &auart4;
6bf6eb09
FE		 44 spi0 = &ssp1;
45 spi1 = &ssp2;
1f35cc6a
PC		 46 usbphy0 = &usbphy0;
47 usbphy1 = &usbphy1;
ce4c6f9b
SG		 48 };
49
bc3a59c1 50 cpus {
d447dd88 51 #address-cells = <1>;
7925e89f
LP		 52 #size-cells = <0>;
53
d447dd88 54 cpu@0 {
7925e89f
LP		 55 compatible = "arm,arm926ej-s";
56 device_type = "cpu";
d447dd88 57 reg = <0>;
bc3a59c1
DA		 58 };
59 };
60
61 apb@80000000 {
62 compatible = "simple-bus";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 reg = <0x80000000 0x80000>;
66 ranges;
67
68 apbh@80000000 {
69 compatible = "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 reg = <0x80000000 0x3c900>;
73 ranges;
74
75 icoll: interrupt-controller@80000000 {
83a84efc 76 compatible = "fsl,imx28-icoll", "fsl,icoll";
bc3a59c1
DA		 77 interrupt-controller;
78 #interrupt-cells = <1>;
79 reg = <0x80000000 0x2000>;
80 };
81
296f8cd3 82 hsadc: hsadc@80002000 {
0f06cde7 83 reg = <0x80002000 0x2000>;
7f2b9288 84 interrupts = <13>;
f30fb03d
SG		 85 dmas = <&dma_apbh 12>;
86 dma-names = "rx";
bc3a59c1
DA		 87 status = "disabled";
88 };
89
f30fb03d 90 dma_apbh: dma-apbh@80004000 {
84f3570a 91 compatible = "fsl,imx28-dma-apbh";
0f06cde7 92 reg = <0x80004000 0x2000>;
f30fb03d
SG		 93 interrupts = <82 83 84 85
94 88 88 88 88
95 88 88 88 88
96 87 86 0 0>;
97 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
98 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
99 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
100 "hsadc", "lcdif", "empty", "empty";
101 #dma-cells = <1>;
102 dma-channels = <16>;
b598b9f3 103 clocks = <&clks 25>;
bc3a59c1
DA		 104 };
105
296f8cd3 106 perfmon: perfmon@80006000 {
0f06cde7 107 reg = <0x80006000 0x800>;
bc3a59c1
DA		 108 interrupts = <27>;
109 status = "disabled";
110 };
111
296f8cd3 112 gpmi: gpmi-nand@8000c000 {
7a8e5149
HS		 113 compatible = "fsl,imx28-gpmi-nand";
114 #address-cells = <1>;
115 #size-cells = <1>;
0f06cde7 116 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
7a8e5149 117 reg-names = "gpmi-nand", "bch";
7f2b9288
SG		 118 interrupts = <41>;
119 interrupt-names = "bch";
b598b9f3 120 clocks = <&clks 50>;
b6442559 121 clock-names = "gpmi_io";
f30fb03d
SG		 122 dmas = <&dma_apbh 4>;
123 dma-names = "rx-tx";
bc3a59c1
DA		 124 status = "disabled";
125 };
126
127 ssp0: ssp@80010000 {
41bf5706
MR		 128 #address-cells = <1>;
129 #size-cells = <0>;
0f06cde7 130 reg = <0x80010000 0x2000>;
7f2b9288 131 interrupts = <96>;
b598b9f3 132 clocks = <&clks 46>;
f30fb03d
SG		 133 dmas = <&dma_apbh 0>;
134 dma-names = "rx-tx";
bc3a59c1
DA		 135 status = "disabled";
136 };
137
138 ssp1: ssp@80012000 {
41bf5706
MR		 139 #address-cells = <1>;
140 #size-cells = <0>;
0f06cde7 141 reg = <0x80012000 0x2000>;
7f2b9288 142 interrupts = <97>;
b598b9f3 143 clocks = <&clks 47>;
f30fb03d
SG		 144 dmas = <&dma_apbh 1>;
145 dma-names = "rx-tx";
bc3a59c1
DA		 146 status = "disabled";
147 };
148
149 ssp2: ssp@80014000 {
41bf5706
MR		 150 #address-cells = <1>;
151 #size-cells = <0>;
0f06cde7 152 reg = <0x80014000 0x2000>;
7f2b9288 153 interrupts = <98>;
b598b9f3 154 clocks = <&clks 48>;
f30fb03d
SG		 155 dmas = <&dma_apbh 2>;
156 dma-names = "rx-tx";
bc3a59c1
DA		 157 status = "disabled";
158 };
159
160 ssp3: ssp@80016000 {
41bf5706
MR		 161 #address-cells = <1>;
162 #size-cells = <0>;
0f06cde7 163 reg = <0x80016000 0x2000>;
7f2b9288 164 interrupts = <99>;
b598b9f3 165 clocks = <&clks 49>;
f30fb03d
SG		 166 dmas = <&dma_apbh 3>;
167 dma-names = "rx-tx";
bc3a59c1
DA		 168 status = "disabled";
169 };
170
296f8cd3 171 pinctrl: pinctrl@80018000 {
bc3a59c1
DA		 172 #address-cells = <1>;
173 #size-cells = <0>;
ce4c6f9b 174 compatible = "fsl,imx28-pinctrl", "simple-bus";
0f06cde7 175 reg = <0x80018000 0x2000>;
bc3a59c1 176
ce4c6f9b
SG		 177 gpio0: gpio@0 {
178 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
e57609aa 179 reg = <0>;
ce4c6f9b
SG		 180 interrupts = <127>;
181 gpio-controller;
182 #gpio-cells = <2>;
183 interrupt-controller;
184 #interrupt-cells = <2>;
185 };
186
187 gpio1: gpio@1 {
188 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
e57609aa 189 reg = <1>;
ce4c6f9b
SG		 190 interrupts = <126>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 interrupt-controller;
194 #interrupt-cells = <2>;
195 };
196
197 gpio2: gpio@2 {
198 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
e57609aa 199 reg = <2>;
ce4c6f9b
SG		 200 interrupts = <125>;
201 gpio-controller;
202 #gpio-cells = <2>;
203 interrupt-controller;
204 #interrupt-cells = <2>;
205 };
206
207 gpio3: gpio@3 {
208 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
e57609aa 209 reg = <3>;
ce4c6f9b
SG		 210 interrupts = <124>;
211 gpio-controller;
212 #gpio-cells = <2>;
213 interrupt-controller;
214 #interrupt-cells = <2>;
215 };
216
217 gpio4: gpio@4 {
218 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
e57609aa 219 reg = <4>;
ce4c6f9b
SG		 220 interrupts = <123>;
221 gpio-controller;
222 #gpio-cells = <2>;
223 interrupt-controller;
224 #interrupt-cells = <2>;
225 };
226
bc3a59c1
DA		 227 duart_pins_a: duart@0 {
228 reg = <0>;
f14da767 229 fsl,pinmux-ids = <
bc3875f1
LW		 230 MX28_PAD_PWM0__DUART_RX
231 MX28_PAD_PWM1__DUART_TX
f14da767 232 >;
4191c340
LW		 233 fsl,drive-strength = <MXS_DRIVE_4mA>;
234 fsl,voltage = <MXS_VOLTAGE_HIGH>;
235 fsl,pull-up = <MXS_PULL_DISABLE>;
bc3a59c1
DA		 236 };
237
8385e7c1
MR		 238 duart_pins_b: duart@1 {
239 reg = <1>;
f14da767 240 fsl,pinmux-ids = <
bc3875f1
LW		 241 MX28_PAD_AUART0_CTS__DUART_RX
242 MX28_PAD_AUART0_RTS__DUART_TX
f14da767 243 >;
4191c340
LW		 244 fsl,drive-strength = <MXS_DRIVE_4mA>;
245 fsl,voltage = <MXS_VOLTAGE_HIGH>;
246 fsl,pull-up = <MXS_PULL_DISABLE>;
8385e7c1
MR		 247 };
248
e1a4d18f
SG		 249 duart_4pins_a: duart-4pins@0 {
250 reg = <0>;
251 fsl,pinmux-ids = <
bc3875f1
LW		 252 MX28_PAD_AUART0_CTS__DUART_RX
253 MX28_PAD_AUART0_RTS__DUART_TX
254 MX28_PAD_AUART0_RX__DUART_CTS
255 MX28_PAD_AUART0_TX__DUART_RTS
e1a4d18f 256 >;
4191c340
LW		 257 fsl,drive-strength = <MXS_DRIVE_4mA>;
258 fsl,voltage = <MXS_VOLTAGE_HIGH>;
259 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 260 };
261
7a8e5149
HS		 262 gpmi_pins_a: gpmi-nand@0 {
263 reg = <0>;
f14da767 264 fsl,pinmux-ids = <
bc3875f1
LW		 265 MX28_PAD_GPMI_D00__GPMI_D0
266 MX28_PAD_GPMI_D01__GPMI_D1
267 MX28_PAD_GPMI_D02__GPMI_D2
268 MX28_PAD_GPMI_D03__GPMI_D3
269 MX28_PAD_GPMI_D04__GPMI_D4
270 MX28_PAD_GPMI_D05__GPMI_D5
271 MX28_PAD_GPMI_D06__GPMI_D6
272 MX28_PAD_GPMI_D07__GPMI_D7
273 MX28_PAD_GPMI_CE0N__GPMI_CE0N
274 MX28_PAD_GPMI_RDY0__GPMI_READY0
275 MX28_PAD_GPMI_RDN__GPMI_RDN
276 MX28_PAD_GPMI_WRN__GPMI_WRN
277 MX28_PAD_GPMI_ALE__GPMI_ALE
278 MX28_PAD_GPMI_CLE__GPMI_CLE
279 MX28_PAD_GPMI_RESETN__GPMI_RESETN
f14da767 280 >;
4191c340
LW		 281 fsl,drive-strength = <MXS_DRIVE_4mA>;
282 fsl,voltage = <MXS_VOLTAGE_HIGH>;
283 fsl,pull-up = <MXS_PULL_DISABLE>;
7a8e5149
HS		 284 };
285
286 gpmi_status_cfg: gpmi-status-cfg {
f14da767 287 fsl,pinmux-ids = <
bc3875f1
LW		 288 MX28_PAD_GPMI_RDN__GPMI_RDN
289 MX28_PAD_GPMI_WRN__GPMI_WRN
290 MX28_PAD_GPMI_RESETN__GPMI_RESETN
f14da767 291 >;
4191c340 292 fsl,drive-strength = <MXS_DRIVE_12mA>;
7a8e5149
HS		 293 };
294
80d969e4
FE		 295 auart0_pins_a: auart0@0 {
296 reg = <0>;
f14da767 297 fsl,pinmux-ids = <
bc3875f1
LW		 298 MX28_PAD_AUART0_RX__AUART0_RX
299 MX28_PAD_AUART0_TX__AUART0_TX
300 MX28_PAD_AUART0_CTS__AUART0_CTS
301 MX28_PAD_AUART0_RTS__AUART0_RTS
f14da767 302 >;
4191c340
LW		 303 fsl,drive-strength = <MXS_DRIVE_4mA>;
304 fsl,voltage = <MXS_VOLTAGE_HIGH>;
305 fsl,pull-up = <MXS_PULL_DISABLE>;
8fa62e11
MV		 306 };
307
308 auart0_2pins_a: auart0-2pins@0 {
309 reg = <0>;
310 fsl,pinmux-ids = <
bc3875f1
LW		 311 MX28_PAD_AUART0_RX__AUART0_RX
312 MX28_PAD_AUART0_TX__AUART0_TX
8fa62e11 313 >;
4191c340
LW		 314 fsl,drive-strength = <MXS_DRIVE_4mA>;
315 fsl,voltage = <MXS_VOLTAGE_HIGH>;
316 fsl,pull-up = <MXS_PULL_DISABLE>;
80d969e4
FE		 317 };
318
e1a4d18f
SG		 319 auart1_pins_a: auart1@0 {
320 reg = <0>;
321 fsl,pinmux-ids = <
bc3875f1
LW		 322 MX28_PAD_AUART1_RX__AUART1_RX
323 MX28_PAD_AUART1_TX__AUART1_TX
324 MX28_PAD_AUART1_CTS__AUART1_CTS
325 MX28_PAD_AUART1_RTS__AUART1_RTS
e1a4d18f 326 >;
4191c340
LW		 327 fsl,drive-strength = <MXS_DRIVE_4mA>;
328 fsl,voltage = <MXS_VOLTAGE_HIGH>;
329 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 330 };
331
3143bbb4
SG		 332 auart1_2pins_a: auart1-2pins@0 {
333 reg = <0>;
334 fsl,pinmux-ids = <
bc3875f1
LW		 335 MX28_PAD_AUART1_RX__AUART1_RX
336 MX28_PAD_AUART1_TX__AUART1_TX
3143bbb4 337 >;
4191c340
LW		 338 fsl,drive-strength = <MXS_DRIVE_4mA>;
339 fsl,voltage = <MXS_VOLTAGE_HIGH>;
340 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 341 };
342
343 auart2_2pins_a: auart2-2pins@0 {
344 reg = <0>;
345 fsl,pinmux-ids = <
bc3875f1
LW		 346 MX28_PAD_SSP2_SCK__AUART2_RX
347 MX28_PAD_SSP2_MOSI__AUART2_TX
3143bbb4 348 >;
4191c340
LW		 349 fsl,drive-strength = <MXS_DRIVE_4mA>;
350 fsl,voltage = <MXS_VOLTAGE_HIGH>;
351 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 352 };
353
f8040cf5
EB		 354 auart2_2pins_b: auart2-2pins@1 {
355 reg = <1>;
356 fsl,pinmux-ids = <
bc3875f1
LW		 357 MX28_PAD_AUART2_RX__AUART2_RX
358 MX28_PAD_AUART2_TX__AUART2_TX
f8040cf5 359 >;
4191c340
LW		 360 fsl,drive-strength = <MXS_DRIVE_4mA>;
361 fsl,voltage = <MXS_VOLTAGE_HIGH>;
362 fsl,pull-up = <MXS_PULL_DISABLE>;
f8040cf5
EB		 363 };
364
cd0214c3
AM		 365 auart2_pins_a: auart2-pins@0 {
366 reg = <0>;
367 fsl,pinmux-ids = <
368 MX28_PAD_AUART2_RX__AUART2_RX
369 MX28_PAD_AUART2_TX__AUART2_TX
370 MX28_PAD_AUART2_CTS__AUART2_CTS
371 MX28_PAD_AUART2_RTS__AUART2_RTS
372 >;
373 fsl,drive-strength = <MXS_DRIVE_4mA>;
374 fsl,voltage = <MXS_VOLTAGE_HIGH>;
375 fsl,pull-up = <MXS_PULL_DISABLE>;
376 };
377
80d969e4
FE		 378 auart3_pins_a: auart3@0 {
379 reg = <0>;
f14da767 380 fsl,pinmux-ids = <
bc3875f1
LW		 381 MX28_PAD_AUART3_RX__AUART3_RX
382 MX28_PAD_AUART3_TX__AUART3_TX
383 MX28_PAD_AUART3_CTS__AUART3_CTS
384 MX28_PAD_AUART3_RTS__AUART3_RTS
f14da767 385 >;
4191c340
LW		 386 fsl,drive-strength = <MXS_DRIVE_4mA>;
387 fsl,voltage = <MXS_VOLTAGE_HIGH>;
388 fsl,pull-up = <MXS_PULL_DISABLE>;
80d969e4
FE		 389 };
390
3143bbb4
SG		 391 auart3_2pins_a: auart3-2pins@0 {
392 reg = <0>;
393 fsl,pinmux-ids = <
bc3875f1
LW		 394 MX28_PAD_SSP2_MISO__AUART3_RX
395 MX28_PAD_SSP2_SS0__AUART3_TX
3143bbb4 396 >;
4191c340
LW		 397 fsl,drive-strength = <MXS_DRIVE_4mA>;
398 fsl,voltage = <MXS_VOLTAGE_HIGH>;
399 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 400 };
401
4812e746
EB		 402 auart3_2pins_b: auart3-2pins@1 {
403 reg = <1>;
404 fsl,pinmux-ids = <
bc3875f1
LW		 405 MX28_PAD_AUART3_RX__AUART3_RX
406 MX28_PAD_AUART3_TX__AUART3_TX
4812e746 407 >;
4191c340
LW		 408 fsl,drive-strength = <MXS_DRIVE_4mA>;
409 fsl,voltage = <MXS_VOLTAGE_HIGH>;
410 fsl,pull-up = <MXS_PULL_DISABLE>;
4812e746
EB		 411 };
412
33678d12
EB		 413 auart4_2pins_a: auart4@0 {
414 reg = <0>;
415 fsl,pinmux-ids = <
bc3875f1
LW		 416 MX28_PAD_SSP3_SCK__AUART4_TX
417 MX28_PAD_SSP3_MOSI__AUART4_RX
33678d12 418 >;
4191c340
LW		 419 fsl,drive-strength = <MXS_DRIVE_4mA>;
420 fsl,voltage = <MXS_VOLTAGE_HIGH>;
421 fsl,pull-up = <MXS_PULL_DISABLE>;
33678d12
EB		 422 };
423
cfa1dd99
MR		 424 auart4_2pins_b: auart4@1 {
425 reg = <1>;
426 fsl,pinmux-ids = <
427 MX28_PAD_AUART0_CTS__AUART4_RX
428 MX28_PAD_AUART0_RTS__AUART4_TX
429 >;
430 fsl,drive-strength = <MXS_DRIVE_4mA>;
431 fsl,voltage = <MXS_VOLTAGE_HIGH>;
432 fsl,pull-up = <MXS_PULL_DISABLE>;
433 };
434
bc3a59c1
DA		 435 mac0_pins_a: mac0@0 {
436 reg = <0>;
f14da767 437 fsl,pinmux-ids = <
bc3875f1
LW		 438 MX28_PAD_ENET0_MDC__ENET0_MDC
439 MX28_PAD_ENET0_MDIO__ENET0_MDIO
440 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
441 MX28_PAD_ENET0_RXD0__ENET0_RXD0
442 MX28_PAD_ENET0_RXD1__ENET0_RXD1
443 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
444 MX28_PAD_ENET0_TXD0__ENET0_TXD0
445 MX28_PAD_ENET0_TXD1__ENET0_TXD1
446 MX28_PAD_ENET_CLK__CLKCTRL_ENET
f14da767 447 >;
4191c340
LW		 448 fsl,drive-strength = <MXS_DRIVE_8mA>;
449 fsl,voltage = <MXS_VOLTAGE_HIGH>;
450 fsl,pull-up = <MXS_PULL_ENABLE>;
bc3a59c1
DA		 451 };
452
9eb7db1c
UKK		 453 mac0_pins_b: mac0@1 {
454 reg = <1>;
455 fsl,pinmux-ids = <
456 MX28_PAD_ENET0_MDC__ENET0_MDC
457 MX28_PAD_ENET0_MDIO__ENET0_MDIO
458 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
459 MX28_PAD_ENET0_RXD0__ENET0_RXD0
460 MX28_PAD_ENET0_RXD1__ENET0_RXD1
461 MX28_PAD_ENET0_RXD2__ENET0_RXD2
462 MX28_PAD_ENET0_RXD3__ENET0_RXD3
463 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
464 MX28_PAD_ENET0_TXD0__ENET0_TXD0
465 MX28_PAD_ENET0_TXD1__ENET0_TXD1
466 MX28_PAD_ENET0_TXD2__ENET0_TXD2
467 MX28_PAD_ENET0_TXD3__ENET0_TXD3
468 MX28_PAD_ENET_CLK__CLKCTRL_ENET
469 MX28_PAD_ENET0_COL__ENET0_COL
470 MX28_PAD_ENET0_CRS__ENET0_CRS
471 MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
472 MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
473 >;
474 fsl,drive-strength = <MXS_DRIVE_8mA>;
475 fsl,voltage = <MXS_VOLTAGE_HIGH>;
476 fsl,pull-up = <MXS_PULL_ENABLE>;
477 };
478
bc3a59c1
DA		 479 mac1_pins_a: mac1@0 {
480 reg = <0>;
f14da767 481 fsl,pinmux-ids = <
bc3875f1
LW		 482 MX28_PAD_ENET0_CRS__ENET1_RX_EN
483 MX28_PAD_ENET0_RXD2__ENET1_RXD0
484 MX28_PAD_ENET0_RXD3__ENET1_RXD1
485 MX28_PAD_ENET0_COL__ENET1_TX_EN
486 MX28_PAD_ENET0_TXD2__ENET1_TXD0
487 MX28_PAD_ENET0_TXD3__ENET1_TXD1
f14da767 488 >;
4191c340
LW		 489 fsl,drive-strength = <MXS_DRIVE_8mA>;
490 fsl,voltage = <MXS_VOLTAGE_HIGH>;
491 fsl,pull-up = <MXS_PULL_ENABLE>;
bc3a59c1 492 };
35d23047
SG		 493
494 mmc0_8bit_pins_a: mmc0-8bit@0 {
495 reg = <0>;
f14da767 496 fsl,pinmux-ids = <
bc3875f1
LW		 497 MX28_PAD_SSP0_DATA0__SSP0_D0
498 MX28_PAD_SSP0_DATA1__SSP0_D1
499 MX28_PAD_SSP0_DATA2__SSP0_D2
500 MX28_PAD_SSP0_DATA3__SSP0_D3
501 MX28_PAD_SSP0_DATA4__SSP0_D4
502 MX28_PAD_SSP0_DATA5__SSP0_D5
503 MX28_PAD_SSP0_DATA6__SSP0_D6
504 MX28_PAD_SSP0_DATA7__SSP0_D7
505 MX28_PAD_SSP0_CMD__SSP0_CMD
506 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
507 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 508 >;
4191c340
LW		 509 fsl,drive-strength = <MXS_DRIVE_8mA>;
510 fsl,voltage = <MXS_VOLTAGE_HIGH>;
511 fsl,pull-up = <MXS_PULL_ENABLE>;
35d23047
SG		 512 };
513
8385e7c1
MR		 514 mmc0_4bit_pins_a: mmc0-4bit@0 {
515 reg = <0>;
f14da767 516 fsl,pinmux-ids = <
bc3875f1
LW		 517 MX28_PAD_SSP0_DATA0__SSP0_D0
518 MX28_PAD_SSP0_DATA1__SSP0_D1
519 MX28_PAD_SSP0_DATA2__SSP0_D2
520 MX28_PAD_SSP0_DATA3__SSP0_D3
521 MX28_PAD_SSP0_CMD__SSP0_CMD
522 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
523 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 524 >;
4191c340
LW		 525 fsl,drive-strength = <MXS_DRIVE_8mA>;
526 fsl,voltage = <MXS_VOLTAGE_HIGH>;
527 fsl,pull-up = <MXS_PULL_ENABLE>;
8385e7c1
MR		 528 };
529
35d23047 530 mmc0_cd_cfg: mmc0-cd-cfg {
f14da767 531 fsl,pinmux-ids = <
bc3875f1 532 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
f14da767 533 >;
4191c340 534 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047
SG		 535 };
536
537 mmc0_sck_cfg: mmc0-sck-cfg {
f14da767 538 fsl,pinmux-ids = <
bc3875f1 539 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 540 >;
4191c340
LW		 541 fsl,drive-strength = <MXS_DRIVE_12mA>;
542 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047 543 };
2a96e391 544
77d6386b
MKB		 545 mmc1_4bit_pins_a: mmc1-4bit@0 {
546 reg = <0>;
547 fsl,pinmux-ids = <
548 MX28_PAD_GPMI_D00__SSP1_D0
549 MX28_PAD_GPMI_D01__SSP1_D1
550 MX28_PAD_GPMI_D02__SSP1_D2
551 MX28_PAD_GPMI_D03__SSP1_D3
552 MX28_PAD_GPMI_RDY1__SSP1_CMD
553 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
554 MX28_PAD_GPMI_WRN__SSP1_SCK
555 >;
556 fsl,drive-strength = <MXS_DRIVE_8mA>;
557 fsl,voltage = <MXS_VOLTAGE_HIGH>;
558 fsl,pull-up = <MXS_PULL_ENABLE>;
559 };
560
561 mmc1_cd_cfg: mmc1-cd-cfg {
562 fsl,pinmux-ids = <
563 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
564 >;
565 fsl,pull-up = <MXS_PULL_DISABLE>;
566 };
567
568 mmc1_sck_cfg: mmc1-sck-cfg {
569 fsl,pinmux-ids = <
570 MX28_PAD_GPMI_WRN__SSP1_SCK
571 >;
572 fsl,drive-strength = <MXS_DRIVE_12mA>;
573 fsl,pull-up = <MXS_PULL_DISABLE>;
574 };
575
576
5550e8e9
MV		 577 mmc2_4bit_pins_a: mmc2-4bit@0 {
578 reg = <0>;
579 fsl,pinmux-ids = <
580 MX28_PAD_SSP0_DATA4__SSP2_D0
581 MX28_PAD_SSP1_SCK__SSP2_D1
582 MX28_PAD_SSP1_CMD__SSP2_D2
583 MX28_PAD_SSP0_DATA5__SSP2_D3
584 MX28_PAD_SSP0_DATA6__SSP2_CMD
585 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
586 MX28_PAD_SSP0_DATA7__SSP2_SCK
587 >;
588 fsl,drive-strength = <MXS_DRIVE_8mA>;
589 fsl,voltage = <MXS_VOLTAGE_HIGH>;
590 fsl,pull-up = <MXS_PULL_ENABLE>;
591 };
592
593 mmc2_cd_cfg: mmc2-cd-cfg {
594 fsl,pinmux-ids = <
595 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
596 >;
597 fsl,pull-up = <MXS_PULL_DISABLE>;
598 };
599
600 mmc2_sck_cfg: mmc2-sck-cfg {
601 fsl,pinmux-ids = <
602 MX28_PAD_SSP0_DATA7__SSP2_SCK
603 >;
604 fsl,drive-strength = <MXS_DRIVE_12mA>;
605 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047 606 };
2a96e391
SG		 607
608 i2c0_pins_a: i2c0@0 {
609 reg = <0>;
f14da767 610 fsl,pinmux-ids = <
bc3875f1
LW		 611 MX28_PAD_I2C0_SCL__I2C0_SCL
612 MX28_PAD_I2C0_SDA__I2C0_SDA
f14da767 613 >;
4191c340
LW		 614 fsl,drive-strength = <MXS_DRIVE_8mA>;
615 fsl,voltage = <MXS_VOLTAGE_HIGH>;
616 fsl,pull-up = <MXS_PULL_ENABLE>;
2a96e391 617 };
530f1d41 618
5c697ea2
MR		 619 i2c0_pins_b: i2c0@1 {
620 reg = <1>;
621 fsl,pinmux-ids = <
bc3875f1
LW		 622 MX28_PAD_AUART0_RX__I2C0_SCL
623 MX28_PAD_AUART0_TX__I2C0_SDA
5c697ea2 624 >;
4191c340
LW		 625 fsl,drive-strength = <MXS_DRIVE_8mA>;
626 fsl,voltage = <MXS_VOLTAGE_HIGH>;
627 fsl,pull-up = <MXS_PULL_ENABLE>;
5c697ea2
MR		 628 };
629
de7e934f
MR		 630 i2c1_pins_a: i2c1@0 {
631 reg = <0>;
632 fsl,pinmux-ids = <
bc3875f1
LW		 633 MX28_PAD_PWM0__I2C1_SCL
634 MX28_PAD_PWM1__I2C1_SDA
de7e934f 635 >;
4191c340
LW		 636 fsl,drive-strength = <MXS_DRIVE_8mA>;
637 fsl,voltage = <MXS_VOLTAGE_HIGH>;
638 fsl,pull-up = <MXS_PULL_ENABLE>;
de7e934f
MR		 639 };
640
17c63dd0
UKK		 641 i2c1_pins_b: i2c1@1 {
642 reg = <1>;
643 fsl,pinmux-ids = <
644 MX28_PAD_AUART2_CTS__I2C1_SCL
645 MX28_PAD_AUART2_RTS__I2C1_SDA
646 >;
647 fsl,drive-strength = <MXS_DRIVE_8mA>;
648 fsl,voltage = <MXS_VOLTAGE_HIGH>;
649 fsl,pull-up = <MXS_PULL_ENABLE>;
650 };
651
530f1d41
SG		 652 saif0_pins_a: saif0@0 {
653 reg = <0>;
f14da767 654 fsl,pinmux-ids = <
bc3875f1
LW		 655 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
656 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
657 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
658 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
f14da767 659 >;
4191c340
LW		 660 fsl,drive-strength = <MXS_DRIVE_12mA>;
661 fsl,voltage = <MXS_VOLTAGE_HIGH>;
662 fsl,pull-up = <MXS_PULL_ENABLE>;
530f1d41
SG		 663 };
664
2e1dd9fc
LW		 665 saif0_pins_b: saif0@1 {
666 reg = <1>;
667 fsl,pinmux-ids = <
bc3875f1
LW		 668 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
669 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
670 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
2e1dd9fc 671 >;
4191c340
LW		 672 fsl,drive-strength = <MXS_DRIVE_12mA>;
673 fsl,voltage = <MXS_VOLTAGE_HIGH>;
674 fsl,pull-up = <MXS_PULL_ENABLE>;
2e1dd9fc
LW		 675 };
676
530f1d41
SG		 677 saif1_pins_a: saif1@0 {
678 reg = <0>;
f14da767 679 fsl,pinmux-ids = <
bc3875f1 680 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
f14da767 681 >;
4191c340
LW		 682 fsl,drive-strength = <MXS_DRIVE_12mA>;
683 fsl,voltage = <MXS_VOLTAGE_HIGH>;
684 fsl,pull-up = <MXS_PULL_ENABLE>;
530f1d41 685 };
52f7176b 686
e1a4d18f
SG		 687 pwm0_pins_a: pwm0@0 {
688 reg = <0>;
689 fsl,pinmux-ids = <
bc3875f1 690 MX28_PAD_PWM0__PWM_0
e1a4d18f 691 >;
4191c340
LW		 692 fsl,drive-strength = <MXS_DRIVE_4mA>;
693 fsl,voltage = <MXS_VOLTAGE_HIGH>;
694 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 695 };
696
52f7176b
SG		 697 pwm2_pins_a: pwm2@0 {
698 reg = <0>;
699 fsl,pinmux-ids = <
bc3875f1 700 MX28_PAD_PWM2__PWM_2
52f7176b 701 >;
4191c340
LW		 702 fsl,drive-strength = <MXS_DRIVE_4mA>;
703 fsl,voltage = <MXS_VOLTAGE_HIGH>;
704 fsl,pull-up = <MXS_PULL_DISABLE>;
52f7176b 705 };
a915ee42 706
2bde51cb
JB		 707 pwm3_pins_a: pwm3@0 {
708 reg = <0>;
709 fsl,pinmux-ids = <
bc3875f1 710 MX28_PAD_PWM3__PWM_3
2bde51cb 711 >;
4191c340
LW		 712 fsl,drive-strength = <MXS_DRIVE_4mA>;
713 fsl,voltage = <MXS_VOLTAGE_HIGH>;
714 fsl,pull-up = <MXS_PULL_DISABLE>;
2bde51cb
JB		 715 };
716
d248620c
MR		 717 pwm3_pins_b: pwm3@1 {
718 reg = <1>;
719 fsl,pinmux-ids = <
bc3875f1 720 MX28_PAD_SAIF0_MCLK__PWM_3
d248620c 721 >;
4191c340
LW		 722 fsl,drive-strength = <MXS_DRIVE_4mA>;
723 fsl,voltage = <MXS_VOLTAGE_HIGH>;
724 fsl,pull-up = <MXS_PULL_DISABLE>;
d248620c
MR		 725 };
726
2f44211f
MR		 727 pwm4_pins_a: pwm4@0 {
728 reg = <0>;
729 fsl,pinmux-ids = <
bc3875f1 730 MX28_PAD_PWM4__PWM_4
2f44211f 731 >;
4191c340
LW		 732 fsl,drive-strength = <MXS_DRIVE_4mA>;
733 fsl,voltage = <MXS_VOLTAGE_HIGH>;
734 fsl,pull-up = <MXS_PULL_DISABLE>;
2f44211f
MR		 735 };
736
a915ee42
SG		 737 lcdif_24bit_pins_a: lcdif-24bit@0 {
738 reg = <0>;
739 fsl,pinmux-ids = <
bc3875f1
LW		 740 MX28_PAD_LCD_D00__LCD_D0
741 MX28_PAD_LCD_D01__LCD_D1
742 MX28_PAD_LCD_D02__LCD_D2
743 MX28_PAD_LCD_D03__LCD_D3
744 MX28_PAD_LCD_D04__LCD_D4
745 MX28_PAD_LCD_D05__LCD_D5
746 MX28_PAD_LCD_D06__LCD_D6
747 MX28_PAD_LCD_D07__LCD_D7
748 MX28_PAD_LCD_D08__LCD_D8
749 MX28_PAD_LCD_D09__LCD_D9
750 MX28_PAD_LCD_D10__LCD_D10
751 MX28_PAD_LCD_D11__LCD_D11
752 MX28_PAD_LCD_D12__LCD_D12
753 MX28_PAD_LCD_D13__LCD_D13
754 MX28_PAD_LCD_D14__LCD_D14
755 MX28_PAD_LCD_D15__LCD_D15
756 MX28_PAD_LCD_D16__LCD_D16
757 MX28_PAD_LCD_D17__LCD_D17
758 MX28_PAD_LCD_D18__LCD_D18
759 MX28_PAD_LCD_D19__LCD_D19
760 MX28_PAD_LCD_D20__LCD_D20
761 MX28_PAD_LCD_D21__LCD_D21
762 MX28_PAD_LCD_D22__LCD_D22
763 MX28_PAD_LCD_D23__LCD_D23
a915ee42 764 >;
4191c340
LW		 765 fsl,drive-strength = <MXS_DRIVE_4mA>;
766 fsl,voltage = <MXS_VOLTAGE_HIGH>;
767 fsl,pull-up = <MXS_PULL_DISABLE>;
a915ee42 768 };
6ca44acf 769
ec985eb2
DC		 770 lcdif_18bit_pins_a: lcdif-18bit@0 {
771 reg = <0>;
772 fsl,pinmux-ids = <
773 MX28_PAD_LCD_D00__LCD_D0
774 MX28_PAD_LCD_D01__LCD_D1
775 MX28_PAD_LCD_D02__LCD_D2
776 MX28_PAD_LCD_D03__LCD_D3
777 MX28_PAD_LCD_D04__LCD_D4
778 MX28_PAD_LCD_D05__LCD_D5
779 MX28_PAD_LCD_D06__LCD_D6
780 MX28_PAD_LCD_D07__LCD_D7
781 MX28_PAD_LCD_D08__LCD_D8
782 MX28_PAD_LCD_D09__LCD_D9
783 MX28_PAD_LCD_D10__LCD_D10
784 MX28_PAD_LCD_D11__LCD_D11
785 MX28_PAD_LCD_D12__LCD_D12
786 MX28_PAD_LCD_D13__LCD_D13
787 MX28_PAD_LCD_D14__LCD_D14
788 MX28_PAD_LCD_D15__LCD_D15
789 MX28_PAD_LCD_D16__LCD_D16
790 MX28_PAD_LCD_D17__LCD_D17
791 >;
792 fsl,drive-strength = <MXS_DRIVE_4mA>;
793 fsl,voltage = <MXS_VOLTAGE_HIGH>;
794 fsl,pull-up = <MXS_PULL_DISABLE>;
795 };
796
4ced2a40
GGM		 797 lcdif_16bit_pins_a: lcdif-16bit@0 {
798 reg = <0>;
799 fsl,pinmux-ids = <
bc3875f1
LW		 800 MX28_PAD_LCD_D00__LCD_D0
801 MX28_PAD_LCD_D01__LCD_D1
802 MX28_PAD_LCD_D02__LCD_D2
803 MX28_PAD_LCD_D03__LCD_D3
804 MX28_PAD_LCD_D04__LCD_D4
805 MX28_PAD_LCD_D05__LCD_D5
806 MX28_PAD_LCD_D06__LCD_D6
807 MX28_PAD_LCD_D07__LCD_D7
808 MX28_PAD_LCD_D08__LCD_D8
809 MX28_PAD_LCD_D09__LCD_D9
810 MX28_PAD_LCD_D10__LCD_D10
811 MX28_PAD_LCD_D11__LCD_D11
812 MX28_PAD_LCD_D12__LCD_D12
813 MX28_PAD_LCD_D13__LCD_D13
814 MX28_PAD_LCD_D14__LCD_D14
815 MX28_PAD_LCD_D15__LCD_D15
4ced2a40 816 >;
4191c340
LW		 817 fsl,drive-strength = <MXS_DRIVE_4mA>;
818 fsl,voltage = <MXS_VOLTAGE_HIGH>;
819 fsl,pull-up = <MXS_PULL_DISABLE>;
4ced2a40
GGM		 820 };
821
23ad6f65
LW		 822 lcdif_sync_pins_a: lcdif-sync@0 {
823 reg = <0>;
824 fsl,pinmux-ids = <
bc3875f1
LW		 825 MX28_PAD_LCD_RS__LCD_DOTCLK
826 MX28_PAD_LCD_CS__LCD_ENABLE
827 MX28_PAD_LCD_RD_E__LCD_VSYNC
828 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
23ad6f65 829 >;
4191c340
LW		 830 fsl,drive-strength = <MXS_DRIVE_4mA>;
831 fsl,voltage = <MXS_VOLTAGE_HIGH>;
832 fsl,pull-up = <MXS_PULL_DISABLE>;
23ad6f65
LW		 833 };
834
6ca44acf
SG		 835 can0_pins_a: can0@0 {
836 reg = <0>;
837 fsl,pinmux-ids = <
bc3875f1
LW		 838 MX28_PAD_GPMI_RDY2__CAN0_TX
839 MX28_PAD_GPMI_RDY3__CAN0_RX
6ca44acf 840 >;
4191c340
LW		 841 fsl,drive-strength = <MXS_DRIVE_4mA>;
842 fsl,voltage = <MXS_VOLTAGE_HIGH>;
843 fsl,pull-up = <MXS_PULL_DISABLE>;
6ca44acf
SG		 844 };
845
846 can1_pins_a: can1@0 {
847 reg = <0>;
848 fsl,pinmux-ids = <
bc3875f1
LW		 849 MX28_PAD_GPMI_CE2N__CAN1_TX
850 MX28_PAD_GPMI_CE3N__CAN1_RX
6ca44acf 851 >;
4191c340
LW		 852 fsl,drive-strength = <MXS_DRIVE_4mA>;
853 fsl,voltage = <MXS_VOLTAGE_HIGH>;
854 fsl,pull-up = <MXS_PULL_DISABLE>;
6ca44acf 855 };
7f122213
MV		 856
857 spi2_pins_a: spi2@0 {
858 reg = <0>;
859 fsl,pinmux-ids = <
bc3875f1
LW		 860 MX28_PAD_SSP2_SCK__SSP2_SCK
861 MX28_PAD_SSP2_MOSI__SSP2_CMD
862 MX28_PAD_SSP2_MISO__SSP2_D0
863 MX28_PAD_SSP2_SS0__SSP2_D3
7f122213 864 >;
4191c340
LW		 865 fsl,drive-strength = <MXS_DRIVE_8mA>;
866 fsl,voltage = <MXS_VOLTAGE_HIGH>;
867 fsl,pull-up = <MXS_PULL_ENABLE>;
7f122213 868 };
bb2f1261 869
3314d2be
LW		 870 spi3_pins_a: spi3@0 {
871 reg = <0>;
872 fsl,pinmux-ids = <
bc3875f1
LW		 873 MX28_PAD_AUART2_RX__SSP3_D4
874 MX28_PAD_AUART2_TX__SSP3_D5
875 MX28_PAD_SSP3_SCK__SSP3_SCK
876 MX28_PAD_SSP3_MOSI__SSP3_CMD
877 MX28_PAD_SSP3_MISO__SSP3_D0
878 MX28_PAD_SSP3_SS0__SSP3_D3
3314d2be 879 >;
4191c340
LW		 880 fsl,drive-strength = <MXS_DRIVE_8mA>;
881 fsl,voltage = <MXS_VOLTAGE_HIGH>;
882 fsl,pull-up = <MXS_PULL_DISABLE>;
3314d2be
LW		 883 };
884
8f0b07a4
UKK		 885 spi3_pins_b: spi3@1 {
886 reg = <1>;
887 fsl,pinmux-ids = <
888 MX28_PAD_SSP3_SCK__SSP3_SCK
889 MX28_PAD_SSP3_MOSI__SSP3_CMD
890 MX28_PAD_SSP3_MISO__SSP3_D0
891 MX28_PAD_SSP3_SS0__SSP3_D3
892 >;
893 fsl,drive-strength = <MXS_DRIVE_8mA>;
894 fsl,voltage = <MXS_VOLTAGE_HIGH>;
895 fsl,pull-up = <MXS_PULL_ENABLE>;
896 };
897
c8e42bc9 898 usb0_pins_a: usb0@0 {
bb2f1261
MV		 899 reg = <0>;
900 fsl,pinmux-ids = <
bc3875f1 901 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
bb2f1261 902 >;
4191c340
LW		 903 fsl,drive-strength = <MXS_DRIVE_12mA>;
904 fsl,voltage = <MXS_VOLTAGE_HIGH>;
905 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261
MV		 906 };
907
c8e42bc9 908 usb0_pins_b: usb0@1 {
bb2f1261
MV		 909 reg = <1>;
910 fsl,pinmux-ids = <
bc3875f1 911 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
bb2f1261 912 >;
4191c340
LW		 913 fsl,drive-strength = <MXS_DRIVE_12mA>;
914 fsl,voltage = <MXS_VOLTAGE_HIGH>;
915 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261
MV		 916 };
917
c8e42bc9 918 usb1_pins_a: usb1@0 {
bb2f1261
MV		 919 reg = <0>;
920 fsl,pinmux-ids = <
bc3875f1 921 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
bb2f1261 922 >;
4191c340
LW		 923 fsl,drive-strength = <MXS_DRIVE_12mA>;
924 fsl,voltage = <MXS_VOLTAGE_HIGH>;
925 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261 926 };
69c02f95
FE		 927
928 usb0_id_pins_a: usb0id@0 {
929 reg = <0>;
930 fsl,pinmux-ids = <
e96e1782 931 MX28_PAD_AUART1_RTS__USB0_ID
bb2f1261 932 >;
e96e1782
LW		 933 fsl,drive-strength = <MXS_DRIVE_12mA>;
934 fsl,voltage = <MXS_VOLTAGE_HIGH>;
935 fsl,pull-up = <MXS_PULL_ENABLE>;
bb2f1261 936 };
bb89b8d2
DC		 937
938 usb0_id_pins_b: usb0id1@0 {
939 reg = <0>;
940 fsl,pinmux-ids = <
941 MX28_PAD_PWM2__USB0_ID
942 >;
943 fsl,drive-strength = <MXS_DRIVE_12mA>;
944 fsl,voltage = <MXS_VOLTAGE_HIGH>;
945 fsl,pull-up = <MXS_PULL_ENABLE>;
946 };
947
bc3a59c1
DA		 948 };
949
296f8cd3 950 digctl: digctl@8001c000 {
115581cf 951 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
0f06cde7 952 reg = <0x8001c000 0x2000>;
bc3a59c1
DA		 953 interrupts = <89>;
954 status = "disabled";
955 };
956
296f8cd3 957 etm: etm@80022000 {
0f06cde7 958 reg = <0x80022000 0x2000>;
bc3a59c1
DA		 959 status = "disabled";
960 };
961
f30fb03d 962 dma_apbx: dma-apbx@80024000 {
84f3570a 963 compatible = "fsl,imx28-dma-apbx";
0f06cde7 964 reg = <0x80024000 0x2000>;
f30fb03d
SG		 965 interrupts = <78 79 66 0
966 80 81 68 69
967 70 71 72 73
968 74 75 76 77>;
4ada77e3 969 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
f30fb03d
SG		 970 "saif0", "saif1", "i2c0", "i2c1",
971 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
972 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
973 #dma-cells = <1>;
974 dma-channels = <16>;
b598b9f3 975 clocks = <&clks 26>;
bc3a59c1
DA		 976 };
977
296f8cd3 978 dcp: dcp@80028000 {
7d56a28f 979 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
0f06cde7 980 reg = <0x80028000 0x2000>;
bc3a59c1 981 interrupts = <52 53 54>;
7d56a28f 982 status = "okay";
bc3a59c1
DA		 983 };
984
296f8cd3 985 pxp: pxp@8002a000 {
0f06cde7 986 reg = <0x8002a000 0x2000>;
bc3a59c1
DA		 987 interrupts = <39>;
988 status = "disabled";
989 };
990
296f8cd3 991 ocotp: ocotp@8002c000 {
a7be1e68
SW		 992 compatible = "fsl,imx28-ocotp", "fsl,ocotp";
993 #address-cells = <1>;
994 #size-cells = <1>;
0f06cde7 995 reg = <0x8002c000 0x2000>;
a7be1e68 996 clocks = <&clks 25>;
bc3a59c1
DA		 997 };
998
999 axi-ahb@8002e000 {
0f06cde7 1000 reg = <0x8002e000 0x2000>;
bc3a59c1
DA		 1001 status = "disabled";
1002 };
1003
296f8cd3 1004 lcdif: lcdif@80030000 {
a915ee42 1005 compatible = "fsl,imx28-lcdif";
0f06cde7 1006 reg = <0x80030000 0x2000>;
7f2b9288 1007 interrupts = <38>;
b598b9f3 1008 clocks = <&clks 55>;
f30fb03d
SG		 1009 dmas = <&dma_apbh 13>;
1010 dma-names = "rx";
bc3a59c1
DA		 1011 status = "disabled";
1012 };
1013
1014 can0: can@80032000 {
6ca44acf 1015 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 1016 reg = <0x80032000 0x2000>;
bc3a59c1 1017 interrupts = <8>;
b598b9f3
SG		 1018 clocks = <&clks 58>, <&clks 58>;
1019 clock-names = "ipg", "per";
bc3a59c1
DA		 1020 status = "disabled";
1021 };
1022
1023 can1: can@80034000 {
6ca44acf 1024 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 1025 reg = <0x80034000 0x2000>;
bc3a59c1 1026 interrupts = <9>;
b598b9f3
SG		 1027 clocks = <&clks 59>, <&clks 59>;
1028 clock-names = "ipg", "per";
bc3a59c1
DA		 1029 status = "disabled";
1030 };
1031
296f8cd3 1032 simdbg: simdbg@8003c000 {
0f06cde7 1033 reg = <0x8003c000 0x200>;
bc3a59c1
DA		 1034 status = "disabled";
1035 };
1036
296f8cd3 1037 simgpmisel: simgpmisel@8003c200 {
0f06cde7 1038 reg = <0x8003c200 0x100>;
bc3a59c1
DA		 1039 status = "disabled";
1040 };
1041
296f8cd3 1042 simsspsel: simsspsel@8003c300 {
0f06cde7 1043 reg = <0x8003c300 0x100>;
bc3a59c1
DA		 1044 status = "disabled";
1045 };
1046
296f8cd3 1047 simmemsel: simmemsel@8003c400 {
0f06cde7 1048 reg = <0x8003c400 0x100>;
bc3a59c1
DA		 1049 status = "disabled";
1050 };
1051
296f8cd3 1052 gpiomon: gpiomon@8003c500 {
0f06cde7 1053 reg = <0x8003c500 0x100>;
bc3a59c1
DA		 1054 status = "disabled";
1055 };
1056
296f8cd3 1057 simenet: simenet@8003c700 {
0f06cde7 1058 reg = <0x8003c700 0x100>;
bc3a59c1
DA		 1059 status = "disabled";
1060 };
1061
296f8cd3 1062 armjtag: armjtag@8003c800 {
0f06cde7 1063 reg = <0x8003c800 0x100>;
bc3a59c1
DA		 1064 status = "disabled";
1065 };
07a3ce7f 1066 };
bc3a59c1
DA		 1067
1068 apbx@80040000 {
1069 compatible = "simple-bus";
1070 #address-cells = <1>;
1071 #size-cells = <1>;
1072 reg = <0x80040000 0x40000>;
1073 ranges;
1074
b598b9f3 1075 clks: clkctrl@80040000 {
8f7cf881 1076 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
0f06cde7 1077 reg = <0x80040000 0x2000>;
b598b9f3 1078 #clock-cells = <1>;
bc3a59c1
DA		 1079 };
1080
1081 saif0: saif@80042000 {
27767d68 1082 #sound-dai-cells = <0>;
530f1d41 1083 compatible = "fsl,imx28-saif";
0f06cde7 1084 reg = <0x80042000 0x2000>;
7f2b9288 1085 interrupts = <59>;
66acaf3f 1086 #clock-cells = <0>;
b598b9f3 1087 clocks = <&clks 53>;
f30fb03d
SG		 1088 dmas = <&dma_apbx 4>;
1089 dma-names = "rx-tx";
bc3a59c1
DA		 1090 status = "disabled";
1091 };
1092
296f8cd3 1093 power: power@80044000 {
0f06cde7 1094 reg = <0x80044000 0x2000>;
bc3a59c1
DA		 1095 status = "disabled";
1096 };
1097
1098 saif1: saif@80046000 {
27767d68 1099 #sound-dai-cells = <0>;
530f1d41 1100 compatible = "fsl,imx28-saif";
0f06cde7 1101 reg = <0x80046000 0x2000>;
7f2b9288 1102 interrupts = <58>;
b598b9f3 1103 clocks = <&clks 54>;
f30fb03d
SG		 1104 dmas = <&dma_apbx 5>;
1105 dma-names = "rx-tx";
bc3a59c1
DA		 1106 status = "disabled";
1107 };
1108
296f8cd3 1109 lradc: lradc@80050000 {
aef35104 1110 compatible = "fsl,imx28-lradc";
0f06cde7 1111 reg = <0x80050000 0x2000>;
aef35104
MV		 1112 interrupts = <10 14 15 16 17 18 19
1113 20 21 22 23 24 25>;
bc3a59c1 1114 status = "disabled";
18da755d 1115 clocks = <&clks 41>;
40dde681 1116 #io-channel-cells = <1>;
bc3a59c1
DA		 1117 };
1118
296f8cd3 1119 spdif: spdif@80054000 {
0f06cde7 1120 reg = <0x80054000 0x2000>;
7f2b9288 1121 interrupts = <45>;
f30fb03d
SG		 1122 dmas = <&dma_apbx 2>;
1123 dma-names = "tx";
bc3a59c1
DA		 1124 status = "disabled";
1125 };
1126
296f8cd3 1127 mxs_rtc: rtc@80056000 {
f98c990c 1128 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
0f06cde7 1129 reg = <0x80056000 0x2000>;
f98c990c 1130 interrupts = <29>;
bc3a59c1
DA		 1131 };
1132
1133 i2c0: i2c@80058000 {
2a96e391
SG		 1134 #address-cells = <1>;
1135 #size-cells = <0>;
1136 compatible = "fsl,imx28-i2c";
0f06cde7 1137 reg = <0x80058000 0x2000>;
7f2b9288 1138 interrupts = <111>;
cd4f2d4a 1139 clock-frequency = <100000>;
f30fb03d
SG		 1140 dmas = <&dma_apbx 6>;
1141 dma-names = "rx-tx";
bc3a59c1
DA		 1142 status = "disabled";
1143 };
1144
1145 i2c1: i2c@8005a000 {
2a96e391
SG		 1146 #address-cells = <1>;
1147 #size-cells = <0>;
1148 compatible = "fsl,imx28-i2c";
0f06cde7 1149 reg = <0x8005a000 0x2000>;
7f2b9288 1150 interrupts = <110>;
cd4f2d4a 1151 clock-frequency = <100000>;
f30fb03d
SG		 1152 dmas = <&dma_apbx 7>;
1153 dma-names = "rx-tx";
bc3a59c1
DA		 1154 status = "disabled";
1155 };
1156
52f7176b
SG		 1157 pwm: pwm@80064000 {
1158 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
0f06cde7 1159 reg = <0x80064000 0x2000>;
b598b9f3 1160 clocks = <&clks 44>;
52f7176b
SG		 1161 #pwm-cells = <2>;
1162 fsl,pwm-number = <8>;
bc3a59c1
DA		 1163 status = "disabled";
1164 };
1165
296f8cd3 1166 timer: timrot@80068000 {
eeca6e60 1167 compatible = "fsl,imx28-timrot", "fsl,timrot";
0f06cde7 1168 reg = <0x80068000 0x2000>;
eeca6e60 1169 interrupts = <48 49 50 51>;
2efb9504 1170 clocks = <&clks 26>;
bc3a59c1
DA		 1171 };
1172
1173 auart0: serial@8006a000 {
80d969e4 1174 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1175 reg = <0x8006a000 0x2000>;
7f2b9288 1176 interrupts = <112>;
f30fb03d
SG		 1177 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1178 dma-names = "rx", "tx";
b598b9f3 1179 clocks = <&clks 45>;
bc3a59c1
DA		 1180 status = "disabled";
1181 };
1182
1183 auart1: serial@8006c000 {
80d969e4 1184 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1185 reg = <0x8006c000 0x2000>;
7f2b9288 1186 interrupts = <113>;
f30fb03d
SG		 1187 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1188 dma-names = "rx", "tx";
b598b9f3 1189 clocks = <&clks 45>;
bc3a59c1
DA		 1190 status = "disabled";
1191 };
1192
1193 auart2: serial@8006e000 {
80d969e4 1194 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1195 reg = <0x8006e000 0x2000>;
7f2b9288 1196 interrupts = <114>;
f30fb03d
SG		 1197 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1198 dma-names = "rx", "tx";
b598b9f3 1199 clocks = <&clks 45>;
bc3a59c1
DA		 1200 status = "disabled";
1201 };
1202
1203 auart3: serial@80070000 {
80d969e4 1204 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1205 reg = <0x80070000 0x2000>;
7f2b9288 1206 interrupts = <115>;
f30fb03d
SG		 1207 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1208 dma-names = "rx", "tx";
b598b9f3 1209 clocks = <&clks 45>;
bc3a59c1
DA		 1210 status = "disabled";
1211 };
1212
1213 auart4: serial@80072000 {
80d969e4 1214 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1215 reg = <0x80072000 0x2000>;
7f2b9288 1216 interrupts = <116>;
f30fb03d
SG		 1217 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1218 dma-names = "rx", "tx";
b598b9f3 1219 clocks = <&clks 45>;
bc3a59c1
DA		 1220 status = "disabled";
1221 };
1222
1223 duart: serial@80074000 {
1224 compatible = "arm,pl011", "arm,primecell";
1225 reg = <0x80074000 0x1000>;
1226 interrupts = <47>;
b598b9f3
SG		 1227 clocks = <&clks 45>, <&clks 26>;
1228 clock-names = "uart", "apb_pclk";
bc3a59c1
DA		 1229 status = "disabled";
1230 };
1231
1232 usbphy0: usbphy@8007c000 {
5da01270 1233 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 1234 reg = <0x8007c000 0x2000>;
b598b9f3 1235 clocks = <&clks 62>;
bc3a59c1
DA		 1236 status = "disabled";
1237 };
1238
1239 usbphy1: usbphy@8007e000 {
5da01270 1240 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 1241 reg = <0x8007e000 0x2000>;
b598b9f3 1242 clocks = <&clks 63>;
bc3a59c1
DA		 1243 status = "disabled";
1244 };
1245 };
1246 };
1247
1248 ahb@80080000 {
1249 compatible = "simple-bus";
1250 #address-cells = <1>;
1251 #size-cells = <1>;
1252 reg = <0x80080000 0x80000>;
1253 ranges;
1254
5da01270
RZ		 1255 usb0: usb@80080000 {
1256 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 1257 reg = <0x80080000 0x10000>;
5da01270 1258 interrupts = <93>;
b598b9f3 1259 clocks = <&clks 60>;
5da01270 1260 fsl,usbphy = <&usbphy0>;
bc3a59c1
DA		 1261 status = "disabled";
1262 };
1263
5da01270
RZ		 1264 usb1: usb@80090000 {
1265 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 1266 reg = <0x80090000 0x10000>;
5da01270 1267 interrupts = <92>;
b598b9f3 1268 clocks = <&clks 61>;
5da01270 1269 fsl,usbphy = <&usbphy1>;
3ec481ed 1270 dr_mode = "host";
bc3a59c1
DA		 1271 status = "disabled";
1272 };
1273
296f8cd3 1274 dflpt: dflpt@800c0000 {
bc3a59c1
DA		 1275 reg = <0x800c0000 0x10000>;
1276 status = "disabled";
1277 };
1278
1279 mac0: ethernet@800f0000 {
1280 compatible = "fsl,imx28-fec";
1281 reg = <0x800f0000 0x4000>;
1282 interrupts = <101>;
f231a9fe
WS		 1283 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1284 clock-names = "ipg", "ahb", "enet_out";
bc3a59c1
DA		 1285 status = "disabled";
1286 };
1287
1288 mac1: ethernet@800f4000 {
1289 compatible = "fsl,imx28-fec";
1290 reg = <0x800f4000 0x4000>;
1291 interrupts = <102>;
b598b9f3
SG		 1292 clocks = <&clks 57>, <&clks 57>;
1293 clock-names = "ipg", "ahb";
bc3a59c1
DA		 1294 status = "disabled";
1295 };
1296
296f8cd3 1297 etn_switch: switch@800f8000 {
bc3a59c1
DA		 1298 reg = <0x800f8000 0x8000>;
1299 status = "disabled";
1300 };
bc3a59c1 1301 };
f92dfb02 1302
0b452ccc 1303 iio-hwmon {
f92dfb02
AB		 1304 compatible = "iio-hwmon";
1305 io-channels = <&lradc 8>;
1306 };
bc3a59c1 1307};
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