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Merge tag 'linux-watchdog-4.17-rc1' of git://www.linux-watchdog.org/linux-watchdog
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx28.dtsi
CommitLineData
bc3a59c1
DA		 1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
25fc228e 12#include <dt-bindings/gpio/gpio.h>
bc3875f1 13#include "imx28-pinfunc.h"
bc3a59c1
DA		 14
15/ {
7f107887
FE		 16 #address-cells = <1>;
17 #size-cells = <1>;
18
bc3a59c1 19 interrupt-parent = <&icoll>;
a971c554
FE		 20 /*
21 * The decompressor and also some bootloaders rely on a
22 * pre-existing /chosen node to be available to insert the
23 * command line and merge other ATAGS info.
24 * Also for U-Boot there must be a pre-existing /memory node.
25 */
26 chosen {};
7f08e6aa 27 memory { device_type = "memory"; };
bc3a59c1 28
ce4c6f9b 29 aliases {
6bf6eb09
FE		 30 ethernet0 = &mac0;
31 ethernet1 = &mac1;
ce4c6f9b
SG		 32 gpio0 = &gpio0;
33 gpio1 = &gpio1;
34 gpio2 = &gpio2;
35 gpio3 = &gpio3;
36 gpio4 = &gpio4;
530f1d41
SG		 37 saif0 = &saif0;
38 saif1 = &saif1;
80d969e4
FE		 39 serial0 = &auart0;
40 serial1 = &auart1;
41 serial2 = &auart2;
42 serial3 = &auart3;
43 serial4 = &auart4;
6bf6eb09
FE		 44 spi0 = &ssp1;
45 spi1 = &ssp2;
1f35cc6a
PC		 46 usbphy0 = &usbphy0;
47 usbphy1 = &usbphy1;
ce4c6f9b
SG		 48 };
49
bc3a59c1 50 cpus {
d447dd88 51 #address-cells = <1>;
7925e89f
LP		 52 #size-cells = <0>;
53
d447dd88 54 cpu@0 {
7925e89f
LP		 55 compatible = "arm,arm926ej-s";
56 device_type = "cpu";
d447dd88 57 reg = <0>;
bc3a59c1
DA		 58 };
59 };
60
61 apb@80000000 {
62 compatible = "simple-bus";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 reg = <0x80000000 0x80000>;
66 ranges;
67
68 apbh@80000000 {
69 compatible = "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 reg = <0x80000000 0x3c900>;
73 ranges;
74
75 icoll: interrupt-controller@80000000 {
83a84efc 76 compatible = "fsl,imx28-icoll", "fsl,icoll";
bc3a59c1
DA		 77 interrupt-controller;
78 #interrupt-cells = <1>;
79 reg = <0x80000000 0x2000>;
80 };
81
296f8cd3 82 hsadc: hsadc@80002000 {
0f06cde7 83 reg = <0x80002000 0x2000>;
7f2b9288 84 interrupts = <13>;
f30fb03d
SG		 85 dmas = <&dma_apbh 12>;
86 dma-names = "rx";
bc3a59c1
DA		 87 status = "disabled";
88 };
89
f30fb03d 90 dma_apbh: dma-apbh@80004000 {
84f3570a 91 compatible = "fsl,imx28-dma-apbh";
0f06cde7 92 reg = <0x80004000 0x2000>;
f30fb03d
SG		 93 interrupts = <82 83 84 85
94 88 88 88 88
95 88 88 88 88
96 87 86 0 0>;
97 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
98 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
99 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
100 "hsadc", "lcdif", "empty", "empty";
101 #dma-cells = <1>;
102 dma-channels = <16>;
b598b9f3 103 clocks = <&clks 25>;
bc3a59c1
DA		 104 };
105
296f8cd3 106 perfmon: perfmon@80006000 {
0f06cde7 107 reg = <0x80006000 0x800>;
bc3a59c1
DA		 108 interrupts = <27>;
109 status = "disabled";
110 };
111
296f8cd3 112 gpmi: gpmi-nand@8000c000 {
7a8e5149
HS		 113 compatible = "fsl,imx28-gpmi-nand";
114 #address-cells = <1>;
115 #size-cells = <1>;
0f06cde7 116 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
7a8e5149 117 reg-names = "gpmi-nand", "bch";
7f2b9288
SG		 118 interrupts = <41>;
119 interrupt-names = "bch";
b598b9f3 120 clocks = <&clks 50>;
b6442559 121 clock-names = "gpmi_io";
f30fb03d
SG		 122 dmas = <&dma_apbh 4>;
123 dma-names = "rx-tx";
bc3a59c1
DA		 124 status = "disabled";
125 };
126
127 ssp0: ssp@80010000 {
41bf5706
MR		 128 #address-cells = <1>;
129 #size-cells = <0>;
0f06cde7 130 reg = <0x80010000 0x2000>;
7f2b9288 131 interrupts = <96>;
b598b9f3 132 clocks = <&clks 46>;
f30fb03d
SG		 133 dmas = <&dma_apbh 0>;
134 dma-names = "rx-tx";
bc3a59c1
DA		 135 status = "disabled";
136 };
137
138 ssp1: ssp@80012000 {
41bf5706
MR		 139 #address-cells = <1>;
140 #size-cells = <0>;
0f06cde7 141 reg = <0x80012000 0x2000>;
7f2b9288 142 interrupts = <97>;
b598b9f3 143 clocks = <&clks 47>;
f30fb03d
SG		 144 dmas = <&dma_apbh 1>;
145 dma-names = "rx-tx";
bc3a59c1
DA		 146 status = "disabled";
147 };
148
149 ssp2: ssp@80014000 {
41bf5706
MR		 150 #address-cells = <1>;
151 #size-cells = <0>;
0f06cde7 152 reg = <0x80014000 0x2000>;
7f2b9288 153 interrupts = <98>;
b598b9f3 154 clocks = <&clks 48>;
f30fb03d
SG		 155 dmas = <&dma_apbh 2>;
156 dma-names = "rx-tx";
bc3a59c1
DA		 157 status = "disabled";
158 };
159
160 ssp3: ssp@80016000 {
41bf5706
MR		 161 #address-cells = <1>;
162 #size-cells = <0>;
0f06cde7 163 reg = <0x80016000 0x2000>;
7f2b9288 164 interrupts = <99>;
b598b9f3 165 clocks = <&clks 49>;
f30fb03d
SG		 166 dmas = <&dma_apbh 3>;
167 dma-names = "rx-tx";
bc3a59c1
DA		 168 status = "disabled";
169 };
170
296f8cd3 171 pinctrl: pinctrl@80018000 {
bc3a59c1
DA		 172 #address-cells = <1>;
173 #size-cells = <0>;
ce4c6f9b 174 compatible = "fsl,imx28-pinctrl", "simple-bus";
0f06cde7 175 reg = <0x80018000 0x2000>;
bc3a59c1 176
ce4c6f9b
SG		 177 gpio0: gpio@0 {
178 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
e57609aa 179 reg = <0>;
ce4c6f9b
SG		 180 interrupts = <127>;
181 gpio-controller;
182 #gpio-cells = <2>;
183 interrupt-controller;
184 #interrupt-cells = <2>;
185 };
186
187 gpio1: gpio@1 {
188 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
e57609aa 189 reg = <1>;
ce4c6f9b
SG		 190 interrupts = <126>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 interrupt-controller;
194 #interrupt-cells = <2>;
195 };
196
197 gpio2: gpio@2 {
198 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
e57609aa 199 reg = <2>;
ce4c6f9b
SG		 200 interrupts = <125>;
201 gpio-controller;
202 #gpio-cells = <2>;
203 interrupt-controller;
204 #interrupt-cells = <2>;
205 };
206
207 gpio3: gpio@3 {
208 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
e57609aa 209 reg = <3>;
ce4c6f9b
SG		 210 interrupts = <124>;
211 gpio-controller;
212 #gpio-cells = <2>;
213 interrupt-controller;
214 #interrupt-cells = <2>;
215 };
216
217 gpio4: gpio@4 {
218 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
e57609aa 219 reg = <4>;
ce4c6f9b
SG		 220 interrupts = <123>;
221 gpio-controller;
222 #gpio-cells = <2>;
223 interrupt-controller;
224 #interrupt-cells = <2>;
225 };
226
bc3a59c1
DA		 227 duart_pins_a: duart@0 {
228 reg = <0>;
f14da767 229 fsl,pinmux-ids = <
bc3875f1
LW		 230 MX28_PAD_PWM0__DUART_RX
231 MX28_PAD_PWM1__DUART_TX
f14da767 232 >;
4191c340
LW		 233 fsl,drive-strength = <MXS_DRIVE_4mA>;
234 fsl,voltage = <MXS_VOLTAGE_HIGH>;
235 fsl,pull-up = <MXS_PULL_DISABLE>;
bc3a59c1
DA		 236 };
237
8385e7c1
MR		 238 duart_pins_b: duart@1 {
239 reg = <1>;
f14da767 240 fsl,pinmux-ids = <
bc3875f1
LW		 241 MX28_PAD_AUART0_CTS__DUART_RX
242 MX28_PAD_AUART0_RTS__DUART_TX
f14da767 243 >;
4191c340
LW		 244 fsl,drive-strength = <MXS_DRIVE_4mA>;
245 fsl,voltage = <MXS_VOLTAGE_HIGH>;
246 fsl,pull-up = <MXS_PULL_DISABLE>;
8385e7c1
MR		 247 };
248
e1a4d18f
SG		 249 duart_4pins_a: duart-4pins@0 {
250 reg = <0>;
251 fsl,pinmux-ids = <
bc3875f1
LW		 252 MX28_PAD_AUART0_CTS__DUART_RX
253 MX28_PAD_AUART0_RTS__DUART_TX
254 MX28_PAD_AUART0_RX__DUART_CTS
255 MX28_PAD_AUART0_TX__DUART_RTS
e1a4d18f 256 >;
4191c340
LW		 257 fsl,drive-strength = <MXS_DRIVE_4mA>;
258 fsl,voltage = <MXS_VOLTAGE_HIGH>;
259 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 260 };
261
7a8e5149
HS		 262 gpmi_pins_a: gpmi-nand@0 {
263 reg = <0>;
f14da767 264 fsl,pinmux-ids = <
bc3875f1
LW		 265 MX28_PAD_GPMI_D00__GPMI_D0
266 MX28_PAD_GPMI_D01__GPMI_D1
267 MX28_PAD_GPMI_D02__GPMI_D2
268 MX28_PAD_GPMI_D03__GPMI_D3
269 MX28_PAD_GPMI_D04__GPMI_D4
270 MX28_PAD_GPMI_D05__GPMI_D5
271 MX28_PAD_GPMI_D06__GPMI_D6
272 MX28_PAD_GPMI_D07__GPMI_D7
273 MX28_PAD_GPMI_CE0N__GPMI_CE0N
274 MX28_PAD_GPMI_RDY0__GPMI_READY0
275 MX28_PAD_GPMI_RDN__GPMI_RDN
276 MX28_PAD_GPMI_WRN__GPMI_WRN
277 MX28_PAD_GPMI_ALE__GPMI_ALE
278 MX28_PAD_GPMI_CLE__GPMI_CLE
279 MX28_PAD_GPMI_RESETN__GPMI_RESETN
f14da767 280 >;
4191c340
LW		 281 fsl,drive-strength = <MXS_DRIVE_4mA>;
282 fsl,voltage = <MXS_VOLTAGE_HIGH>;
283 fsl,pull-up = <MXS_PULL_DISABLE>;
7a8e5149
HS		 284 };
285
497b90db
FE		 286 gpmi_status_cfg: gpmi-status-cfg@0 {
287 reg = <0>;
f14da767 288 fsl,pinmux-ids = <
bc3875f1
LW		 289 MX28_PAD_GPMI_RDN__GPMI_RDN
290 MX28_PAD_GPMI_WRN__GPMI_WRN
291 MX28_PAD_GPMI_RESETN__GPMI_RESETN
f14da767 292 >;
4191c340 293 fsl,drive-strength = <MXS_DRIVE_12mA>;
7a8e5149
HS		 294 };
295
80d969e4
FE		 296 auart0_pins_a: auart0@0 {
297 reg = <0>;
f14da767 298 fsl,pinmux-ids = <
bc3875f1
LW		 299 MX28_PAD_AUART0_RX__AUART0_RX
300 MX28_PAD_AUART0_TX__AUART0_TX
301 MX28_PAD_AUART0_CTS__AUART0_CTS
302 MX28_PAD_AUART0_RTS__AUART0_RTS
f14da767 303 >;
4191c340
LW		 304 fsl,drive-strength = <MXS_DRIVE_4mA>;
305 fsl,voltage = <MXS_VOLTAGE_HIGH>;
306 fsl,pull-up = <MXS_PULL_DISABLE>;
8fa62e11
MV		 307 };
308
309 auart0_2pins_a: auart0-2pins@0 {
310 reg = <0>;
311 fsl,pinmux-ids = <
bc3875f1
LW		 312 MX28_PAD_AUART0_RX__AUART0_RX
313 MX28_PAD_AUART0_TX__AUART0_TX
8fa62e11 314 >;
4191c340
LW		 315 fsl,drive-strength = <MXS_DRIVE_4mA>;
316 fsl,voltage = <MXS_VOLTAGE_HIGH>;
317 fsl,pull-up = <MXS_PULL_DISABLE>;
80d969e4
FE		 318 };
319
e1a4d18f
SG		 320 auart1_pins_a: auart1@0 {
321 reg = <0>;
322 fsl,pinmux-ids = <
bc3875f1
LW		 323 MX28_PAD_AUART1_RX__AUART1_RX
324 MX28_PAD_AUART1_TX__AUART1_TX
325 MX28_PAD_AUART1_CTS__AUART1_CTS
326 MX28_PAD_AUART1_RTS__AUART1_RTS
e1a4d18f 327 >;
4191c340
LW		 328 fsl,drive-strength = <MXS_DRIVE_4mA>;
329 fsl,voltage = <MXS_VOLTAGE_HIGH>;
330 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 331 };
332
3143bbb4
SG		 333 auart1_2pins_a: auart1-2pins@0 {
334 reg = <0>;
335 fsl,pinmux-ids = <
bc3875f1
LW		 336 MX28_PAD_AUART1_RX__AUART1_RX
337 MX28_PAD_AUART1_TX__AUART1_TX
3143bbb4 338 >;
4191c340
LW		 339 fsl,drive-strength = <MXS_DRIVE_4mA>;
340 fsl,voltage = <MXS_VOLTAGE_HIGH>;
341 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 342 };
343
344 auart2_2pins_a: auart2-2pins@0 {
345 reg = <0>;
346 fsl,pinmux-ids = <
bc3875f1
LW		 347 MX28_PAD_SSP2_SCK__AUART2_RX
348 MX28_PAD_SSP2_MOSI__AUART2_TX
3143bbb4 349 >;
4191c340
LW		 350 fsl,drive-strength = <MXS_DRIVE_4mA>;
351 fsl,voltage = <MXS_VOLTAGE_HIGH>;
352 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 353 };
354
f8040cf5
EB		 355 auart2_2pins_b: auart2-2pins@1 {
356 reg = <1>;
357 fsl,pinmux-ids = <
bc3875f1
LW		 358 MX28_PAD_AUART2_RX__AUART2_RX
359 MX28_PAD_AUART2_TX__AUART2_TX
f8040cf5 360 >;
4191c340
LW		 361 fsl,drive-strength = <MXS_DRIVE_4mA>;
362 fsl,voltage = <MXS_VOLTAGE_HIGH>;
363 fsl,pull-up = <MXS_PULL_DISABLE>;
f8040cf5
EB		 364 };
365
cd0214c3
AM		 366 auart2_pins_a: auart2-pins@0 {
367 reg = <0>;
368 fsl,pinmux-ids = <
369 MX28_PAD_AUART2_RX__AUART2_RX
370 MX28_PAD_AUART2_TX__AUART2_TX
371 MX28_PAD_AUART2_CTS__AUART2_CTS
372 MX28_PAD_AUART2_RTS__AUART2_RTS
373 >;
374 fsl,drive-strength = <MXS_DRIVE_4mA>;
375 fsl,voltage = <MXS_VOLTAGE_HIGH>;
376 fsl,pull-up = <MXS_PULL_DISABLE>;
377 };
378
80d969e4
FE		 379 auart3_pins_a: auart3@0 {
380 reg = <0>;
f14da767 381 fsl,pinmux-ids = <
bc3875f1
LW		 382 MX28_PAD_AUART3_RX__AUART3_RX
383 MX28_PAD_AUART3_TX__AUART3_TX
384 MX28_PAD_AUART3_CTS__AUART3_CTS
385 MX28_PAD_AUART3_RTS__AUART3_RTS
f14da767 386 >;
4191c340
LW		 387 fsl,drive-strength = <MXS_DRIVE_4mA>;
388 fsl,voltage = <MXS_VOLTAGE_HIGH>;
389 fsl,pull-up = <MXS_PULL_DISABLE>;
80d969e4
FE		 390 };
391
3143bbb4
SG		 392 auart3_2pins_a: auart3-2pins@0 {
393 reg = <0>;
394 fsl,pinmux-ids = <
bc3875f1
LW		 395 MX28_PAD_SSP2_MISO__AUART3_RX
396 MX28_PAD_SSP2_SS0__AUART3_TX
3143bbb4 397 >;
4191c340
LW		 398 fsl,drive-strength = <MXS_DRIVE_4mA>;
399 fsl,voltage = <MXS_VOLTAGE_HIGH>;
400 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 401 };
402
4812e746
EB		 403 auart3_2pins_b: auart3-2pins@1 {
404 reg = <1>;
405 fsl,pinmux-ids = <
bc3875f1
LW		 406 MX28_PAD_AUART3_RX__AUART3_RX
407 MX28_PAD_AUART3_TX__AUART3_TX
4812e746 408 >;
4191c340
LW		 409 fsl,drive-strength = <MXS_DRIVE_4mA>;
410 fsl,voltage = <MXS_VOLTAGE_HIGH>;
411 fsl,pull-up = <MXS_PULL_DISABLE>;
4812e746
EB		 412 };
413
33678d12
EB		 414 auart4_2pins_a: auart4@0 {
415 reg = <0>;
416 fsl,pinmux-ids = <
bc3875f1
LW		 417 MX28_PAD_SSP3_SCK__AUART4_TX
418 MX28_PAD_SSP3_MOSI__AUART4_RX
33678d12 419 >;
4191c340
LW		 420 fsl,drive-strength = <MXS_DRIVE_4mA>;
421 fsl,voltage = <MXS_VOLTAGE_HIGH>;
422 fsl,pull-up = <MXS_PULL_DISABLE>;
33678d12
EB		 423 };
424
cfa1dd99
MR		 425 auart4_2pins_b: auart4@1 {
426 reg = <1>;
427 fsl,pinmux-ids = <
428 MX28_PAD_AUART0_CTS__AUART4_RX
429 MX28_PAD_AUART0_RTS__AUART4_TX
430 >;
431 fsl,drive-strength = <MXS_DRIVE_4mA>;
432 fsl,voltage = <MXS_VOLTAGE_HIGH>;
433 fsl,pull-up = <MXS_PULL_DISABLE>;
434 };
435
bc3a59c1
DA		 436 mac0_pins_a: mac0@0 {
437 reg = <0>;
f14da767 438 fsl,pinmux-ids = <
bc3875f1
LW		 439 MX28_PAD_ENET0_MDC__ENET0_MDC
440 MX28_PAD_ENET0_MDIO__ENET0_MDIO
441 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
442 MX28_PAD_ENET0_RXD0__ENET0_RXD0
443 MX28_PAD_ENET0_RXD1__ENET0_RXD1
444 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
445 MX28_PAD_ENET0_TXD0__ENET0_TXD0
446 MX28_PAD_ENET0_TXD1__ENET0_TXD1
447 MX28_PAD_ENET_CLK__CLKCTRL_ENET
f14da767 448 >;
4191c340
LW		 449 fsl,drive-strength = <MXS_DRIVE_8mA>;
450 fsl,voltage = <MXS_VOLTAGE_HIGH>;
451 fsl,pull-up = <MXS_PULL_ENABLE>;
bc3a59c1
DA		 452 };
453
9eb7db1c
UKK		 454 mac0_pins_b: mac0@1 {
455 reg = <1>;
456 fsl,pinmux-ids = <
457 MX28_PAD_ENET0_MDC__ENET0_MDC
458 MX28_PAD_ENET0_MDIO__ENET0_MDIO
459 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
460 MX28_PAD_ENET0_RXD0__ENET0_RXD0
461 MX28_PAD_ENET0_RXD1__ENET0_RXD1
462 MX28_PAD_ENET0_RXD2__ENET0_RXD2
463 MX28_PAD_ENET0_RXD3__ENET0_RXD3
464 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
465 MX28_PAD_ENET0_TXD0__ENET0_TXD0
466 MX28_PAD_ENET0_TXD1__ENET0_TXD1
467 MX28_PAD_ENET0_TXD2__ENET0_TXD2
468 MX28_PAD_ENET0_TXD3__ENET0_TXD3
469 MX28_PAD_ENET_CLK__CLKCTRL_ENET
470 MX28_PAD_ENET0_COL__ENET0_COL
471 MX28_PAD_ENET0_CRS__ENET0_CRS
472 MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
473 MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
474 >;
475 fsl,drive-strength = <MXS_DRIVE_8mA>;
476 fsl,voltage = <MXS_VOLTAGE_HIGH>;
477 fsl,pull-up = <MXS_PULL_ENABLE>;
478 };
479
bc3a59c1
DA		 480 mac1_pins_a: mac1@0 {
481 reg = <0>;
f14da767 482 fsl,pinmux-ids = <
bc3875f1
LW		 483 MX28_PAD_ENET0_CRS__ENET1_RX_EN
484 MX28_PAD_ENET0_RXD2__ENET1_RXD0
485 MX28_PAD_ENET0_RXD3__ENET1_RXD1
486 MX28_PAD_ENET0_COL__ENET1_TX_EN
487 MX28_PAD_ENET0_TXD2__ENET1_TXD0
488 MX28_PAD_ENET0_TXD3__ENET1_TXD1
f14da767 489 >;
4191c340
LW		 490 fsl,drive-strength = <MXS_DRIVE_8mA>;
491 fsl,voltage = <MXS_VOLTAGE_HIGH>;
492 fsl,pull-up = <MXS_PULL_ENABLE>;
bc3a59c1 493 };
35d23047
SG		 494
495 mmc0_8bit_pins_a: mmc0-8bit@0 {
496 reg = <0>;
f14da767 497 fsl,pinmux-ids = <
bc3875f1
LW		 498 MX28_PAD_SSP0_DATA0__SSP0_D0
499 MX28_PAD_SSP0_DATA1__SSP0_D1
500 MX28_PAD_SSP0_DATA2__SSP0_D2
501 MX28_PAD_SSP0_DATA3__SSP0_D3
502 MX28_PAD_SSP0_DATA4__SSP0_D4
503 MX28_PAD_SSP0_DATA5__SSP0_D5
504 MX28_PAD_SSP0_DATA6__SSP0_D6
505 MX28_PAD_SSP0_DATA7__SSP0_D7
506 MX28_PAD_SSP0_CMD__SSP0_CMD
507 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
508 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 509 >;
4191c340
LW		 510 fsl,drive-strength = <MXS_DRIVE_8mA>;
511 fsl,voltage = <MXS_VOLTAGE_HIGH>;
512 fsl,pull-up = <MXS_PULL_ENABLE>;
35d23047
SG		 513 };
514
8385e7c1
MR		 515 mmc0_4bit_pins_a: mmc0-4bit@0 {
516 reg = <0>;
f14da767 517 fsl,pinmux-ids = <
bc3875f1
LW		 518 MX28_PAD_SSP0_DATA0__SSP0_D0
519 MX28_PAD_SSP0_DATA1__SSP0_D1
520 MX28_PAD_SSP0_DATA2__SSP0_D2
521 MX28_PAD_SSP0_DATA3__SSP0_D3
522 MX28_PAD_SSP0_CMD__SSP0_CMD
523 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
524 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 525 >;
4191c340
LW		 526 fsl,drive-strength = <MXS_DRIVE_8mA>;
527 fsl,voltage = <MXS_VOLTAGE_HIGH>;
528 fsl,pull-up = <MXS_PULL_ENABLE>;
8385e7c1
MR		 529 };
530
497b90db
FE		 531 mmc0_cd_cfg: mmc0-cd-cfg@0 {
532 reg = <0>;
f14da767 533 fsl,pinmux-ids = <
bc3875f1 534 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
f14da767 535 >;
4191c340 536 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047
SG		 537 };
538
497b90db
FE		 539 mmc0_sck_cfg: mmc0-sck-cfg@0 {
540 reg = <0>;
f14da767 541 fsl,pinmux-ids = <
bc3875f1 542 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 543 >;
4191c340
LW		 544 fsl,drive-strength = <MXS_DRIVE_12mA>;
545 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047 546 };
2a96e391 547
77d6386b
MKB		 548 mmc1_4bit_pins_a: mmc1-4bit@0 {
549 reg = <0>;
550 fsl,pinmux-ids = <
551 MX28_PAD_GPMI_D00__SSP1_D0
552 MX28_PAD_GPMI_D01__SSP1_D1
553 MX28_PAD_GPMI_D02__SSP1_D2
554 MX28_PAD_GPMI_D03__SSP1_D3
555 MX28_PAD_GPMI_RDY1__SSP1_CMD
556 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
557 MX28_PAD_GPMI_WRN__SSP1_SCK
558 >;
559 fsl,drive-strength = <MXS_DRIVE_8mA>;
560 fsl,voltage = <MXS_VOLTAGE_HIGH>;
561 fsl,pull-up = <MXS_PULL_ENABLE>;
562 };
563
497b90db
FE		 564 mmc1_cd_cfg: mmc1-cd-cfg@0 {
565 reg = <0>;
77d6386b
MKB		 566 fsl,pinmux-ids = <
567 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
568 >;
569 fsl,pull-up = <MXS_PULL_DISABLE>;
570 };
571
497b90db
FE		 572 mmc1_sck_cfg: mmc1-sck-cfg@0 {
573 reg = <0>;
77d6386b
MKB		 574 fsl,pinmux-ids = <
575 MX28_PAD_GPMI_WRN__SSP1_SCK
576 >;
577 fsl,drive-strength = <MXS_DRIVE_12mA>;
578 fsl,pull-up = <MXS_PULL_DISABLE>;
579 };
580
581
5550e8e9
MV		 582 mmc2_4bit_pins_a: mmc2-4bit@0 {
583 reg = <0>;
584 fsl,pinmux-ids = <
585 MX28_PAD_SSP0_DATA4__SSP2_D0
586 MX28_PAD_SSP1_SCK__SSP2_D1
587 MX28_PAD_SSP1_CMD__SSP2_D2
588 MX28_PAD_SSP0_DATA5__SSP2_D3
589 MX28_PAD_SSP0_DATA6__SSP2_CMD
590 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
591 MX28_PAD_SSP0_DATA7__SSP2_SCK
592 >;
593 fsl,drive-strength = <MXS_DRIVE_8mA>;
594 fsl,voltage = <MXS_VOLTAGE_HIGH>;
595 fsl,pull-up = <MXS_PULL_ENABLE>;
596 };
597
df93726b
MH		 598 mmc2_4bit_pins_b: mmc2-4bit@1 {
599 reg = <1>;
600 fsl,pinmux-ids = <
601 MX28_PAD_SSP2_SCK__SSP2_SCK
602 MX28_PAD_SSP2_MOSI__SSP2_CMD
603 MX28_PAD_SSP2_MISO__SSP2_D0
604 MX28_PAD_SSP2_SS0__SSP2_D3
605 MX28_PAD_SSP2_SS1__SSP2_D1
606 MX28_PAD_SSP2_SS2__SSP2_D2
607 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
608 >;
609 fsl,drive-strength = <MXS_DRIVE_8mA>;
610 fsl,voltage = <MXS_VOLTAGE_HIGH>;
611 fsl,pull-up = <MXS_PULL_ENABLE>;
612 };
613
497b90db
FE		 614 mmc2_cd_cfg: mmc2-cd-cfg@0 {
615 reg = <0>;
5550e8e9
MV		 616 fsl,pinmux-ids = <
617 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
618 >;
619 fsl,pull-up = <MXS_PULL_DISABLE>;
620 };
621
45e89549
MH		 622 mmc2_sck_cfg_a: mmc2-sck-cfg@0 {
623 reg = <0>;
5550e8e9
MV		 624 fsl,pinmux-ids = <
625 MX28_PAD_SSP0_DATA7__SSP2_SCK
626 >;
627 fsl,drive-strength = <MXS_DRIVE_12mA>;
628 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047 629 };
2a96e391 630
620885e8
MH		 631 mmc2_sck_cfg_b: mmc2-sck-cfg@1 {
632 reg = <1>;
633 fsl,pinmux-ids = <
634 MX28_PAD_SSP2_SCK__SSP2_SCK
635 >;
636 fsl,drive-strength = <MXS_DRIVE_12mA>;
637 fsl,pull-up = <MXS_PULL_DISABLE>;
638 };
639
2a96e391
SG		 640 i2c0_pins_a: i2c0@0 {
641 reg = <0>;
f14da767 642 fsl,pinmux-ids = <
bc3875f1
LW		 643 MX28_PAD_I2C0_SCL__I2C0_SCL
644 MX28_PAD_I2C0_SDA__I2C0_SDA
f14da767 645 >;
4191c340
LW		 646 fsl,drive-strength = <MXS_DRIVE_8mA>;
647 fsl,voltage = <MXS_VOLTAGE_HIGH>;
648 fsl,pull-up = <MXS_PULL_ENABLE>;
2a96e391 649 };
530f1d41 650
5c697ea2
MR		 651 i2c0_pins_b: i2c0@1 {
652 reg = <1>;
653 fsl,pinmux-ids = <
bc3875f1
LW		 654 MX28_PAD_AUART0_RX__I2C0_SCL
655 MX28_PAD_AUART0_TX__I2C0_SDA
5c697ea2 656 >;
4191c340
LW		 657 fsl,drive-strength = <MXS_DRIVE_8mA>;
658 fsl,voltage = <MXS_VOLTAGE_HIGH>;
659 fsl,pull-up = <MXS_PULL_ENABLE>;
5c697ea2
MR		 660 };
661
de7e934f
MR		 662 i2c1_pins_a: i2c1@0 {
663 reg = <0>;
664 fsl,pinmux-ids = <
bc3875f1
LW		 665 MX28_PAD_PWM0__I2C1_SCL
666 MX28_PAD_PWM1__I2C1_SDA
de7e934f 667 >;
4191c340
LW		 668 fsl,drive-strength = <MXS_DRIVE_8mA>;
669 fsl,voltage = <MXS_VOLTAGE_HIGH>;
670 fsl,pull-up = <MXS_PULL_ENABLE>;
de7e934f
MR		 671 };
672
17c63dd0
UKK		 673 i2c1_pins_b: i2c1@1 {
674 reg = <1>;
675 fsl,pinmux-ids = <
676 MX28_PAD_AUART2_CTS__I2C1_SCL
677 MX28_PAD_AUART2_RTS__I2C1_SDA
678 >;
679 fsl,drive-strength = <MXS_DRIVE_8mA>;
680 fsl,voltage = <MXS_VOLTAGE_HIGH>;
681 fsl,pull-up = <MXS_PULL_ENABLE>;
682 };
683
530f1d41
SG		 684 saif0_pins_a: saif0@0 {
685 reg = <0>;
f14da767 686 fsl,pinmux-ids = <
bc3875f1
LW		 687 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
688 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
689 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
690 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
f14da767 691 >;
4191c340
LW		 692 fsl,drive-strength = <MXS_DRIVE_12mA>;
693 fsl,voltage = <MXS_VOLTAGE_HIGH>;
694 fsl,pull-up = <MXS_PULL_ENABLE>;
530f1d41
SG		 695 };
696
2e1dd9fc
LW		 697 saif0_pins_b: saif0@1 {
698 reg = <1>;
699 fsl,pinmux-ids = <
bc3875f1
LW		 700 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
701 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
702 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
2e1dd9fc 703 >;
4191c340
LW		 704 fsl,drive-strength = <MXS_DRIVE_12mA>;
705 fsl,voltage = <MXS_VOLTAGE_HIGH>;
706 fsl,pull-up = <MXS_PULL_ENABLE>;
2e1dd9fc
LW		 707 };
708
530f1d41
SG		 709 saif1_pins_a: saif1@0 {
710 reg = <0>;
f14da767 711 fsl,pinmux-ids = <
bc3875f1 712 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
f14da767 713 >;
4191c340
LW		 714 fsl,drive-strength = <MXS_DRIVE_12mA>;
715 fsl,voltage = <MXS_VOLTAGE_HIGH>;
716 fsl,pull-up = <MXS_PULL_ENABLE>;
530f1d41 717 };
52f7176b 718
e1a4d18f
SG		 719 pwm0_pins_a: pwm0@0 {
720 reg = <0>;
721 fsl,pinmux-ids = <
bc3875f1 722 MX28_PAD_PWM0__PWM_0
e1a4d18f 723 >;
4191c340
LW		 724 fsl,drive-strength = <MXS_DRIVE_4mA>;
725 fsl,voltage = <MXS_VOLTAGE_HIGH>;
726 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 727 };
728
52f7176b
SG		 729 pwm2_pins_a: pwm2@0 {
730 reg = <0>;
731 fsl,pinmux-ids = <
bc3875f1 732 MX28_PAD_PWM2__PWM_2
52f7176b 733 >;
4191c340
LW		 734 fsl,drive-strength = <MXS_DRIVE_4mA>;
735 fsl,voltage = <MXS_VOLTAGE_HIGH>;
736 fsl,pull-up = <MXS_PULL_DISABLE>;
52f7176b 737 };
a915ee42 738
2bde51cb
JB		 739 pwm3_pins_a: pwm3@0 {
740 reg = <0>;
741 fsl,pinmux-ids = <
bc3875f1 742 MX28_PAD_PWM3__PWM_3
2bde51cb 743 >;
4191c340
LW		 744 fsl,drive-strength = <MXS_DRIVE_4mA>;
745 fsl,voltage = <MXS_VOLTAGE_HIGH>;
746 fsl,pull-up = <MXS_PULL_DISABLE>;
2bde51cb
JB		 747 };
748
d248620c
MR		 749 pwm3_pins_b: pwm3@1 {
750 reg = <1>;
751 fsl,pinmux-ids = <
bc3875f1 752 MX28_PAD_SAIF0_MCLK__PWM_3
d248620c 753 >;
4191c340
LW		 754 fsl,drive-strength = <MXS_DRIVE_4mA>;
755 fsl,voltage = <MXS_VOLTAGE_HIGH>;
756 fsl,pull-up = <MXS_PULL_DISABLE>;
d248620c
MR		 757 };
758
2f44211f
MR		 759 pwm4_pins_a: pwm4@0 {
760 reg = <0>;
761 fsl,pinmux-ids = <
bc3875f1 762 MX28_PAD_PWM4__PWM_4
2f44211f 763 >;
4191c340
LW		 764 fsl,drive-strength = <MXS_DRIVE_4mA>;
765 fsl,voltage = <MXS_VOLTAGE_HIGH>;
766 fsl,pull-up = <MXS_PULL_DISABLE>;
2f44211f
MR		 767 };
768
a915ee42
SG		 769 lcdif_24bit_pins_a: lcdif-24bit@0 {
770 reg = <0>;
771 fsl,pinmux-ids = <
bc3875f1
LW		 772 MX28_PAD_LCD_D00__LCD_D0
773 MX28_PAD_LCD_D01__LCD_D1
774 MX28_PAD_LCD_D02__LCD_D2
775 MX28_PAD_LCD_D03__LCD_D3
776 MX28_PAD_LCD_D04__LCD_D4
777 MX28_PAD_LCD_D05__LCD_D5
778 MX28_PAD_LCD_D06__LCD_D6
779 MX28_PAD_LCD_D07__LCD_D7
780 MX28_PAD_LCD_D08__LCD_D8
781 MX28_PAD_LCD_D09__LCD_D9
782 MX28_PAD_LCD_D10__LCD_D10
783 MX28_PAD_LCD_D11__LCD_D11
784 MX28_PAD_LCD_D12__LCD_D12
785 MX28_PAD_LCD_D13__LCD_D13
786 MX28_PAD_LCD_D14__LCD_D14
787 MX28_PAD_LCD_D15__LCD_D15
788 MX28_PAD_LCD_D16__LCD_D16
789 MX28_PAD_LCD_D17__LCD_D17
790 MX28_PAD_LCD_D18__LCD_D18
791 MX28_PAD_LCD_D19__LCD_D19
792 MX28_PAD_LCD_D20__LCD_D20
793 MX28_PAD_LCD_D21__LCD_D21
794 MX28_PAD_LCD_D22__LCD_D22
795 MX28_PAD_LCD_D23__LCD_D23
a915ee42 796 >;
4191c340
LW		 797 fsl,drive-strength = <MXS_DRIVE_4mA>;
798 fsl,voltage = <MXS_VOLTAGE_HIGH>;
799 fsl,pull-up = <MXS_PULL_DISABLE>;
a915ee42 800 };
6ca44acf 801
ec985eb2
DC		 802 lcdif_18bit_pins_a: lcdif-18bit@0 {
803 reg = <0>;
804 fsl,pinmux-ids = <
805 MX28_PAD_LCD_D00__LCD_D0
806 MX28_PAD_LCD_D01__LCD_D1
807 MX28_PAD_LCD_D02__LCD_D2
808 MX28_PAD_LCD_D03__LCD_D3
809 MX28_PAD_LCD_D04__LCD_D4
810 MX28_PAD_LCD_D05__LCD_D5
811 MX28_PAD_LCD_D06__LCD_D6
812 MX28_PAD_LCD_D07__LCD_D7
813 MX28_PAD_LCD_D08__LCD_D8
814 MX28_PAD_LCD_D09__LCD_D9
815 MX28_PAD_LCD_D10__LCD_D10
816 MX28_PAD_LCD_D11__LCD_D11
817 MX28_PAD_LCD_D12__LCD_D12
818 MX28_PAD_LCD_D13__LCD_D13
819 MX28_PAD_LCD_D14__LCD_D14
820 MX28_PAD_LCD_D15__LCD_D15
821 MX28_PAD_LCD_D16__LCD_D16
822 MX28_PAD_LCD_D17__LCD_D17
823 >;
824 fsl,drive-strength = <MXS_DRIVE_4mA>;
825 fsl,voltage = <MXS_VOLTAGE_HIGH>;
826 fsl,pull-up = <MXS_PULL_DISABLE>;
827 };
828
4ced2a40
GGM		 829 lcdif_16bit_pins_a: lcdif-16bit@0 {
830 reg = <0>;
831 fsl,pinmux-ids = <
bc3875f1
LW		 832 MX28_PAD_LCD_D00__LCD_D0
833 MX28_PAD_LCD_D01__LCD_D1
834 MX28_PAD_LCD_D02__LCD_D2
835 MX28_PAD_LCD_D03__LCD_D3
836 MX28_PAD_LCD_D04__LCD_D4
837 MX28_PAD_LCD_D05__LCD_D5
838 MX28_PAD_LCD_D06__LCD_D6
839 MX28_PAD_LCD_D07__LCD_D7
840 MX28_PAD_LCD_D08__LCD_D8
841 MX28_PAD_LCD_D09__LCD_D9
842 MX28_PAD_LCD_D10__LCD_D10
843 MX28_PAD_LCD_D11__LCD_D11
844 MX28_PAD_LCD_D12__LCD_D12
845 MX28_PAD_LCD_D13__LCD_D13
846 MX28_PAD_LCD_D14__LCD_D14
847 MX28_PAD_LCD_D15__LCD_D15
4ced2a40 848 >;
4191c340
LW		 849 fsl,drive-strength = <MXS_DRIVE_4mA>;
850 fsl,voltage = <MXS_VOLTAGE_HIGH>;
851 fsl,pull-up = <MXS_PULL_DISABLE>;
4ced2a40
GGM		 852 };
853
23ad6f65
LW		 854 lcdif_sync_pins_a: lcdif-sync@0 {
855 reg = <0>;
856 fsl,pinmux-ids = <
bc3875f1
LW		 857 MX28_PAD_LCD_RS__LCD_DOTCLK
858 MX28_PAD_LCD_CS__LCD_ENABLE
859 MX28_PAD_LCD_RD_E__LCD_VSYNC
860 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
23ad6f65 861 >;
4191c340
LW		 862 fsl,drive-strength = <MXS_DRIVE_4mA>;
863 fsl,voltage = <MXS_VOLTAGE_HIGH>;
864 fsl,pull-up = <MXS_PULL_DISABLE>;
23ad6f65
LW		 865 };
866
6ca44acf
SG		 867 can0_pins_a: can0@0 {
868 reg = <0>;
869 fsl,pinmux-ids = <
bc3875f1
LW		 870 MX28_PAD_GPMI_RDY2__CAN0_TX
871 MX28_PAD_GPMI_RDY3__CAN0_RX
6ca44acf 872 >;
4191c340
LW		 873 fsl,drive-strength = <MXS_DRIVE_4mA>;
874 fsl,voltage = <MXS_VOLTAGE_HIGH>;
875 fsl,pull-up = <MXS_PULL_DISABLE>;
6ca44acf
SG		 876 };
877
878 can1_pins_a: can1@0 {
879 reg = <0>;
880 fsl,pinmux-ids = <
bc3875f1
LW		 881 MX28_PAD_GPMI_CE2N__CAN1_TX
882 MX28_PAD_GPMI_CE3N__CAN1_RX
6ca44acf 883 >;
4191c340
LW		 884 fsl,drive-strength = <MXS_DRIVE_4mA>;
885 fsl,voltage = <MXS_VOLTAGE_HIGH>;
886 fsl,pull-up = <MXS_PULL_DISABLE>;
6ca44acf 887 };
7f122213
MV		 888
889 spi2_pins_a: spi2@0 {
890 reg = <0>;
891 fsl,pinmux-ids = <
bc3875f1
LW		 892 MX28_PAD_SSP2_SCK__SSP2_SCK
893 MX28_PAD_SSP2_MOSI__SSP2_CMD
894 MX28_PAD_SSP2_MISO__SSP2_D0
895 MX28_PAD_SSP2_SS0__SSP2_D3
7f122213 896 >;
4191c340
LW		 897 fsl,drive-strength = <MXS_DRIVE_8mA>;
898 fsl,voltage = <MXS_VOLTAGE_HIGH>;
899 fsl,pull-up = <MXS_PULL_ENABLE>;
7f122213 900 };
bb2f1261 901
3314d2be
LW		 902 spi3_pins_a: spi3@0 {
903 reg = <0>;
904 fsl,pinmux-ids = <
bc3875f1
LW		 905 MX28_PAD_AUART2_RX__SSP3_D4
906 MX28_PAD_AUART2_TX__SSP3_D5
907 MX28_PAD_SSP3_SCK__SSP3_SCK
908 MX28_PAD_SSP3_MOSI__SSP3_CMD
909 MX28_PAD_SSP3_MISO__SSP3_D0
910 MX28_PAD_SSP3_SS0__SSP3_D3
3314d2be 911 >;
4191c340
LW		 912 fsl,drive-strength = <MXS_DRIVE_8mA>;
913 fsl,voltage = <MXS_VOLTAGE_HIGH>;
914 fsl,pull-up = <MXS_PULL_DISABLE>;
3314d2be
LW		 915 };
916
8f0b07a4
UKK		 917 spi3_pins_b: spi3@1 {
918 reg = <1>;
919 fsl,pinmux-ids = <
920 MX28_PAD_SSP3_SCK__SSP3_SCK
921 MX28_PAD_SSP3_MOSI__SSP3_CMD
922 MX28_PAD_SSP3_MISO__SSP3_D0
923 MX28_PAD_SSP3_SS0__SSP3_D3
924 >;
925 fsl,drive-strength = <MXS_DRIVE_8mA>;
926 fsl,voltage = <MXS_VOLTAGE_HIGH>;
927 fsl,pull-up = <MXS_PULL_ENABLE>;
928 };
929
c8e42bc9 930 usb0_pins_a: usb0@0 {
bb2f1261
MV		 931 reg = <0>;
932 fsl,pinmux-ids = <
bc3875f1 933 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
bb2f1261 934 >;
4191c340
LW		 935 fsl,drive-strength = <MXS_DRIVE_12mA>;
936 fsl,voltage = <MXS_VOLTAGE_HIGH>;
937 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261
MV		 938 };
939
c8e42bc9 940 usb0_pins_b: usb0@1 {
bb2f1261
MV		 941 reg = <1>;
942 fsl,pinmux-ids = <
bc3875f1 943 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
bb2f1261 944 >;
4191c340
LW		 945 fsl,drive-strength = <MXS_DRIVE_12mA>;
946 fsl,voltage = <MXS_VOLTAGE_HIGH>;
947 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261
MV		 948 };
949
c8e42bc9 950 usb1_pins_a: usb1@0 {
bb2f1261
MV		 951 reg = <0>;
952 fsl,pinmux-ids = <
bc3875f1 953 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
bb2f1261 954 >;
4191c340
LW		 955 fsl,drive-strength = <MXS_DRIVE_12mA>;
956 fsl,voltage = <MXS_VOLTAGE_HIGH>;
957 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261 958 };
69c02f95
FE		 959
960 usb0_id_pins_a: usb0id@0 {
961 reg = <0>;
962 fsl,pinmux-ids = <
e96e1782 963 MX28_PAD_AUART1_RTS__USB0_ID
bb2f1261 964 >;
e96e1782
LW		 965 fsl,drive-strength = <MXS_DRIVE_12mA>;
966 fsl,voltage = <MXS_VOLTAGE_HIGH>;
967 fsl,pull-up = <MXS_PULL_ENABLE>;
bb2f1261 968 };
bb89b8d2
DC		 969
970 usb0_id_pins_b: usb0id1@0 {
971 reg = <0>;
972 fsl,pinmux-ids = <
973 MX28_PAD_PWM2__USB0_ID
974 >;
975 fsl,drive-strength = <MXS_DRIVE_12mA>;
976 fsl,voltage = <MXS_VOLTAGE_HIGH>;
977 fsl,pull-up = <MXS_PULL_ENABLE>;
978 };
979
bc3a59c1
DA		 980 };
981
296f8cd3 982 digctl: digctl@8001c000 {
115581cf 983 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
0f06cde7 984 reg = <0x8001c000 0x2000>;
bc3a59c1
DA		 985 interrupts = <89>;
986 status = "disabled";
987 };
988
296f8cd3 989 etm: etm@80022000 {
0f06cde7 990 reg = <0x80022000 0x2000>;
bc3a59c1
DA		 991 status = "disabled";
992 };
993
f30fb03d 994 dma_apbx: dma-apbx@80024000 {
84f3570a 995 compatible = "fsl,imx28-dma-apbx";
0f06cde7 996 reg = <0x80024000 0x2000>;
f30fb03d
SG		 997 interrupts = <78 79 66 0
998 80 81 68 69
999 70 71 72 73
1000 74 75 76 77>;
4ada77e3 1001 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
f30fb03d
SG		 1002 "saif0", "saif1", "i2c0", "i2c1",
1003 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
1004 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
1005 #dma-cells = <1>;
1006 dma-channels = <16>;
b598b9f3 1007 clocks = <&clks 26>;
bc3a59c1
DA		 1008 };
1009
296f8cd3 1010 dcp: dcp@80028000 {
7d56a28f 1011 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
0f06cde7 1012 reg = <0x80028000 0x2000>;
bc3a59c1 1013 interrupts = <52 53 54>;
7d56a28f 1014 status = "okay";
bc3a59c1
DA		 1015 };
1016
296f8cd3 1017 pxp: pxp@8002a000 {
0f06cde7 1018 reg = <0x8002a000 0x2000>;
bc3a59c1
DA		 1019 interrupts = <39>;
1020 status = "disabled";
1021 };
1022
296f8cd3 1023 ocotp: ocotp@8002c000 {
a7be1e68
SW		 1024 compatible = "fsl,imx28-ocotp", "fsl,ocotp";
1025 #address-cells = <1>;
1026 #size-cells = <1>;
0f06cde7 1027 reg = <0x8002c000 0x2000>;
a7be1e68 1028 clocks = <&clks 25>;
bc3a59c1
DA		 1029 };
1030
1031 axi-ahb@8002e000 {
0f06cde7 1032 reg = <0x8002e000 0x2000>;
bc3a59c1
DA		 1033 status = "disabled";
1034 };
1035
296f8cd3 1036 lcdif: lcdif@80030000 {
a915ee42 1037 compatible = "fsl,imx28-lcdif";
0f06cde7 1038 reg = <0x80030000 0x2000>;
7f2b9288 1039 interrupts = <38>;
b598b9f3 1040 clocks = <&clks 55>;
f30fb03d
SG		 1041 dmas = <&dma_apbh 13>;
1042 dma-names = "rx";
bc3a59c1
DA		 1043 status = "disabled";
1044 };
1045
1046 can0: can@80032000 {
d50f4630 1047 compatible = "fsl,imx28-flexcan";
0f06cde7 1048 reg = <0x80032000 0x2000>;
bc3a59c1 1049 interrupts = <8>;
b598b9f3
SG		 1050 clocks = <&clks 58>, <&clks 58>;
1051 clock-names = "ipg", "per";
bc3a59c1
DA		 1052 status = "disabled";
1053 };
1054
1055 can1: can@80034000 {
d50f4630 1056 compatible = "fsl,imx28-flexcan";
0f06cde7 1057 reg = <0x80034000 0x2000>;
bc3a59c1 1058 interrupts = <9>;
b598b9f3
SG		 1059 clocks = <&clks 59>, <&clks 59>;
1060 clock-names = "ipg", "per";
bc3a59c1
DA		 1061 status = "disabled";
1062 };
1063
296f8cd3 1064 simdbg: simdbg@8003c000 {
0f06cde7 1065 reg = <0x8003c000 0x200>;
bc3a59c1
DA		 1066 status = "disabled";
1067 };
1068
296f8cd3 1069 simgpmisel: simgpmisel@8003c200 {
0f06cde7 1070 reg = <0x8003c200 0x100>;
bc3a59c1
DA		 1071 status = "disabled";
1072 };
1073
296f8cd3 1074 simsspsel: simsspsel@8003c300 {
0f06cde7 1075 reg = <0x8003c300 0x100>;
bc3a59c1
DA		 1076 status = "disabled";
1077 };
1078
296f8cd3 1079 simmemsel: simmemsel@8003c400 {
0f06cde7 1080 reg = <0x8003c400 0x100>;
bc3a59c1
DA		 1081 status = "disabled";
1082 };
1083
296f8cd3 1084 gpiomon: gpiomon@8003c500 {
0f06cde7 1085 reg = <0x8003c500 0x100>;
bc3a59c1
DA		 1086 status = "disabled";
1087 };
1088
296f8cd3 1089 simenet: simenet@8003c700 {
0f06cde7 1090 reg = <0x8003c700 0x100>;
bc3a59c1
DA		 1091 status = "disabled";
1092 };
1093
296f8cd3 1094 armjtag: armjtag@8003c800 {
0f06cde7 1095 reg = <0x8003c800 0x100>;
bc3a59c1
DA		 1096 status = "disabled";
1097 };
07a3ce7f 1098 };
bc3a59c1
DA		 1099
1100 apbx@80040000 {
1101 compatible = "simple-bus";
1102 #address-cells = <1>;
1103 #size-cells = <1>;
1104 reg = <0x80040000 0x40000>;
1105 ranges;
1106
b598b9f3 1107 clks: clkctrl@80040000 {
8f7cf881 1108 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
0f06cde7 1109 reg = <0x80040000 0x2000>;
b598b9f3 1110 #clock-cells = <1>;
bc3a59c1
DA		 1111 };
1112
1113 saif0: saif@80042000 {
27767d68 1114 #sound-dai-cells = <0>;
530f1d41 1115 compatible = "fsl,imx28-saif";
0f06cde7 1116 reg = <0x80042000 0x2000>;
7f2b9288 1117 interrupts = <59>;
66acaf3f 1118 #clock-cells = <0>;
b598b9f3 1119 clocks = <&clks 53>;
f30fb03d
SG		 1120 dmas = <&dma_apbx 4>;
1121 dma-names = "rx-tx";
bc3a59c1
DA		 1122 status = "disabled";
1123 };
1124
296f8cd3 1125 power: power@80044000 {
0f06cde7 1126 reg = <0x80044000 0x2000>;
bc3a59c1
DA		 1127 status = "disabled";
1128 };
1129
1130 saif1: saif@80046000 {
27767d68 1131 #sound-dai-cells = <0>;
530f1d41 1132 compatible = "fsl,imx28-saif";
0f06cde7 1133 reg = <0x80046000 0x2000>;
7f2b9288 1134 interrupts = <58>;
b598b9f3 1135 clocks = <&clks 54>;
f30fb03d
SG		 1136 dmas = <&dma_apbx 5>;
1137 dma-names = "rx-tx";
bc3a59c1
DA		 1138 status = "disabled";
1139 };
1140
296f8cd3 1141 lradc: lradc@80050000 {
aef35104 1142 compatible = "fsl,imx28-lradc";
0f06cde7 1143 reg = <0x80050000 0x2000>;
aef35104
MV		 1144 interrupts = <10 14 15 16 17 18 19
1145 20 21 22 23 24 25>;
bc3a59c1 1146 status = "disabled";
18da755d 1147 clocks = <&clks 41>;
40dde681 1148 #io-channel-cells = <1>;
bc3a59c1
DA		 1149 };
1150
296f8cd3 1151 spdif: spdif@80054000 {
0f06cde7 1152 reg = <0x80054000 0x2000>;
7f2b9288 1153 interrupts = <45>;
f30fb03d
SG		 1154 dmas = <&dma_apbx 2>;
1155 dma-names = "tx";
bc3a59c1
DA		 1156 status = "disabled";
1157 };
1158
296f8cd3 1159 mxs_rtc: rtc@80056000 {
f98c990c 1160 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
0f06cde7 1161 reg = <0x80056000 0x2000>;
f98c990c 1162 interrupts = <29>;
bc3a59c1
DA		 1163 };
1164
1165 i2c0: i2c@80058000 {
2a96e391
SG		 1166 #address-cells = <1>;
1167 #size-cells = <0>;
1168 compatible = "fsl,imx28-i2c";
0f06cde7 1169 reg = <0x80058000 0x2000>;
7f2b9288 1170 interrupts = <111>;
cd4f2d4a 1171 clock-frequency = <100000>;
f30fb03d
SG		 1172 dmas = <&dma_apbx 6>;
1173 dma-names = "rx-tx";
bc3a59c1
DA		 1174 status = "disabled";
1175 };
1176
1177 i2c1: i2c@8005a000 {
2a96e391
SG		 1178 #address-cells = <1>;
1179 #size-cells = <0>;
1180 compatible = "fsl,imx28-i2c";
0f06cde7 1181 reg = <0x8005a000 0x2000>;
7f2b9288 1182 interrupts = <110>;
cd4f2d4a 1183 clock-frequency = <100000>;
f30fb03d
SG		 1184 dmas = <&dma_apbx 7>;
1185 dma-names = "rx-tx";
bc3a59c1
DA		 1186 status = "disabled";
1187 };
1188
52f7176b
SG		 1189 pwm: pwm@80064000 {
1190 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
0f06cde7 1191 reg = <0x80064000 0x2000>;
b598b9f3 1192 clocks = <&clks 44>;
52f7176b
SG		 1193 #pwm-cells = <2>;
1194 fsl,pwm-number = <8>;
bc3a59c1
DA		 1195 status = "disabled";
1196 };
1197
296f8cd3 1198 timer: timrot@80068000 {
eeca6e60 1199 compatible = "fsl,imx28-timrot", "fsl,timrot";
0f06cde7 1200 reg = <0x80068000 0x2000>;
eeca6e60 1201 interrupts = <48 49 50 51>;
2efb9504 1202 clocks = <&clks 26>;
bc3a59c1
DA		 1203 };
1204
1205 auart0: serial@8006a000 {
80d969e4 1206 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1207 reg = <0x8006a000 0x2000>;
7f2b9288 1208 interrupts = <112>;
f30fb03d
SG		 1209 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1210 dma-names = "rx", "tx";
b598b9f3 1211 clocks = <&clks 45>;
bc3a59c1
DA		 1212 status = "disabled";
1213 };
1214
1215 auart1: serial@8006c000 {
80d969e4 1216 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1217 reg = <0x8006c000 0x2000>;
7f2b9288 1218 interrupts = <113>;
f30fb03d
SG		 1219 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1220 dma-names = "rx", "tx";
b598b9f3 1221 clocks = <&clks 45>;
bc3a59c1
DA		 1222 status = "disabled";
1223 };
1224
1225 auart2: serial@8006e000 {
80d969e4 1226 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1227 reg = <0x8006e000 0x2000>;
7f2b9288 1228 interrupts = <114>;
f30fb03d
SG		 1229 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1230 dma-names = "rx", "tx";
b598b9f3 1231 clocks = <&clks 45>;
bc3a59c1
DA		 1232 status = "disabled";
1233 };
1234
1235 auart3: serial@80070000 {
80d969e4 1236 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1237 reg = <0x80070000 0x2000>;
7f2b9288 1238 interrupts = <115>;
f30fb03d
SG		 1239 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1240 dma-names = "rx", "tx";
b598b9f3 1241 clocks = <&clks 45>;
bc3a59c1
DA		 1242 status = "disabled";
1243 };
1244
1245 auart4: serial@80072000 {
80d969e4 1246 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1247 reg = <0x80072000 0x2000>;
7f2b9288 1248 interrupts = <116>;
f30fb03d
SG		 1249 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1250 dma-names = "rx", "tx";
b598b9f3 1251 clocks = <&clks 45>;
bc3a59c1
DA		 1252 status = "disabled";
1253 };
1254
1255 duart: serial@80074000 {
1256 compatible = "arm,pl011", "arm,primecell";
1257 reg = <0x80074000 0x1000>;
1258 interrupts = <47>;
b598b9f3
SG		 1259 clocks = <&clks 45>, <&clks 26>;
1260 clock-names = "uart", "apb_pclk";
bc3a59c1
DA		 1261 status = "disabled";
1262 };
1263
1264 usbphy0: usbphy@8007c000 {
5da01270 1265 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 1266 reg = <0x8007c000 0x2000>;
b598b9f3 1267 clocks = <&clks 62>;
bc3a59c1
DA		 1268 status = "disabled";
1269 };
1270
1271 usbphy1: usbphy@8007e000 {
5da01270 1272 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 1273 reg = <0x8007e000 0x2000>;
b598b9f3 1274 clocks = <&clks 63>;
bc3a59c1
DA		 1275 status = "disabled";
1276 };
1277 };
1278 };
1279
1280 ahb@80080000 {
1281 compatible = "simple-bus";
1282 #address-cells = <1>;
1283 #size-cells = <1>;
1284 reg = <0x80080000 0x80000>;
1285 ranges;
1286
5da01270
RZ		 1287 usb0: usb@80080000 {
1288 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 1289 reg = <0x80080000 0x10000>;
5da01270 1290 interrupts = <93>;
b598b9f3 1291 clocks = <&clks 60>;
5da01270 1292 fsl,usbphy = <&usbphy0>;
bc3a59c1
DA		 1293 status = "disabled";
1294 };
1295
5da01270
RZ		 1296 usb1: usb@80090000 {
1297 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 1298 reg = <0x80090000 0x10000>;
5da01270 1299 interrupts = <92>;
b598b9f3 1300 clocks = <&clks 61>;
5da01270 1301 fsl,usbphy = <&usbphy1>;
3ec481ed 1302 dr_mode = "host";
bc3a59c1
DA		 1303 status = "disabled";
1304 };
1305
296f8cd3 1306 dflpt: dflpt@800c0000 {
bc3a59c1
DA		 1307 reg = <0x800c0000 0x10000>;
1308 status = "disabled";
1309 };
1310
1311 mac0: ethernet@800f0000 {
1312 compatible = "fsl,imx28-fec";
1313 reg = <0x800f0000 0x4000>;
1314 interrupts = <101>;
f231a9fe
WS		 1315 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1316 clock-names = "ipg", "ahb", "enet_out";
bc3a59c1
DA		 1317 status = "disabled";
1318 };
1319
1320 mac1: ethernet@800f4000 {
1321 compatible = "fsl,imx28-fec";
1322 reg = <0x800f4000 0x4000>;
1323 interrupts = <102>;
b598b9f3
SG		 1324 clocks = <&clks 57>, <&clks 57>;
1325 clock-names = "ipg", "ahb";
bc3a59c1
DA		 1326 status = "disabled";
1327 };
1328
296f8cd3 1329 etn_switch: switch@800f8000 {
bc3a59c1
DA		 1330 reg = <0x800f8000 0x8000>;
1331 status = "disabled";
1332 };
bc3a59c1 1333 };
f92dfb02 1334
0b452ccc 1335 iio-hwmon {
f92dfb02
AB		 1336 compatible = "iio-hwmon";
1337 io-channels = <&lradc 8>;
1338 };
bc3a59c1 1339};
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