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Commit | Line | Data |
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bc3a59c1 DA |
1 | /* |
2 | * Copyright 2012 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
25fc228e | 12 | #include <dt-bindings/gpio/gpio.h> |
bc3875f1 | 13 | #include "imx28-pinfunc.h" |
bc3a59c1 DA |
14 | |
15 | / { | |
7f107887 FE |
16 | #address-cells = <1>; |
17 | #size-cells = <1>; | |
18 | ||
bc3a59c1 DA |
19 | interrupt-parent = <&icoll>; |
20 | ||
ce4c6f9b | 21 | aliases { |
6bf6eb09 FE |
22 | ethernet0 = &mac0; |
23 | ethernet1 = &mac1; | |
ce4c6f9b SG |
24 | gpio0 = &gpio0; |
25 | gpio1 = &gpio1; | |
26 | gpio2 = &gpio2; | |
27 | gpio3 = &gpio3; | |
28 | gpio4 = &gpio4; | |
530f1d41 SG |
29 | saif0 = &saif0; |
30 | saif1 = &saif1; | |
80d969e4 FE |
31 | serial0 = &auart0; |
32 | serial1 = &auart1; | |
33 | serial2 = &auart2; | |
34 | serial3 = &auart3; | |
35 | serial4 = &auart4; | |
6bf6eb09 FE |
36 | spi0 = &ssp1; |
37 | spi1 = &ssp2; | |
1f35cc6a PC |
38 | usbphy0 = &usbphy0; |
39 | usbphy1 = &usbphy1; | |
ce4c6f9b SG |
40 | }; |
41 | ||
bc3a59c1 | 42 | cpus { |
7925e89f LP |
43 | #address-cells = <0>; |
44 | #size-cells = <0>; | |
45 | ||
46 | cpu { | |
47 | compatible = "arm,arm926ej-s"; | |
48 | device_type = "cpu"; | |
bc3a59c1 DA |
49 | }; |
50 | }; | |
51 | ||
52 | apb@80000000 { | |
53 | compatible = "simple-bus"; | |
54 | #address-cells = <1>; | |
55 | #size-cells = <1>; | |
56 | reg = <0x80000000 0x80000>; | |
57 | ranges; | |
58 | ||
59 | apbh@80000000 { | |
60 | compatible = "simple-bus"; | |
61 | #address-cells = <1>; | |
62 | #size-cells = <1>; | |
63 | reg = <0x80000000 0x3c900>; | |
64 | ranges; | |
65 | ||
66 | icoll: interrupt-controller@80000000 { | |
83a84efc | 67 | compatible = "fsl,imx28-icoll", "fsl,icoll"; |
bc3a59c1 DA |
68 | interrupt-controller; |
69 | #interrupt-cells = <1>; | |
70 | reg = <0x80000000 0x2000>; | |
71 | }; | |
72 | ||
296f8cd3 | 73 | hsadc: hsadc@80002000 { |
0f06cde7 | 74 | reg = <0x80002000 0x2000>; |
7f2b9288 | 75 | interrupts = <13>; |
f30fb03d SG |
76 | dmas = <&dma_apbh 12>; |
77 | dma-names = "rx"; | |
bc3a59c1 DA |
78 | status = "disabled"; |
79 | }; | |
80 | ||
f30fb03d | 81 | dma_apbh: dma-apbh@80004000 { |
84f3570a | 82 | compatible = "fsl,imx28-dma-apbh"; |
0f06cde7 | 83 | reg = <0x80004000 0x2000>; |
f30fb03d SG |
84 | interrupts = <82 83 84 85 |
85 | 88 88 88 88 | |
86 | 88 88 88 88 | |
87 | 87 86 0 0>; | |
88 | interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3", | |
89 | "gpmi0", "gmpi1", "gpmi2", "gmpi3", | |
90 | "gpmi4", "gmpi5", "gpmi6", "gmpi7", | |
91 | "hsadc", "lcdif", "empty", "empty"; | |
92 | #dma-cells = <1>; | |
93 | dma-channels = <16>; | |
b598b9f3 | 94 | clocks = <&clks 25>; |
bc3a59c1 DA |
95 | }; |
96 | ||
296f8cd3 | 97 | perfmon: perfmon@80006000 { |
0f06cde7 | 98 | reg = <0x80006000 0x800>; |
bc3a59c1 DA |
99 | interrupts = <27>; |
100 | status = "disabled"; | |
101 | }; | |
102 | ||
296f8cd3 | 103 | gpmi: gpmi-nand@8000c000 { |
7a8e5149 HS |
104 | compatible = "fsl,imx28-gpmi-nand"; |
105 | #address-cells = <1>; | |
106 | #size-cells = <1>; | |
0f06cde7 | 107 | reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; |
7a8e5149 | 108 | reg-names = "gpmi-nand", "bch"; |
7f2b9288 SG |
109 | interrupts = <41>; |
110 | interrupt-names = "bch"; | |
b598b9f3 | 111 | clocks = <&clks 50>; |
b6442559 | 112 | clock-names = "gpmi_io"; |
f30fb03d SG |
113 | dmas = <&dma_apbh 4>; |
114 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
115 | status = "disabled"; |
116 | }; | |
117 | ||
118 | ssp0: ssp@80010000 { | |
41bf5706 MR |
119 | #address-cells = <1>; |
120 | #size-cells = <0>; | |
0f06cde7 | 121 | reg = <0x80010000 0x2000>; |
7f2b9288 | 122 | interrupts = <96>; |
b598b9f3 | 123 | clocks = <&clks 46>; |
f30fb03d SG |
124 | dmas = <&dma_apbh 0>; |
125 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
126 | status = "disabled"; |
127 | }; | |
128 | ||
129 | ssp1: ssp@80012000 { | |
41bf5706 MR |
130 | #address-cells = <1>; |
131 | #size-cells = <0>; | |
0f06cde7 | 132 | reg = <0x80012000 0x2000>; |
7f2b9288 | 133 | interrupts = <97>; |
b598b9f3 | 134 | clocks = <&clks 47>; |
f30fb03d SG |
135 | dmas = <&dma_apbh 1>; |
136 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
137 | status = "disabled"; |
138 | }; | |
139 | ||
140 | ssp2: ssp@80014000 { | |
41bf5706 MR |
141 | #address-cells = <1>; |
142 | #size-cells = <0>; | |
0f06cde7 | 143 | reg = <0x80014000 0x2000>; |
7f2b9288 | 144 | interrupts = <98>; |
b598b9f3 | 145 | clocks = <&clks 48>; |
f30fb03d SG |
146 | dmas = <&dma_apbh 2>; |
147 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
148 | status = "disabled"; |
149 | }; | |
150 | ||
151 | ssp3: ssp@80016000 { | |
41bf5706 MR |
152 | #address-cells = <1>; |
153 | #size-cells = <0>; | |
0f06cde7 | 154 | reg = <0x80016000 0x2000>; |
7f2b9288 | 155 | interrupts = <99>; |
b598b9f3 | 156 | clocks = <&clks 49>; |
f30fb03d SG |
157 | dmas = <&dma_apbh 3>; |
158 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
159 | status = "disabled"; |
160 | }; | |
161 | ||
296f8cd3 | 162 | pinctrl: pinctrl@80018000 { |
bc3a59c1 DA |
163 | #address-cells = <1>; |
164 | #size-cells = <0>; | |
ce4c6f9b | 165 | compatible = "fsl,imx28-pinctrl", "simple-bus"; |
0f06cde7 | 166 | reg = <0x80018000 0x2000>; |
bc3a59c1 | 167 | |
ce4c6f9b SG |
168 | gpio0: gpio@0 { |
169 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
e57609aa | 170 | reg = <0>; |
ce4c6f9b SG |
171 | interrupts = <127>; |
172 | gpio-controller; | |
173 | #gpio-cells = <2>; | |
174 | interrupt-controller; | |
175 | #interrupt-cells = <2>; | |
176 | }; | |
177 | ||
178 | gpio1: gpio@1 { | |
179 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
e57609aa | 180 | reg = <1>; |
ce4c6f9b SG |
181 | interrupts = <126>; |
182 | gpio-controller; | |
183 | #gpio-cells = <2>; | |
184 | interrupt-controller; | |
185 | #interrupt-cells = <2>; | |
186 | }; | |
187 | ||
188 | gpio2: gpio@2 { | |
189 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
e57609aa | 190 | reg = <2>; |
ce4c6f9b SG |
191 | interrupts = <125>; |
192 | gpio-controller; | |
193 | #gpio-cells = <2>; | |
194 | interrupt-controller; | |
195 | #interrupt-cells = <2>; | |
196 | }; | |
197 | ||
198 | gpio3: gpio@3 { | |
199 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
e57609aa | 200 | reg = <3>; |
ce4c6f9b SG |
201 | interrupts = <124>; |
202 | gpio-controller; | |
203 | #gpio-cells = <2>; | |
204 | interrupt-controller; | |
205 | #interrupt-cells = <2>; | |
206 | }; | |
207 | ||
208 | gpio4: gpio@4 { | |
209 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
e57609aa | 210 | reg = <4>; |
ce4c6f9b SG |
211 | interrupts = <123>; |
212 | gpio-controller; | |
213 | #gpio-cells = <2>; | |
214 | interrupt-controller; | |
215 | #interrupt-cells = <2>; | |
216 | }; | |
217 | ||
bc3a59c1 DA |
218 | duart_pins_a: duart@0 { |
219 | reg = <0>; | |
f14da767 | 220 | fsl,pinmux-ids = < |
bc3875f1 LW |
221 | MX28_PAD_PWM0__DUART_RX |
222 | MX28_PAD_PWM1__DUART_TX | |
f14da767 | 223 | >; |
4191c340 LW |
224 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
225 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
226 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
bc3a59c1 DA |
227 | }; |
228 | ||
8385e7c1 MR |
229 | duart_pins_b: duart@1 { |
230 | reg = <1>; | |
f14da767 | 231 | fsl,pinmux-ids = < |
bc3875f1 LW |
232 | MX28_PAD_AUART0_CTS__DUART_RX |
233 | MX28_PAD_AUART0_RTS__DUART_TX | |
f14da767 | 234 | >; |
4191c340 LW |
235 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
236 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
237 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
8385e7c1 MR |
238 | }; |
239 | ||
e1a4d18f SG |
240 | duart_4pins_a: duart-4pins@0 { |
241 | reg = <0>; | |
242 | fsl,pinmux-ids = < | |
bc3875f1 LW |
243 | MX28_PAD_AUART0_CTS__DUART_RX |
244 | MX28_PAD_AUART0_RTS__DUART_TX | |
245 | MX28_PAD_AUART0_RX__DUART_CTS | |
246 | MX28_PAD_AUART0_TX__DUART_RTS | |
e1a4d18f | 247 | >; |
4191c340 LW |
248 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
249 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
250 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
e1a4d18f SG |
251 | }; |
252 | ||
7a8e5149 HS |
253 | gpmi_pins_a: gpmi-nand@0 { |
254 | reg = <0>; | |
f14da767 | 255 | fsl,pinmux-ids = < |
bc3875f1 LW |
256 | MX28_PAD_GPMI_D00__GPMI_D0 |
257 | MX28_PAD_GPMI_D01__GPMI_D1 | |
258 | MX28_PAD_GPMI_D02__GPMI_D2 | |
259 | MX28_PAD_GPMI_D03__GPMI_D3 | |
260 | MX28_PAD_GPMI_D04__GPMI_D4 | |
261 | MX28_PAD_GPMI_D05__GPMI_D5 | |
262 | MX28_PAD_GPMI_D06__GPMI_D6 | |
263 | MX28_PAD_GPMI_D07__GPMI_D7 | |
264 | MX28_PAD_GPMI_CE0N__GPMI_CE0N | |
265 | MX28_PAD_GPMI_RDY0__GPMI_READY0 | |
266 | MX28_PAD_GPMI_RDN__GPMI_RDN | |
267 | MX28_PAD_GPMI_WRN__GPMI_WRN | |
268 | MX28_PAD_GPMI_ALE__GPMI_ALE | |
269 | MX28_PAD_GPMI_CLE__GPMI_CLE | |
270 | MX28_PAD_GPMI_RESETN__GPMI_RESETN | |
f14da767 | 271 | >; |
4191c340 LW |
272 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
273 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
274 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
7a8e5149 HS |
275 | }; |
276 | ||
277 | gpmi_status_cfg: gpmi-status-cfg { | |
f14da767 | 278 | fsl,pinmux-ids = < |
bc3875f1 LW |
279 | MX28_PAD_GPMI_RDN__GPMI_RDN |
280 | MX28_PAD_GPMI_WRN__GPMI_WRN | |
281 | MX28_PAD_GPMI_RESETN__GPMI_RESETN | |
f14da767 | 282 | >; |
4191c340 | 283 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
7a8e5149 HS |
284 | }; |
285 | ||
80d969e4 FE |
286 | auart0_pins_a: auart0@0 { |
287 | reg = <0>; | |
f14da767 | 288 | fsl,pinmux-ids = < |
bc3875f1 LW |
289 | MX28_PAD_AUART0_RX__AUART0_RX |
290 | MX28_PAD_AUART0_TX__AUART0_TX | |
291 | MX28_PAD_AUART0_CTS__AUART0_CTS | |
292 | MX28_PAD_AUART0_RTS__AUART0_RTS | |
f14da767 | 293 | >; |
4191c340 LW |
294 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
295 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
296 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
8fa62e11 MV |
297 | }; |
298 | ||
299 | auart0_2pins_a: auart0-2pins@0 { | |
300 | reg = <0>; | |
301 | fsl,pinmux-ids = < | |
bc3875f1 LW |
302 | MX28_PAD_AUART0_RX__AUART0_RX |
303 | MX28_PAD_AUART0_TX__AUART0_TX | |
8fa62e11 | 304 | >; |
4191c340 LW |
305 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
306 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
307 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
80d969e4 FE |
308 | }; |
309 | ||
e1a4d18f SG |
310 | auart1_pins_a: auart1@0 { |
311 | reg = <0>; | |
312 | fsl,pinmux-ids = < | |
bc3875f1 LW |
313 | MX28_PAD_AUART1_RX__AUART1_RX |
314 | MX28_PAD_AUART1_TX__AUART1_TX | |
315 | MX28_PAD_AUART1_CTS__AUART1_CTS | |
316 | MX28_PAD_AUART1_RTS__AUART1_RTS | |
e1a4d18f | 317 | >; |
4191c340 LW |
318 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
319 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
320 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
e1a4d18f SG |
321 | }; |
322 | ||
3143bbb4 SG |
323 | auart1_2pins_a: auart1-2pins@0 { |
324 | reg = <0>; | |
325 | fsl,pinmux-ids = < | |
bc3875f1 LW |
326 | MX28_PAD_AUART1_RX__AUART1_RX |
327 | MX28_PAD_AUART1_TX__AUART1_TX | |
3143bbb4 | 328 | >; |
4191c340 LW |
329 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
330 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
331 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
3143bbb4 SG |
332 | }; |
333 | ||
334 | auart2_2pins_a: auart2-2pins@0 { | |
335 | reg = <0>; | |
336 | fsl,pinmux-ids = < | |
bc3875f1 LW |
337 | MX28_PAD_SSP2_SCK__AUART2_RX |
338 | MX28_PAD_SSP2_MOSI__AUART2_TX | |
3143bbb4 | 339 | >; |
4191c340 LW |
340 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
341 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
342 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
3143bbb4 SG |
343 | }; |
344 | ||
f8040cf5 EB |
345 | auart2_2pins_b: auart2-2pins@1 { |
346 | reg = <1>; | |
347 | fsl,pinmux-ids = < | |
bc3875f1 LW |
348 | MX28_PAD_AUART2_RX__AUART2_RX |
349 | MX28_PAD_AUART2_TX__AUART2_TX | |
f8040cf5 | 350 | >; |
4191c340 LW |
351 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
352 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
353 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
f8040cf5 EB |
354 | }; |
355 | ||
cd0214c3 AM |
356 | auart2_pins_a: auart2-pins@0 { |
357 | reg = <0>; | |
358 | fsl,pinmux-ids = < | |
359 | MX28_PAD_AUART2_RX__AUART2_RX | |
360 | MX28_PAD_AUART2_TX__AUART2_TX | |
361 | MX28_PAD_AUART2_CTS__AUART2_CTS | |
362 | MX28_PAD_AUART2_RTS__AUART2_RTS | |
363 | >; | |
364 | fsl,drive-strength = <MXS_DRIVE_4mA>; | |
365 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
366 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
367 | }; | |
368 | ||
80d969e4 FE |
369 | auart3_pins_a: auart3@0 { |
370 | reg = <0>; | |
f14da767 | 371 | fsl,pinmux-ids = < |
bc3875f1 LW |
372 | MX28_PAD_AUART3_RX__AUART3_RX |
373 | MX28_PAD_AUART3_TX__AUART3_TX | |
374 | MX28_PAD_AUART3_CTS__AUART3_CTS | |
375 | MX28_PAD_AUART3_RTS__AUART3_RTS | |
f14da767 | 376 | >; |
4191c340 LW |
377 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
378 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
379 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
80d969e4 FE |
380 | }; |
381 | ||
3143bbb4 SG |
382 | auart3_2pins_a: auart3-2pins@0 { |
383 | reg = <0>; | |
384 | fsl,pinmux-ids = < | |
bc3875f1 LW |
385 | MX28_PAD_SSP2_MISO__AUART3_RX |
386 | MX28_PAD_SSP2_SS0__AUART3_TX | |
3143bbb4 | 387 | >; |
4191c340 LW |
388 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
389 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
390 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
3143bbb4 SG |
391 | }; |
392 | ||
4812e746 EB |
393 | auart3_2pins_b: auart3-2pins@1 { |
394 | reg = <1>; | |
395 | fsl,pinmux-ids = < | |
bc3875f1 LW |
396 | MX28_PAD_AUART3_RX__AUART3_RX |
397 | MX28_PAD_AUART3_TX__AUART3_TX | |
4812e746 | 398 | >; |
4191c340 LW |
399 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
400 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
401 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
4812e746 EB |
402 | }; |
403 | ||
33678d12 EB |
404 | auart4_2pins_a: auart4@0 { |
405 | reg = <0>; | |
406 | fsl,pinmux-ids = < | |
bc3875f1 LW |
407 | MX28_PAD_SSP3_SCK__AUART4_TX |
408 | MX28_PAD_SSP3_MOSI__AUART4_RX | |
33678d12 | 409 | >; |
4191c340 LW |
410 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
411 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
412 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
33678d12 EB |
413 | }; |
414 | ||
cfa1dd99 MR |
415 | auart4_2pins_b: auart4@1 { |
416 | reg = <1>; | |
417 | fsl,pinmux-ids = < | |
418 | MX28_PAD_AUART0_CTS__AUART4_RX | |
419 | MX28_PAD_AUART0_RTS__AUART4_TX | |
420 | >; | |
421 | fsl,drive-strength = <MXS_DRIVE_4mA>; | |
422 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
423 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
424 | }; | |
425 | ||
bc3a59c1 DA |
426 | mac0_pins_a: mac0@0 { |
427 | reg = <0>; | |
f14da767 | 428 | fsl,pinmux-ids = < |
bc3875f1 LW |
429 | MX28_PAD_ENET0_MDC__ENET0_MDC |
430 | MX28_PAD_ENET0_MDIO__ENET0_MDIO | |
431 | MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | |
432 | MX28_PAD_ENET0_RXD0__ENET0_RXD0 | |
433 | MX28_PAD_ENET0_RXD1__ENET0_RXD1 | |
434 | MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | |
435 | MX28_PAD_ENET0_TXD0__ENET0_TXD0 | |
436 | MX28_PAD_ENET0_TXD1__ENET0_TXD1 | |
437 | MX28_PAD_ENET_CLK__CLKCTRL_ENET | |
f14da767 | 438 | >; |
4191c340 LW |
439 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
440 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
441 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
bc3a59c1 DA |
442 | }; |
443 | ||
9eb7db1c UKK |
444 | mac0_pins_b: mac0@1 { |
445 | reg = <1>; | |
446 | fsl,pinmux-ids = < | |
447 | MX28_PAD_ENET0_MDC__ENET0_MDC | |
448 | MX28_PAD_ENET0_MDIO__ENET0_MDIO | |
449 | MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | |
450 | MX28_PAD_ENET0_RXD0__ENET0_RXD0 | |
451 | MX28_PAD_ENET0_RXD1__ENET0_RXD1 | |
452 | MX28_PAD_ENET0_RXD2__ENET0_RXD2 | |
453 | MX28_PAD_ENET0_RXD3__ENET0_RXD3 | |
454 | MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | |
455 | MX28_PAD_ENET0_TXD0__ENET0_TXD0 | |
456 | MX28_PAD_ENET0_TXD1__ENET0_TXD1 | |
457 | MX28_PAD_ENET0_TXD2__ENET0_TXD2 | |
458 | MX28_PAD_ENET0_TXD3__ENET0_TXD3 | |
459 | MX28_PAD_ENET_CLK__CLKCTRL_ENET | |
460 | MX28_PAD_ENET0_COL__ENET0_COL | |
461 | MX28_PAD_ENET0_CRS__ENET0_CRS | |
462 | MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK | |
463 | MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK | |
464 | >; | |
465 | fsl,drive-strength = <MXS_DRIVE_8mA>; | |
466 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
467 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
468 | }; | |
469 | ||
bc3a59c1 DA |
470 | mac1_pins_a: mac1@0 { |
471 | reg = <0>; | |
f14da767 | 472 | fsl,pinmux-ids = < |
bc3875f1 LW |
473 | MX28_PAD_ENET0_CRS__ENET1_RX_EN |
474 | MX28_PAD_ENET0_RXD2__ENET1_RXD0 | |
475 | MX28_PAD_ENET0_RXD3__ENET1_RXD1 | |
476 | MX28_PAD_ENET0_COL__ENET1_TX_EN | |
477 | MX28_PAD_ENET0_TXD2__ENET1_TXD0 | |
478 | MX28_PAD_ENET0_TXD3__ENET1_TXD1 | |
f14da767 | 479 | >; |
4191c340 LW |
480 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
481 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
482 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
bc3a59c1 | 483 | }; |
35d23047 SG |
484 | |
485 | mmc0_8bit_pins_a: mmc0-8bit@0 { | |
486 | reg = <0>; | |
f14da767 | 487 | fsl,pinmux-ids = < |
bc3875f1 LW |
488 | MX28_PAD_SSP0_DATA0__SSP0_D0 |
489 | MX28_PAD_SSP0_DATA1__SSP0_D1 | |
490 | MX28_PAD_SSP0_DATA2__SSP0_D2 | |
491 | MX28_PAD_SSP0_DATA3__SSP0_D3 | |
492 | MX28_PAD_SSP0_DATA4__SSP0_D4 | |
493 | MX28_PAD_SSP0_DATA5__SSP0_D5 | |
494 | MX28_PAD_SSP0_DATA6__SSP0_D6 | |
495 | MX28_PAD_SSP0_DATA7__SSP0_D7 | |
496 | MX28_PAD_SSP0_CMD__SSP0_CMD | |
497 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | |
498 | MX28_PAD_SSP0_SCK__SSP0_SCK | |
f14da767 | 499 | >; |
4191c340 LW |
500 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
501 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
502 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
35d23047 SG |
503 | }; |
504 | ||
8385e7c1 MR |
505 | mmc0_4bit_pins_a: mmc0-4bit@0 { |
506 | reg = <0>; | |
f14da767 | 507 | fsl,pinmux-ids = < |
bc3875f1 LW |
508 | MX28_PAD_SSP0_DATA0__SSP0_D0 |
509 | MX28_PAD_SSP0_DATA1__SSP0_D1 | |
510 | MX28_PAD_SSP0_DATA2__SSP0_D2 | |
511 | MX28_PAD_SSP0_DATA3__SSP0_D3 | |
512 | MX28_PAD_SSP0_CMD__SSP0_CMD | |
513 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | |
514 | MX28_PAD_SSP0_SCK__SSP0_SCK | |
f14da767 | 515 | >; |
4191c340 LW |
516 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
517 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
518 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
8385e7c1 MR |
519 | }; |
520 | ||
35d23047 | 521 | mmc0_cd_cfg: mmc0-cd-cfg { |
f14da767 | 522 | fsl,pinmux-ids = < |
bc3875f1 | 523 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
f14da767 | 524 | >; |
4191c340 | 525 | fsl,pull-up = <MXS_PULL_DISABLE>; |
35d23047 SG |
526 | }; |
527 | ||
528 | mmc0_sck_cfg: mmc0-sck-cfg { | |
f14da767 | 529 | fsl,pinmux-ids = < |
bc3875f1 | 530 | MX28_PAD_SSP0_SCK__SSP0_SCK |
f14da767 | 531 | >; |
4191c340 LW |
532 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
533 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
35d23047 | 534 | }; |
2a96e391 | 535 | |
77d6386b MKB |
536 | mmc1_4bit_pins_a: mmc1-4bit@0 { |
537 | reg = <0>; | |
538 | fsl,pinmux-ids = < | |
539 | MX28_PAD_GPMI_D00__SSP1_D0 | |
540 | MX28_PAD_GPMI_D01__SSP1_D1 | |
541 | MX28_PAD_GPMI_D02__SSP1_D2 | |
542 | MX28_PAD_GPMI_D03__SSP1_D3 | |
543 | MX28_PAD_GPMI_RDY1__SSP1_CMD | |
544 | MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | |
545 | MX28_PAD_GPMI_WRN__SSP1_SCK | |
546 | >; | |
547 | fsl,drive-strength = <MXS_DRIVE_8mA>; | |
548 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
549 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
550 | }; | |
551 | ||
552 | mmc1_cd_cfg: mmc1-cd-cfg { | |
553 | fsl,pinmux-ids = < | |
554 | MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | |
555 | >; | |
556 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
557 | }; | |
558 | ||
559 | mmc1_sck_cfg: mmc1-sck-cfg { | |
560 | fsl,pinmux-ids = < | |
561 | MX28_PAD_GPMI_WRN__SSP1_SCK | |
562 | >; | |
563 | fsl,drive-strength = <MXS_DRIVE_12mA>; | |
564 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
565 | }; | |
566 | ||
567 | ||
5550e8e9 MV |
568 | mmc2_4bit_pins_a: mmc2-4bit@0 { |
569 | reg = <0>; | |
570 | fsl,pinmux-ids = < | |
571 | MX28_PAD_SSP0_DATA4__SSP2_D0 | |
572 | MX28_PAD_SSP1_SCK__SSP2_D1 | |
573 | MX28_PAD_SSP1_CMD__SSP2_D2 | |
574 | MX28_PAD_SSP0_DATA5__SSP2_D3 | |
575 | MX28_PAD_SSP0_DATA6__SSP2_CMD | |
576 | MX28_PAD_AUART1_RX__SSP2_CARD_DETECT | |
577 | MX28_PAD_SSP0_DATA7__SSP2_SCK | |
578 | >; | |
579 | fsl,drive-strength = <MXS_DRIVE_8mA>; | |
580 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
581 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
582 | }; | |
583 | ||
584 | mmc2_cd_cfg: mmc2-cd-cfg { | |
585 | fsl,pinmux-ids = < | |
586 | MX28_PAD_AUART1_RX__SSP2_CARD_DETECT | |
587 | >; | |
588 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
589 | }; | |
590 | ||
591 | mmc2_sck_cfg: mmc2-sck-cfg { | |
592 | fsl,pinmux-ids = < | |
593 | MX28_PAD_SSP0_DATA7__SSP2_SCK | |
594 | >; | |
595 | fsl,drive-strength = <MXS_DRIVE_12mA>; | |
596 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
35d23047 | 597 | }; |
2a96e391 SG |
598 | |
599 | i2c0_pins_a: i2c0@0 { | |
600 | reg = <0>; | |
f14da767 | 601 | fsl,pinmux-ids = < |
bc3875f1 LW |
602 | MX28_PAD_I2C0_SCL__I2C0_SCL |
603 | MX28_PAD_I2C0_SDA__I2C0_SDA | |
f14da767 | 604 | >; |
4191c340 LW |
605 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
606 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
607 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
2a96e391 | 608 | }; |
530f1d41 | 609 | |
5c697ea2 MR |
610 | i2c0_pins_b: i2c0@1 { |
611 | reg = <1>; | |
612 | fsl,pinmux-ids = < | |
bc3875f1 LW |
613 | MX28_PAD_AUART0_RX__I2C0_SCL |
614 | MX28_PAD_AUART0_TX__I2C0_SDA | |
5c697ea2 | 615 | >; |
4191c340 LW |
616 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
617 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
618 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
5c697ea2 MR |
619 | }; |
620 | ||
de7e934f MR |
621 | i2c1_pins_a: i2c1@0 { |
622 | reg = <0>; | |
623 | fsl,pinmux-ids = < | |
bc3875f1 LW |
624 | MX28_PAD_PWM0__I2C1_SCL |
625 | MX28_PAD_PWM1__I2C1_SDA | |
de7e934f | 626 | >; |
4191c340 LW |
627 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
628 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
629 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
de7e934f MR |
630 | }; |
631 | ||
17c63dd0 UKK |
632 | i2c1_pins_b: i2c1@1 { |
633 | reg = <1>; | |
634 | fsl,pinmux-ids = < | |
635 | MX28_PAD_AUART2_CTS__I2C1_SCL | |
636 | MX28_PAD_AUART2_RTS__I2C1_SDA | |
637 | >; | |
638 | fsl,drive-strength = <MXS_DRIVE_8mA>; | |
639 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
640 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
641 | }; | |
642 | ||
530f1d41 SG |
643 | saif0_pins_a: saif0@0 { |
644 | reg = <0>; | |
f14da767 | 645 | fsl,pinmux-ids = < |
bc3875f1 LW |
646 | MX28_PAD_SAIF0_MCLK__SAIF0_MCLK |
647 | MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK | |
648 | MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK | |
649 | MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 | |
f14da767 | 650 | >; |
4191c340 LW |
651 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
652 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
653 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
530f1d41 SG |
654 | }; |
655 | ||
2e1dd9fc LW |
656 | saif0_pins_b: saif0@1 { |
657 | reg = <1>; | |
658 | fsl,pinmux-ids = < | |
bc3875f1 LW |
659 | MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK |
660 | MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK | |
661 | MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 | |
2e1dd9fc | 662 | >; |
4191c340 LW |
663 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
664 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
665 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
2e1dd9fc LW |
666 | }; |
667 | ||
530f1d41 SG |
668 | saif1_pins_a: saif1@0 { |
669 | reg = <0>; | |
f14da767 | 670 | fsl,pinmux-ids = < |
bc3875f1 | 671 | MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
f14da767 | 672 | >; |
4191c340 LW |
673 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
674 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
675 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
530f1d41 | 676 | }; |
52f7176b | 677 | |
e1a4d18f SG |
678 | pwm0_pins_a: pwm0@0 { |
679 | reg = <0>; | |
680 | fsl,pinmux-ids = < | |
bc3875f1 | 681 | MX28_PAD_PWM0__PWM_0 |
e1a4d18f | 682 | >; |
4191c340 LW |
683 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
684 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
685 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
e1a4d18f SG |
686 | }; |
687 | ||
52f7176b SG |
688 | pwm2_pins_a: pwm2@0 { |
689 | reg = <0>; | |
690 | fsl,pinmux-ids = < | |
bc3875f1 | 691 | MX28_PAD_PWM2__PWM_2 |
52f7176b | 692 | >; |
4191c340 LW |
693 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
694 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
695 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
52f7176b | 696 | }; |
a915ee42 | 697 | |
2bde51cb JB |
698 | pwm3_pins_a: pwm3@0 { |
699 | reg = <0>; | |
700 | fsl,pinmux-ids = < | |
bc3875f1 | 701 | MX28_PAD_PWM3__PWM_3 |
2bde51cb | 702 | >; |
4191c340 LW |
703 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
704 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
705 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
2bde51cb JB |
706 | }; |
707 | ||
d248620c MR |
708 | pwm3_pins_b: pwm3@1 { |
709 | reg = <1>; | |
710 | fsl,pinmux-ids = < | |
bc3875f1 | 711 | MX28_PAD_SAIF0_MCLK__PWM_3 |
d248620c | 712 | >; |
4191c340 LW |
713 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
714 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
715 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
d248620c MR |
716 | }; |
717 | ||
2f44211f MR |
718 | pwm4_pins_a: pwm4@0 { |
719 | reg = <0>; | |
720 | fsl,pinmux-ids = < | |
bc3875f1 | 721 | MX28_PAD_PWM4__PWM_4 |
2f44211f | 722 | >; |
4191c340 LW |
723 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
724 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
725 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
2f44211f MR |
726 | }; |
727 | ||
a915ee42 SG |
728 | lcdif_24bit_pins_a: lcdif-24bit@0 { |
729 | reg = <0>; | |
730 | fsl,pinmux-ids = < | |
bc3875f1 LW |
731 | MX28_PAD_LCD_D00__LCD_D0 |
732 | MX28_PAD_LCD_D01__LCD_D1 | |
733 | MX28_PAD_LCD_D02__LCD_D2 | |
734 | MX28_PAD_LCD_D03__LCD_D3 | |
735 | MX28_PAD_LCD_D04__LCD_D4 | |
736 | MX28_PAD_LCD_D05__LCD_D5 | |
737 | MX28_PAD_LCD_D06__LCD_D6 | |
738 | MX28_PAD_LCD_D07__LCD_D7 | |
739 | MX28_PAD_LCD_D08__LCD_D8 | |
740 | MX28_PAD_LCD_D09__LCD_D9 | |
741 | MX28_PAD_LCD_D10__LCD_D10 | |
742 | MX28_PAD_LCD_D11__LCD_D11 | |
743 | MX28_PAD_LCD_D12__LCD_D12 | |
744 | MX28_PAD_LCD_D13__LCD_D13 | |
745 | MX28_PAD_LCD_D14__LCD_D14 | |
746 | MX28_PAD_LCD_D15__LCD_D15 | |
747 | MX28_PAD_LCD_D16__LCD_D16 | |
748 | MX28_PAD_LCD_D17__LCD_D17 | |
749 | MX28_PAD_LCD_D18__LCD_D18 | |
750 | MX28_PAD_LCD_D19__LCD_D19 | |
751 | MX28_PAD_LCD_D20__LCD_D20 | |
752 | MX28_PAD_LCD_D21__LCD_D21 | |
753 | MX28_PAD_LCD_D22__LCD_D22 | |
754 | MX28_PAD_LCD_D23__LCD_D23 | |
a915ee42 | 755 | >; |
4191c340 LW |
756 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
757 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
758 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
a915ee42 | 759 | }; |
6ca44acf | 760 | |
ec985eb2 DC |
761 | lcdif_18bit_pins_a: lcdif-18bit@0 { |
762 | reg = <0>; | |
763 | fsl,pinmux-ids = < | |
764 | MX28_PAD_LCD_D00__LCD_D0 | |
765 | MX28_PAD_LCD_D01__LCD_D1 | |
766 | MX28_PAD_LCD_D02__LCD_D2 | |
767 | MX28_PAD_LCD_D03__LCD_D3 | |
768 | MX28_PAD_LCD_D04__LCD_D4 | |
769 | MX28_PAD_LCD_D05__LCD_D5 | |
770 | MX28_PAD_LCD_D06__LCD_D6 | |
771 | MX28_PAD_LCD_D07__LCD_D7 | |
772 | MX28_PAD_LCD_D08__LCD_D8 | |
773 | MX28_PAD_LCD_D09__LCD_D9 | |
774 | MX28_PAD_LCD_D10__LCD_D10 | |
775 | MX28_PAD_LCD_D11__LCD_D11 | |
776 | MX28_PAD_LCD_D12__LCD_D12 | |
777 | MX28_PAD_LCD_D13__LCD_D13 | |
778 | MX28_PAD_LCD_D14__LCD_D14 | |
779 | MX28_PAD_LCD_D15__LCD_D15 | |
780 | MX28_PAD_LCD_D16__LCD_D16 | |
781 | MX28_PAD_LCD_D17__LCD_D17 | |
782 | >; | |
783 | fsl,drive-strength = <MXS_DRIVE_4mA>; | |
784 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
785 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
786 | }; | |
787 | ||
4ced2a40 GGM |
788 | lcdif_16bit_pins_a: lcdif-16bit@0 { |
789 | reg = <0>; | |
790 | fsl,pinmux-ids = < | |
bc3875f1 LW |
791 | MX28_PAD_LCD_D00__LCD_D0 |
792 | MX28_PAD_LCD_D01__LCD_D1 | |
793 | MX28_PAD_LCD_D02__LCD_D2 | |
794 | MX28_PAD_LCD_D03__LCD_D3 | |
795 | MX28_PAD_LCD_D04__LCD_D4 | |
796 | MX28_PAD_LCD_D05__LCD_D5 | |
797 | MX28_PAD_LCD_D06__LCD_D6 | |
798 | MX28_PAD_LCD_D07__LCD_D7 | |
799 | MX28_PAD_LCD_D08__LCD_D8 | |
800 | MX28_PAD_LCD_D09__LCD_D9 | |
801 | MX28_PAD_LCD_D10__LCD_D10 | |
802 | MX28_PAD_LCD_D11__LCD_D11 | |
803 | MX28_PAD_LCD_D12__LCD_D12 | |
804 | MX28_PAD_LCD_D13__LCD_D13 | |
805 | MX28_PAD_LCD_D14__LCD_D14 | |
806 | MX28_PAD_LCD_D15__LCD_D15 | |
4ced2a40 | 807 | >; |
4191c340 LW |
808 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
809 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
810 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
4ced2a40 GGM |
811 | }; |
812 | ||
23ad6f65 LW |
813 | lcdif_sync_pins_a: lcdif-sync@0 { |
814 | reg = <0>; | |
815 | fsl,pinmux-ids = < | |
bc3875f1 LW |
816 | MX28_PAD_LCD_RS__LCD_DOTCLK |
817 | MX28_PAD_LCD_CS__LCD_ENABLE | |
818 | MX28_PAD_LCD_RD_E__LCD_VSYNC | |
819 | MX28_PAD_LCD_WR_RWN__LCD_HSYNC | |
23ad6f65 | 820 | >; |
4191c340 LW |
821 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
822 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
823 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
23ad6f65 LW |
824 | }; |
825 | ||
6ca44acf SG |
826 | can0_pins_a: can0@0 { |
827 | reg = <0>; | |
828 | fsl,pinmux-ids = < | |
bc3875f1 LW |
829 | MX28_PAD_GPMI_RDY2__CAN0_TX |
830 | MX28_PAD_GPMI_RDY3__CAN0_RX | |
6ca44acf | 831 | >; |
4191c340 LW |
832 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
833 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
834 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
6ca44acf SG |
835 | }; |
836 | ||
837 | can1_pins_a: can1@0 { | |
838 | reg = <0>; | |
839 | fsl,pinmux-ids = < | |
bc3875f1 LW |
840 | MX28_PAD_GPMI_CE2N__CAN1_TX |
841 | MX28_PAD_GPMI_CE3N__CAN1_RX | |
6ca44acf | 842 | >; |
4191c340 LW |
843 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
844 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
845 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
6ca44acf | 846 | }; |
7f122213 MV |
847 | |
848 | spi2_pins_a: spi2@0 { | |
849 | reg = <0>; | |
850 | fsl,pinmux-ids = < | |
bc3875f1 LW |
851 | MX28_PAD_SSP2_SCK__SSP2_SCK |
852 | MX28_PAD_SSP2_MOSI__SSP2_CMD | |
853 | MX28_PAD_SSP2_MISO__SSP2_D0 | |
854 | MX28_PAD_SSP2_SS0__SSP2_D3 | |
7f122213 | 855 | >; |
4191c340 LW |
856 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
857 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
858 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
7f122213 | 859 | }; |
bb2f1261 | 860 | |
3314d2be LW |
861 | spi3_pins_a: spi3@0 { |
862 | reg = <0>; | |
863 | fsl,pinmux-ids = < | |
bc3875f1 LW |
864 | MX28_PAD_AUART2_RX__SSP3_D4 |
865 | MX28_PAD_AUART2_TX__SSP3_D5 | |
866 | MX28_PAD_SSP3_SCK__SSP3_SCK | |
867 | MX28_PAD_SSP3_MOSI__SSP3_CMD | |
868 | MX28_PAD_SSP3_MISO__SSP3_D0 | |
869 | MX28_PAD_SSP3_SS0__SSP3_D3 | |
3314d2be | 870 | >; |
4191c340 LW |
871 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
872 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
873 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
3314d2be LW |
874 | }; |
875 | ||
8f0b07a4 UKK |
876 | spi3_pins_b: spi3@1 { |
877 | reg = <1>; | |
878 | fsl,pinmux-ids = < | |
879 | MX28_PAD_SSP3_SCK__SSP3_SCK | |
880 | MX28_PAD_SSP3_MOSI__SSP3_CMD | |
881 | MX28_PAD_SSP3_MISO__SSP3_D0 | |
882 | MX28_PAD_SSP3_SS0__SSP3_D3 | |
883 | >; | |
884 | fsl,drive-strength = <MXS_DRIVE_8mA>; | |
885 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
886 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
887 | }; | |
888 | ||
c8e42bc9 | 889 | usb0_pins_a: usb0@0 { |
bb2f1261 MV |
890 | reg = <0>; |
891 | fsl,pinmux-ids = < | |
bc3875f1 | 892 | MX28_PAD_SSP2_SS2__USB0_OVERCURRENT |
bb2f1261 | 893 | >; |
4191c340 LW |
894 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
895 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
896 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
bb2f1261 MV |
897 | }; |
898 | ||
c8e42bc9 | 899 | usb0_pins_b: usb0@1 { |
bb2f1261 MV |
900 | reg = <1>; |
901 | fsl,pinmux-ids = < | |
bc3875f1 | 902 | MX28_PAD_AUART1_CTS__USB0_OVERCURRENT |
bb2f1261 | 903 | >; |
4191c340 LW |
904 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
905 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
906 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
bb2f1261 MV |
907 | }; |
908 | ||
c8e42bc9 | 909 | usb1_pins_a: usb1@0 { |
bb2f1261 MV |
910 | reg = <0>; |
911 | fsl,pinmux-ids = < | |
bc3875f1 | 912 | MX28_PAD_SSP2_SS1__USB1_OVERCURRENT |
bb2f1261 | 913 | >; |
4191c340 LW |
914 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
915 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
916 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
bb2f1261 | 917 | }; |
69c02f95 FE |
918 | |
919 | usb0_id_pins_a: usb0id@0 { | |
920 | reg = <0>; | |
921 | fsl,pinmux-ids = < | |
e96e1782 | 922 | MX28_PAD_AUART1_RTS__USB0_ID |
bb2f1261 | 923 | >; |
e96e1782 LW |
924 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
925 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
926 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
bb2f1261 | 927 | }; |
bb89b8d2 DC |
928 | |
929 | usb0_id_pins_b: usb0id1@0 { | |
930 | reg = <0>; | |
931 | fsl,pinmux-ids = < | |
932 | MX28_PAD_PWM2__USB0_ID | |
933 | >; | |
934 | fsl,drive-strength = <MXS_DRIVE_12mA>; | |
935 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
936 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
937 | }; | |
938 | ||
bc3a59c1 DA |
939 | }; |
940 | ||
296f8cd3 | 941 | digctl: digctl@8001c000 { |
115581cf | 942 | compatible = "fsl,imx28-digctl", "fsl,imx23-digctl"; |
0f06cde7 | 943 | reg = <0x8001c000 0x2000>; |
bc3a59c1 DA |
944 | interrupts = <89>; |
945 | status = "disabled"; | |
946 | }; | |
947 | ||
296f8cd3 | 948 | etm: etm@80022000 { |
0f06cde7 | 949 | reg = <0x80022000 0x2000>; |
bc3a59c1 DA |
950 | status = "disabled"; |
951 | }; | |
952 | ||
f30fb03d | 953 | dma_apbx: dma-apbx@80024000 { |
84f3570a | 954 | compatible = "fsl,imx28-dma-apbx"; |
0f06cde7 | 955 | reg = <0x80024000 0x2000>; |
f30fb03d SG |
956 | interrupts = <78 79 66 0 |
957 | 80 81 68 69 | |
958 | 70 71 72 73 | |
959 | 74 75 76 77>; | |
4ada77e3 | 960 | interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty", |
f30fb03d SG |
961 | "saif0", "saif1", "i2c0", "i2c1", |
962 | "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", | |
963 | "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; | |
964 | #dma-cells = <1>; | |
965 | dma-channels = <16>; | |
b598b9f3 | 966 | clocks = <&clks 26>; |
bc3a59c1 DA |
967 | }; |
968 | ||
296f8cd3 | 969 | dcp: dcp@80028000 { |
7d56a28f | 970 | compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; |
0f06cde7 | 971 | reg = <0x80028000 0x2000>; |
bc3a59c1 | 972 | interrupts = <52 53 54>; |
7d56a28f | 973 | status = "okay"; |
bc3a59c1 DA |
974 | }; |
975 | ||
296f8cd3 | 976 | pxp: pxp@8002a000 { |
0f06cde7 | 977 | reg = <0x8002a000 0x2000>; |
bc3a59c1 DA |
978 | interrupts = <39>; |
979 | status = "disabled"; | |
980 | }; | |
981 | ||
296f8cd3 | 982 | ocotp: ocotp@8002c000 { |
a7be1e68 SW |
983 | compatible = "fsl,imx28-ocotp", "fsl,ocotp"; |
984 | #address-cells = <1>; | |
985 | #size-cells = <1>; | |
0f06cde7 | 986 | reg = <0x8002c000 0x2000>; |
a7be1e68 | 987 | clocks = <&clks 25>; |
bc3a59c1 DA |
988 | }; |
989 | ||
990 | axi-ahb@8002e000 { | |
0f06cde7 | 991 | reg = <0x8002e000 0x2000>; |
bc3a59c1 DA |
992 | status = "disabled"; |
993 | }; | |
994 | ||
296f8cd3 | 995 | lcdif: lcdif@80030000 { |
a915ee42 | 996 | compatible = "fsl,imx28-lcdif"; |
0f06cde7 | 997 | reg = <0x80030000 0x2000>; |
7f2b9288 | 998 | interrupts = <38>; |
b598b9f3 | 999 | clocks = <&clks 55>; |
f30fb03d SG |
1000 | dmas = <&dma_apbh 13>; |
1001 | dma-names = "rx"; | |
bc3a59c1 DA |
1002 | status = "disabled"; |
1003 | }; | |
1004 | ||
1005 | can0: can@80032000 { | |
6ca44acf | 1006 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; |
0f06cde7 | 1007 | reg = <0x80032000 0x2000>; |
bc3a59c1 | 1008 | interrupts = <8>; |
b598b9f3 SG |
1009 | clocks = <&clks 58>, <&clks 58>; |
1010 | clock-names = "ipg", "per"; | |
bc3a59c1 DA |
1011 | status = "disabled"; |
1012 | }; | |
1013 | ||
1014 | can1: can@80034000 { | |
6ca44acf | 1015 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; |
0f06cde7 | 1016 | reg = <0x80034000 0x2000>; |
bc3a59c1 | 1017 | interrupts = <9>; |
b598b9f3 SG |
1018 | clocks = <&clks 59>, <&clks 59>; |
1019 | clock-names = "ipg", "per"; | |
bc3a59c1 DA |
1020 | status = "disabled"; |
1021 | }; | |
1022 | ||
296f8cd3 | 1023 | simdbg: simdbg@8003c000 { |
0f06cde7 | 1024 | reg = <0x8003c000 0x200>; |
bc3a59c1 DA |
1025 | status = "disabled"; |
1026 | }; | |
1027 | ||
296f8cd3 | 1028 | simgpmisel: simgpmisel@8003c200 { |
0f06cde7 | 1029 | reg = <0x8003c200 0x100>; |
bc3a59c1 DA |
1030 | status = "disabled"; |
1031 | }; | |
1032 | ||
296f8cd3 | 1033 | simsspsel: simsspsel@8003c300 { |
0f06cde7 | 1034 | reg = <0x8003c300 0x100>; |
bc3a59c1 DA |
1035 | status = "disabled"; |
1036 | }; | |
1037 | ||
296f8cd3 | 1038 | simmemsel: simmemsel@8003c400 { |
0f06cde7 | 1039 | reg = <0x8003c400 0x100>; |
bc3a59c1 DA |
1040 | status = "disabled"; |
1041 | }; | |
1042 | ||
296f8cd3 | 1043 | gpiomon: gpiomon@8003c500 { |
0f06cde7 | 1044 | reg = <0x8003c500 0x100>; |
bc3a59c1 DA |
1045 | status = "disabled"; |
1046 | }; | |
1047 | ||
296f8cd3 | 1048 | simenet: simenet@8003c700 { |
0f06cde7 | 1049 | reg = <0x8003c700 0x100>; |
bc3a59c1 DA |
1050 | status = "disabled"; |
1051 | }; | |
1052 | ||
296f8cd3 | 1053 | armjtag: armjtag@8003c800 { |
0f06cde7 | 1054 | reg = <0x8003c800 0x100>; |
bc3a59c1 DA |
1055 | status = "disabled"; |
1056 | }; | |
07a3ce7f | 1057 | }; |
bc3a59c1 DA |
1058 | |
1059 | apbx@80040000 { | |
1060 | compatible = "simple-bus"; | |
1061 | #address-cells = <1>; | |
1062 | #size-cells = <1>; | |
1063 | reg = <0x80040000 0x40000>; | |
1064 | ranges; | |
1065 | ||
b598b9f3 | 1066 | clks: clkctrl@80040000 { |
8f7cf881 | 1067 | compatible = "fsl,imx28-clkctrl", "fsl,clkctrl"; |
0f06cde7 | 1068 | reg = <0x80040000 0x2000>; |
b598b9f3 | 1069 | #clock-cells = <1>; |
bc3a59c1 DA |
1070 | }; |
1071 | ||
1072 | saif0: saif@80042000 { | |
530f1d41 | 1073 | compatible = "fsl,imx28-saif"; |
0f06cde7 | 1074 | reg = <0x80042000 0x2000>; |
7f2b9288 | 1075 | interrupts = <59>; |
66acaf3f | 1076 | #clock-cells = <0>; |
b598b9f3 | 1077 | clocks = <&clks 53>; |
f30fb03d SG |
1078 | dmas = <&dma_apbx 4>; |
1079 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
1080 | status = "disabled"; |
1081 | }; | |
1082 | ||
296f8cd3 | 1083 | power: power@80044000 { |
0f06cde7 | 1084 | reg = <0x80044000 0x2000>; |
bc3a59c1 DA |
1085 | status = "disabled"; |
1086 | }; | |
1087 | ||
1088 | saif1: saif@80046000 { | |
530f1d41 | 1089 | compatible = "fsl,imx28-saif"; |
0f06cde7 | 1090 | reg = <0x80046000 0x2000>; |
7f2b9288 | 1091 | interrupts = <58>; |
b598b9f3 | 1092 | clocks = <&clks 54>; |
f30fb03d SG |
1093 | dmas = <&dma_apbx 5>; |
1094 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
1095 | status = "disabled"; |
1096 | }; | |
1097 | ||
296f8cd3 | 1098 | lradc: lradc@80050000 { |
aef35104 | 1099 | compatible = "fsl,imx28-lradc"; |
0f06cde7 | 1100 | reg = <0x80050000 0x2000>; |
aef35104 MV |
1101 | interrupts = <10 14 15 16 17 18 19 |
1102 | 20 21 22 23 24 25>; | |
bc3a59c1 | 1103 | status = "disabled"; |
18da755d | 1104 | clocks = <&clks 41>; |
40dde681 | 1105 | #io-channel-cells = <1>; |
bc3a59c1 DA |
1106 | }; |
1107 | ||
296f8cd3 | 1108 | spdif: spdif@80054000 { |
0f06cde7 | 1109 | reg = <0x80054000 0x2000>; |
7f2b9288 | 1110 | interrupts = <45>; |
f30fb03d SG |
1111 | dmas = <&dma_apbx 2>; |
1112 | dma-names = "tx"; | |
bc3a59c1 DA |
1113 | status = "disabled"; |
1114 | }; | |
1115 | ||
296f8cd3 | 1116 | mxs_rtc: rtc@80056000 { |
f98c990c | 1117 | compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; |
0f06cde7 | 1118 | reg = <0x80056000 0x2000>; |
f98c990c | 1119 | interrupts = <29>; |
bc3a59c1 DA |
1120 | }; |
1121 | ||
1122 | i2c0: i2c@80058000 { | |
2a96e391 SG |
1123 | #address-cells = <1>; |
1124 | #size-cells = <0>; | |
1125 | compatible = "fsl,imx28-i2c"; | |
0f06cde7 | 1126 | reg = <0x80058000 0x2000>; |
7f2b9288 | 1127 | interrupts = <111>; |
cd4f2d4a | 1128 | clock-frequency = <100000>; |
f30fb03d SG |
1129 | dmas = <&dma_apbx 6>; |
1130 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
1131 | status = "disabled"; |
1132 | }; | |
1133 | ||
1134 | i2c1: i2c@8005a000 { | |
2a96e391 SG |
1135 | #address-cells = <1>; |
1136 | #size-cells = <0>; | |
1137 | compatible = "fsl,imx28-i2c"; | |
0f06cde7 | 1138 | reg = <0x8005a000 0x2000>; |
7f2b9288 | 1139 | interrupts = <110>; |
cd4f2d4a | 1140 | clock-frequency = <100000>; |
f30fb03d SG |
1141 | dmas = <&dma_apbx 7>; |
1142 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
1143 | status = "disabled"; |
1144 | }; | |
1145 | ||
52f7176b SG |
1146 | pwm: pwm@80064000 { |
1147 | compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; | |
0f06cde7 | 1148 | reg = <0x80064000 0x2000>; |
b598b9f3 | 1149 | clocks = <&clks 44>; |
52f7176b SG |
1150 | #pwm-cells = <2>; |
1151 | fsl,pwm-number = <8>; | |
bc3a59c1 DA |
1152 | status = "disabled"; |
1153 | }; | |
1154 | ||
296f8cd3 | 1155 | timer: timrot@80068000 { |
eeca6e60 | 1156 | compatible = "fsl,imx28-timrot", "fsl,timrot"; |
0f06cde7 | 1157 | reg = <0x80068000 0x2000>; |
eeca6e60 | 1158 | interrupts = <48 49 50 51>; |
2efb9504 | 1159 | clocks = <&clks 26>; |
bc3a59c1 DA |
1160 | }; |
1161 | ||
1162 | auart0: serial@8006a000 { | |
80d969e4 | 1163 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 | 1164 | reg = <0x8006a000 0x2000>; |
7f2b9288 | 1165 | interrupts = <112>; |
f30fb03d SG |
1166 | dmas = <&dma_apbx 8>, <&dma_apbx 9>; |
1167 | dma-names = "rx", "tx"; | |
b598b9f3 | 1168 | clocks = <&clks 45>; |
bc3a59c1 DA |
1169 | status = "disabled"; |
1170 | }; | |
1171 | ||
1172 | auart1: serial@8006c000 { | |
80d969e4 | 1173 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 | 1174 | reg = <0x8006c000 0x2000>; |
7f2b9288 | 1175 | interrupts = <113>; |
f30fb03d SG |
1176 | dmas = <&dma_apbx 10>, <&dma_apbx 11>; |
1177 | dma-names = "rx", "tx"; | |
b598b9f3 | 1178 | clocks = <&clks 45>; |
bc3a59c1 DA |
1179 | status = "disabled"; |
1180 | }; | |
1181 | ||
1182 | auart2: serial@8006e000 { | |
80d969e4 | 1183 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 | 1184 | reg = <0x8006e000 0x2000>; |
7f2b9288 | 1185 | interrupts = <114>; |
f30fb03d SG |
1186 | dmas = <&dma_apbx 12>, <&dma_apbx 13>; |
1187 | dma-names = "rx", "tx"; | |
b598b9f3 | 1188 | clocks = <&clks 45>; |
bc3a59c1 DA |
1189 | status = "disabled"; |
1190 | }; | |
1191 | ||
1192 | auart3: serial@80070000 { | |
80d969e4 | 1193 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 | 1194 | reg = <0x80070000 0x2000>; |
7f2b9288 | 1195 | interrupts = <115>; |
f30fb03d SG |
1196 | dmas = <&dma_apbx 14>, <&dma_apbx 15>; |
1197 | dma-names = "rx", "tx"; | |
b598b9f3 | 1198 | clocks = <&clks 45>; |
bc3a59c1 DA |
1199 | status = "disabled"; |
1200 | }; | |
1201 | ||
1202 | auart4: serial@80072000 { | |
80d969e4 | 1203 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 | 1204 | reg = <0x80072000 0x2000>; |
7f2b9288 | 1205 | interrupts = <116>; |
f30fb03d SG |
1206 | dmas = <&dma_apbx 0>, <&dma_apbx 1>; |
1207 | dma-names = "rx", "tx"; | |
b598b9f3 | 1208 | clocks = <&clks 45>; |
bc3a59c1 DA |
1209 | status = "disabled"; |
1210 | }; | |
1211 | ||
1212 | duart: serial@80074000 { | |
1213 | compatible = "arm,pl011", "arm,primecell"; | |
1214 | reg = <0x80074000 0x1000>; | |
1215 | interrupts = <47>; | |
b598b9f3 SG |
1216 | clocks = <&clks 45>, <&clks 26>; |
1217 | clock-names = "uart", "apb_pclk"; | |
bc3a59c1 DA |
1218 | status = "disabled"; |
1219 | }; | |
1220 | ||
1221 | usbphy0: usbphy@8007c000 { | |
5da01270 | 1222 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; |
bc3a59c1 | 1223 | reg = <0x8007c000 0x2000>; |
b598b9f3 | 1224 | clocks = <&clks 62>; |
bc3a59c1 DA |
1225 | status = "disabled"; |
1226 | }; | |
1227 | ||
1228 | usbphy1: usbphy@8007e000 { | |
5da01270 | 1229 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; |
bc3a59c1 | 1230 | reg = <0x8007e000 0x2000>; |
b598b9f3 | 1231 | clocks = <&clks 63>; |
bc3a59c1 DA |
1232 | status = "disabled"; |
1233 | }; | |
1234 | }; | |
1235 | }; | |
1236 | ||
1237 | ahb@80080000 { | |
1238 | compatible = "simple-bus"; | |
1239 | #address-cells = <1>; | |
1240 | #size-cells = <1>; | |
1241 | reg = <0x80080000 0x80000>; | |
1242 | ranges; | |
1243 | ||
5da01270 RZ |
1244 | usb0: usb@80080000 { |
1245 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; | |
bc3a59c1 | 1246 | reg = <0x80080000 0x10000>; |
5da01270 | 1247 | interrupts = <93>; |
b598b9f3 | 1248 | clocks = <&clks 60>; |
5da01270 | 1249 | fsl,usbphy = <&usbphy0>; |
bc3a59c1 DA |
1250 | status = "disabled"; |
1251 | }; | |
1252 | ||
5da01270 RZ |
1253 | usb1: usb@80090000 { |
1254 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; | |
bc3a59c1 | 1255 | reg = <0x80090000 0x10000>; |
5da01270 | 1256 | interrupts = <92>; |
b598b9f3 | 1257 | clocks = <&clks 61>; |
5da01270 | 1258 | fsl,usbphy = <&usbphy1>; |
3ec481ed | 1259 | dr_mode = "host"; |
bc3a59c1 DA |
1260 | status = "disabled"; |
1261 | }; | |
1262 | ||
296f8cd3 | 1263 | dflpt: dflpt@800c0000 { |
bc3a59c1 DA |
1264 | reg = <0x800c0000 0x10000>; |
1265 | status = "disabled"; | |
1266 | }; | |
1267 | ||
1268 | mac0: ethernet@800f0000 { | |
1269 | compatible = "fsl,imx28-fec"; | |
1270 | reg = <0x800f0000 0x4000>; | |
1271 | interrupts = <101>; | |
f231a9fe WS |
1272 | clocks = <&clks 57>, <&clks 57>, <&clks 64>; |
1273 | clock-names = "ipg", "ahb", "enet_out"; | |
bc3a59c1 DA |
1274 | status = "disabled"; |
1275 | }; | |
1276 | ||
1277 | mac1: ethernet@800f4000 { | |
1278 | compatible = "fsl,imx28-fec"; | |
1279 | reg = <0x800f4000 0x4000>; | |
1280 | interrupts = <102>; | |
b598b9f3 SG |
1281 | clocks = <&clks 57>, <&clks 57>; |
1282 | clock-names = "ipg", "ahb"; | |
bc3a59c1 DA |
1283 | status = "disabled"; |
1284 | }; | |
1285 | ||
296f8cd3 | 1286 | etn_switch: switch@800f8000 { |
bc3a59c1 DA |
1287 | reg = <0x800f8000 0x8000>; |
1288 | status = "disabled"; | |
1289 | }; | |
bc3a59c1 | 1290 | }; |
f92dfb02 | 1291 | |
0b452ccc | 1292 | iio-hwmon { |
f92dfb02 AB |
1293 | compatible = "iio-hwmon"; |
1294 | io-channels = <&lradc 8>; | |
1295 | }; | |
bc3a59c1 | 1296 | }; |