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ARM: dts: imx27-phytec-phycore-rdk: Add pinctrl definitions for WEIM
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx28.dtsi
CommitLineData
bc3a59c1
DA		 1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
bc3875f1
LW		 12#include "skeleton.dtsi"
13#include "imx28-pinfunc.h"
bc3a59c1
DA		 14
15/ {
16 interrupt-parent = <&icoll>;
17
ce4c6f9b 18 aliases {
6bf6eb09
FE		 19 ethernet0 = &mac0;
20 ethernet1 = &mac1;
ce4c6f9b
SG		 21 gpio0 = &gpio0;
22 gpio1 = &gpio1;
23 gpio2 = &gpio2;
24 gpio3 = &gpio3;
25 gpio4 = &gpio4;
530f1d41
SG		 26 saif0 = &saif0;
27 saif1 = &saif1;
80d969e4
FE		 28 serial0 = &auart0;
29 serial1 = &auart1;
30 serial2 = &auart2;
31 serial3 = &auart3;
32 serial4 = &auart4;
6bf6eb09
FE		 33 spi0 = &ssp1;
34 spi1 = &ssp2;
ce4c6f9b
SG		 35 };
36
bc3a59c1 37 cpus {
7925e89f
LP		 38 #address-cells = <0>;
39 #size-cells = <0>;
40
41 cpu {
42 compatible = "arm,arm926ej-s";
43 device_type = "cpu";
bc3a59c1
DA		 44 };
45 };
46
47 apb@80000000 {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 reg = <0x80000000 0x80000>;
52 ranges;
53
54 apbh@80000000 {
55 compatible = "simple-bus";
56 #address-cells = <1>;
57 #size-cells = <1>;
58 reg = <0x80000000 0x3c900>;
59 ranges;
60
61 icoll: interrupt-controller@80000000 {
83a84efc 62 compatible = "fsl,imx28-icoll", "fsl,icoll";
bc3a59c1
DA		 63 interrupt-controller;
64 #interrupt-cells = <1>;
65 reg = <0x80000000 0x2000>;
66 };
67
296f8cd3 68 hsadc: hsadc@80002000 {
0f06cde7 69 reg = <0x80002000 0x2000>;
7f2b9288 70 interrupts = <13>;
f30fb03d
SG		 71 dmas = <&dma_apbh 12>;
72 dma-names = "rx";
bc3a59c1
DA		 73 status = "disabled";
74 };
75
f30fb03d 76 dma_apbh: dma-apbh@80004000 {
84f3570a 77 compatible = "fsl,imx28-dma-apbh";
0f06cde7 78 reg = <0x80004000 0x2000>;
f30fb03d
SG		 79 interrupts = <82 83 84 85
80 88 88 88 88
81 88 88 88 88
82 87 86 0 0>;
83 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
84 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
85 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
86 "hsadc", "lcdif", "empty", "empty";
87 #dma-cells = <1>;
88 dma-channels = <16>;
b598b9f3 89 clocks = <&clks 25>;
bc3a59c1
DA		 90 };
91
296f8cd3 92 perfmon: perfmon@80006000 {
0f06cde7 93 reg = <0x80006000 0x800>;
bc3a59c1
DA		 94 interrupts = <27>;
95 status = "disabled";
96 };
97
296f8cd3 98 gpmi: gpmi-nand@8000c000 {
7a8e5149
HS		 99 compatible = "fsl,imx28-gpmi-nand";
100 #address-cells = <1>;
101 #size-cells = <1>;
0f06cde7 102 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
7a8e5149 103 reg-names = "gpmi-nand", "bch";
7f2b9288
SG		 104 interrupts = <41>;
105 interrupt-names = "bch";
b598b9f3 106 clocks = <&clks 50>;
b6442559 107 clock-names = "gpmi_io";
f30fb03d
SG		 108 dmas = <&dma_apbh 4>;
109 dma-names = "rx-tx";
bc3a59c1
DA		 110 status = "disabled";
111 };
112
113 ssp0: ssp@80010000 {
41bf5706
MR		 114 #address-cells = <1>;
115 #size-cells = <0>;
0f06cde7 116 reg = <0x80010000 0x2000>;
7f2b9288 117 interrupts = <96>;
b598b9f3 118 clocks = <&clks 46>;
f30fb03d
SG		 119 dmas = <&dma_apbh 0>;
120 dma-names = "rx-tx";
bc3a59c1
DA		 121 status = "disabled";
122 };
123
124 ssp1: ssp@80012000 {
41bf5706
MR		 125 #address-cells = <1>;
126 #size-cells = <0>;
0f06cde7 127 reg = <0x80012000 0x2000>;
7f2b9288 128 interrupts = <97>;
b598b9f3 129 clocks = <&clks 47>;
f30fb03d
SG		 130 dmas = <&dma_apbh 1>;
131 dma-names = "rx-tx";
bc3a59c1
DA		 132 status = "disabled";
133 };
134
135 ssp2: ssp@80014000 {
41bf5706
MR		 136 #address-cells = <1>;
137 #size-cells = <0>;
0f06cde7 138 reg = <0x80014000 0x2000>;
7f2b9288 139 interrupts = <98>;
b598b9f3 140 clocks = <&clks 48>;
f30fb03d
SG		 141 dmas = <&dma_apbh 2>;
142 dma-names = "rx-tx";
bc3a59c1
DA		 143 status = "disabled";
144 };
145
146 ssp3: ssp@80016000 {
41bf5706
MR		 147 #address-cells = <1>;
148 #size-cells = <0>;
0f06cde7 149 reg = <0x80016000 0x2000>;
7f2b9288 150 interrupts = <99>;
b598b9f3 151 clocks = <&clks 49>;
f30fb03d
SG		 152 dmas = <&dma_apbh 3>;
153 dma-names = "rx-tx";
bc3a59c1
DA		 154 status = "disabled";
155 };
156
296f8cd3 157 pinctrl: pinctrl@80018000 {
bc3a59c1
DA		 158 #address-cells = <1>;
159 #size-cells = <0>;
ce4c6f9b 160 compatible = "fsl,imx28-pinctrl", "simple-bus";
0f06cde7 161 reg = <0x80018000 0x2000>;
bc3a59c1 162
ce4c6f9b
SG		 163 gpio0: gpio@0 {
164 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
165 interrupts = <127>;
166 gpio-controller;
167 #gpio-cells = <2>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 };
171
172 gpio1: gpio@1 {
173 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
174 interrupts = <126>;
175 gpio-controller;
176 #gpio-cells = <2>;
177 interrupt-controller;
178 #interrupt-cells = <2>;
179 };
180
181 gpio2: gpio@2 {
182 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
183 interrupts = <125>;
184 gpio-controller;
185 #gpio-cells = <2>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 };
189
190 gpio3: gpio@3 {
191 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
192 interrupts = <124>;
193 gpio-controller;
194 #gpio-cells = <2>;
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 };
198
199 gpio4: gpio@4 {
200 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
201 interrupts = <123>;
202 gpio-controller;
203 #gpio-cells = <2>;
204 interrupt-controller;
205 #interrupt-cells = <2>;
206 };
207
bc3a59c1
DA		 208 duart_pins_a: duart@0 {
209 reg = <0>;
f14da767 210 fsl,pinmux-ids = <
bc3875f1
LW		 211 MX28_PAD_PWM0__DUART_RX
212 MX28_PAD_PWM1__DUART_TX
f14da767 213 >;
4191c340
LW		 214 fsl,drive-strength = <MXS_DRIVE_4mA>;
215 fsl,voltage = <MXS_VOLTAGE_HIGH>;
216 fsl,pull-up = <MXS_PULL_DISABLE>;
bc3a59c1
DA		 217 };
218
8385e7c1
MR		 219 duart_pins_b: duart@1 {
220 reg = <1>;
f14da767 221 fsl,pinmux-ids = <
bc3875f1
LW		 222 MX28_PAD_AUART0_CTS__DUART_RX
223 MX28_PAD_AUART0_RTS__DUART_TX
f14da767 224 >;
4191c340
LW		 225 fsl,drive-strength = <MXS_DRIVE_4mA>;
226 fsl,voltage = <MXS_VOLTAGE_HIGH>;
227 fsl,pull-up = <MXS_PULL_DISABLE>;
8385e7c1
MR		 228 };
229
e1a4d18f
SG		 230 duart_4pins_a: duart-4pins@0 {
231 reg = <0>;
232 fsl,pinmux-ids = <
bc3875f1
LW		 233 MX28_PAD_AUART0_CTS__DUART_RX
234 MX28_PAD_AUART0_RTS__DUART_TX
235 MX28_PAD_AUART0_RX__DUART_CTS
236 MX28_PAD_AUART0_TX__DUART_RTS
e1a4d18f 237 >;
4191c340
LW		 238 fsl,drive-strength = <MXS_DRIVE_4mA>;
239 fsl,voltage = <MXS_VOLTAGE_HIGH>;
240 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 241 };
242
7a8e5149
HS		 243 gpmi_pins_a: gpmi-nand@0 {
244 reg = <0>;
f14da767 245 fsl,pinmux-ids = <
bc3875f1
LW		 246 MX28_PAD_GPMI_D00__GPMI_D0
247 MX28_PAD_GPMI_D01__GPMI_D1
248 MX28_PAD_GPMI_D02__GPMI_D2
249 MX28_PAD_GPMI_D03__GPMI_D3
250 MX28_PAD_GPMI_D04__GPMI_D4
251 MX28_PAD_GPMI_D05__GPMI_D5
252 MX28_PAD_GPMI_D06__GPMI_D6
253 MX28_PAD_GPMI_D07__GPMI_D7
254 MX28_PAD_GPMI_CE0N__GPMI_CE0N
255 MX28_PAD_GPMI_RDY0__GPMI_READY0
256 MX28_PAD_GPMI_RDN__GPMI_RDN
257 MX28_PAD_GPMI_WRN__GPMI_WRN
258 MX28_PAD_GPMI_ALE__GPMI_ALE
259 MX28_PAD_GPMI_CLE__GPMI_CLE
260 MX28_PAD_GPMI_RESETN__GPMI_RESETN
f14da767 261 >;
4191c340
LW		 262 fsl,drive-strength = <MXS_DRIVE_4mA>;
263 fsl,voltage = <MXS_VOLTAGE_HIGH>;
264 fsl,pull-up = <MXS_PULL_DISABLE>;
7a8e5149
HS		 265 };
266
267 gpmi_status_cfg: gpmi-status-cfg {
f14da767 268 fsl,pinmux-ids = <
bc3875f1
LW		 269 MX28_PAD_GPMI_RDN__GPMI_RDN
270 MX28_PAD_GPMI_WRN__GPMI_WRN
271 MX28_PAD_GPMI_RESETN__GPMI_RESETN
f14da767 272 >;
4191c340 273 fsl,drive-strength = <MXS_DRIVE_12mA>;
7a8e5149
HS		 274 };
275
80d969e4
FE		 276 auart0_pins_a: auart0@0 {
277 reg = <0>;
f14da767 278 fsl,pinmux-ids = <
bc3875f1
LW		 279 MX28_PAD_AUART0_RX__AUART0_RX
280 MX28_PAD_AUART0_TX__AUART0_TX
281 MX28_PAD_AUART0_CTS__AUART0_CTS
282 MX28_PAD_AUART0_RTS__AUART0_RTS
f14da767 283 >;
4191c340
LW		 284 fsl,drive-strength = <MXS_DRIVE_4mA>;
285 fsl,voltage = <MXS_VOLTAGE_HIGH>;
286 fsl,pull-up = <MXS_PULL_DISABLE>;
8fa62e11
MV		 287 };
288
289 auart0_2pins_a: auart0-2pins@0 {
290 reg = <0>;
291 fsl,pinmux-ids = <
bc3875f1
LW		 292 MX28_PAD_AUART0_RX__AUART0_RX
293 MX28_PAD_AUART0_TX__AUART0_TX
8fa62e11 294 >;
4191c340
LW		 295 fsl,drive-strength = <MXS_DRIVE_4mA>;
296 fsl,voltage = <MXS_VOLTAGE_HIGH>;
297 fsl,pull-up = <MXS_PULL_DISABLE>;
80d969e4
FE		 298 };
299
e1a4d18f
SG		 300 auart1_pins_a: auart1@0 {
301 reg = <0>;
302 fsl,pinmux-ids = <
bc3875f1
LW		 303 MX28_PAD_AUART1_RX__AUART1_RX
304 MX28_PAD_AUART1_TX__AUART1_TX
305 MX28_PAD_AUART1_CTS__AUART1_CTS
306 MX28_PAD_AUART1_RTS__AUART1_RTS
e1a4d18f 307 >;
4191c340
LW		 308 fsl,drive-strength = <MXS_DRIVE_4mA>;
309 fsl,voltage = <MXS_VOLTAGE_HIGH>;
310 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 311 };
312
3143bbb4
SG		 313 auart1_2pins_a: auart1-2pins@0 {
314 reg = <0>;
315 fsl,pinmux-ids = <
bc3875f1
LW		 316 MX28_PAD_AUART1_RX__AUART1_RX
317 MX28_PAD_AUART1_TX__AUART1_TX
3143bbb4 318 >;
4191c340
LW		 319 fsl,drive-strength = <MXS_DRIVE_4mA>;
320 fsl,voltage = <MXS_VOLTAGE_HIGH>;
321 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 322 };
323
324 auart2_2pins_a: auart2-2pins@0 {
325 reg = <0>;
326 fsl,pinmux-ids = <
bc3875f1
LW		 327 MX28_PAD_SSP2_SCK__AUART2_RX
328 MX28_PAD_SSP2_MOSI__AUART2_TX
3143bbb4 329 >;
4191c340
LW		 330 fsl,drive-strength = <MXS_DRIVE_4mA>;
331 fsl,voltage = <MXS_VOLTAGE_HIGH>;
332 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 333 };
334
f8040cf5
EB		 335 auart2_2pins_b: auart2-2pins@1 {
336 reg = <1>;
337 fsl,pinmux-ids = <
bc3875f1
LW		 338 MX28_PAD_AUART2_RX__AUART2_RX
339 MX28_PAD_AUART2_TX__AUART2_TX
f8040cf5 340 >;
4191c340
LW		 341 fsl,drive-strength = <MXS_DRIVE_4mA>;
342 fsl,voltage = <MXS_VOLTAGE_HIGH>;
343 fsl,pull-up = <MXS_PULL_DISABLE>;
f8040cf5
EB		 344 };
345
cd0214c3
AM		 346 auart2_pins_a: auart2-pins@0 {
347 reg = <0>;
348 fsl,pinmux-ids = <
349 MX28_PAD_AUART2_RX__AUART2_RX
350 MX28_PAD_AUART2_TX__AUART2_TX
351 MX28_PAD_AUART2_CTS__AUART2_CTS
352 MX28_PAD_AUART2_RTS__AUART2_RTS
353 >;
354 fsl,drive-strength = <MXS_DRIVE_4mA>;
355 fsl,voltage = <MXS_VOLTAGE_HIGH>;
356 fsl,pull-up = <MXS_PULL_DISABLE>;
357 };
358
80d969e4
FE		 359 auart3_pins_a: auart3@0 {
360 reg = <0>;
f14da767 361 fsl,pinmux-ids = <
bc3875f1
LW		 362 MX28_PAD_AUART3_RX__AUART3_RX
363 MX28_PAD_AUART3_TX__AUART3_TX
364 MX28_PAD_AUART3_CTS__AUART3_CTS
365 MX28_PAD_AUART3_RTS__AUART3_RTS
f14da767 366 >;
4191c340
LW		 367 fsl,drive-strength = <MXS_DRIVE_4mA>;
368 fsl,voltage = <MXS_VOLTAGE_HIGH>;
369 fsl,pull-up = <MXS_PULL_DISABLE>;
80d969e4
FE		 370 };
371
3143bbb4
SG		 372 auart3_2pins_a: auart3-2pins@0 {
373 reg = <0>;
374 fsl,pinmux-ids = <
bc3875f1
LW		 375 MX28_PAD_SSP2_MISO__AUART3_RX
376 MX28_PAD_SSP2_SS0__AUART3_TX
3143bbb4 377 >;
4191c340
LW		 378 fsl,drive-strength = <MXS_DRIVE_4mA>;
379 fsl,voltage = <MXS_VOLTAGE_HIGH>;
380 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 381 };
382
4812e746
EB		 383 auart3_2pins_b: auart3-2pins@1 {
384 reg = <1>;
385 fsl,pinmux-ids = <
bc3875f1
LW		 386 MX28_PAD_AUART3_RX__AUART3_RX
387 MX28_PAD_AUART3_TX__AUART3_TX
4812e746 388 >;
4191c340
LW		 389 fsl,drive-strength = <MXS_DRIVE_4mA>;
390 fsl,voltage = <MXS_VOLTAGE_HIGH>;
391 fsl,pull-up = <MXS_PULL_DISABLE>;
4812e746
EB		 392 };
393
33678d12
EB		 394 auart4_2pins_a: auart4@0 {
395 reg = <0>;
396 fsl,pinmux-ids = <
bc3875f1
LW		 397 MX28_PAD_SSP3_SCK__AUART4_TX
398 MX28_PAD_SSP3_MOSI__AUART4_RX
33678d12 399 >;
4191c340
LW		 400 fsl,drive-strength = <MXS_DRIVE_4mA>;
401 fsl,voltage = <MXS_VOLTAGE_HIGH>;
402 fsl,pull-up = <MXS_PULL_DISABLE>;
33678d12
EB		 403 };
404
bc3a59c1
DA		 405 mac0_pins_a: mac0@0 {
406 reg = <0>;
f14da767 407 fsl,pinmux-ids = <
bc3875f1
LW		 408 MX28_PAD_ENET0_MDC__ENET0_MDC
409 MX28_PAD_ENET0_MDIO__ENET0_MDIO
410 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
411 MX28_PAD_ENET0_RXD0__ENET0_RXD0
412 MX28_PAD_ENET0_RXD1__ENET0_RXD1
413 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
414 MX28_PAD_ENET0_TXD0__ENET0_TXD0
415 MX28_PAD_ENET0_TXD1__ENET0_TXD1
416 MX28_PAD_ENET_CLK__CLKCTRL_ENET
f14da767 417 >;
4191c340
LW		 418 fsl,drive-strength = <MXS_DRIVE_8mA>;
419 fsl,voltage = <MXS_VOLTAGE_HIGH>;
420 fsl,pull-up = <MXS_PULL_ENABLE>;
bc3a59c1
DA		 421 };
422
423 mac1_pins_a: mac1@0 {
424 reg = <0>;
f14da767 425 fsl,pinmux-ids = <
bc3875f1
LW		 426 MX28_PAD_ENET0_CRS__ENET1_RX_EN
427 MX28_PAD_ENET0_RXD2__ENET1_RXD0
428 MX28_PAD_ENET0_RXD3__ENET1_RXD1
429 MX28_PAD_ENET0_COL__ENET1_TX_EN
430 MX28_PAD_ENET0_TXD2__ENET1_TXD0
431 MX28_PAD_ENET0_TXD3__ENET1_TXD1
f14da767 432 >;
4191c340
LW		 433 fsl,drive-strength = <MXS_DRIVE_8mA>;
434 fsl,voltage = <MXS_VOLTAGE_HIGH>;
435 fsl,pull-up = <MXS_PULL_ENABLE>;
bc3a59c1 436 };
35d23047
SG		 437
438 mmc0_8bit_pins_a: mmc0-8bit@0 {
439 reg = <0>;
f14da767 440 fsl,pinmux-ids = <
bc3875f1
LW		 441 MX28_PAD_SSP0_DATA0__SSP0_D0
442 MX28_PAD_SSP0_DATA1__SSP0_D1
443 MX28_PAD_SSP0_DATA2__SSP0_D2
444 MX28_PAD_SSP0_DATA3__SSP0_D3
445 MX28_PAD_SSP0_DATA4__SSP0_D4
446 MX28_PAD_SSP0_DATA5__SSP0_D5
447 MX28_PAD_SSP0_DATA6__SSP0_D6
448 MX28_PAD_SSP0_DATA7__SSP0_D7
449 MX28_PAD_SSP0_CMD__SSP0_CMD
450 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
451 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 452 >;
4191c340
LW		 453 fsl,drive-strength = <MXS_DRIVE_8mA>;
454 fsl,voltage = <MXS_VOLTAGE_HIGH>;
455 fsl,pull-up = <MXS_PULL_ENABLE>;
35d23047
SG		 456 };
457
8385e7c1
MR		 458 mmc0_4bit_pins_a: mmc0-4bit@0 {
459 reg = <0>;
f14da767 460 fsl,pinmux-ids = <
bc3875f1
LW		 461 MX28_PAD_SSP0_DATA0__SSP0_D0
462 MX28_PAD_SSP0_DATA1__SSP0_D1
463 MX28_PAD_SSP0_DATA2__SSP0_D2
464 MX28_PAD_SSP0_DATA3__SSP0_D3
465 MX28_PAD_SSP0_CMD__SSP0_CMD
466 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
467 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 468 >;
4191c340
LW		 469 fsl,drive-strength = <MXS_DRIVE_8mA>;
470 fsl,voltage = <MXS_VOLTAGE_HIGH>;
471 fsl,pull-up = <MXS_PULL_ENABLE>;
8385e7c1
MR		 472 };
473
35d23047 474 mmc0_cd_cfg: mmc0-cd-cfg {
f14da767 475 fsl,pinmux-ids = <
bc3875f1 476 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
f14da767 477 >;
4191c340 478 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047
SG		 479 };
480
481 mmc0_sck_cfg: mmc0-sck-cfg {
f14da767 482 fsl,pinmux-ids = <
bc3875f1 483 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 484 >;
4191c340
LW		 485 fsl,drive-strength = <MXS_DRIVE_12mA>;
486 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047 487 };
2a96e391 488
5550e8e9
MV		 489 mmc2_4bit_pins_a: mmc2-4bit@0 {
490 reg = <0>;
491 fsl,pinmux-ids = <
492 MX28_PAD_SSP0_DATA4__SSP2_D0
493 MX28_PAD_SSP1_SCK__SSP2_D1
494 MX28_PAD_SSP1_CMD__SSP2_D2
495 MX28_PAD_SSP0_DATA5__SSP2_D3
496 MX28_PAD_SSP0_DATA6__SSP2_CMD
497 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
498 MX28_PAD_SSP0_DATA7__SSP2_SCK
499 >;
500 fsl,drive-strength = <MXS_DRIVE_8mA>;
501 fsl,voltage = <MXS_VOLTAGE_HIGH>;
502 fsl,pull-up = <MXS_PULL_ENABLE>;
503 };
504
505 mmc2_cd_cfg: mmc2-cd-cfg {
506 fsl,pinmux-ids = <
507 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
508 >;
509 fsl,pull-up = <MXS_PULL_DISABLE>;
510 };
511
512 mmc2_sck_cfg: mmc2-sck-cfg {
513 fsl,pinmux-ids = <
514 MX28_PAD_SSP0_DATA7__SSP2_SCK
515 >;
516 fsl,drive-strength = <MXS_DRIVE_12mA>;
517 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047 518 };
2a96e391
SG		 519
520 i2c0_pins_a: i2c0@0 {
521 reg = <0>;
f14da767 522 fsl,pinmux-ids = <
bc3875f1
LW		 523 MX28_PAD_I2C0_SCL__I2C0_SCL
524 MX28_PAD_I2C0_SDA__I2C0_SDA
f14da767 525 >;
4191c340
LW		 526 fsl,drive-strength = <MXS_DRIVE_8mA>;
527 fsl,voltage = <MXS_VOLTAGE_HIGH>;
528 fsl,pull-up = <MXS_PULL_ENABLE>;
2a96e391 529 };
530f1d41 530
5c697ea2
MR		 531 i2c0_pins_b: i2c0@1 {
532 reg = <1>;
533 fsl,pinmux-ids = <
bc3875f1
LW		 534 MX28_PAD_AUART0_RX__I2C0_SCL
535 MX28_PAD_AUART0_TX__I2C0_SDA
5c697ea2 536 >;
4191c340
LW		 537 fsl,drive-strength = <MXS_DRIVE_8mA>;
538 fsl,voltage = <MXS_VOLTAGE_HIGH>;
539 fsl,pull-up = <MXS_PULL_ENABLE>;
5c697ea2
MR		 540 };
541
de7e934f
MR		 542 i2c1_pins_a: i2c1@0 {
543 reg = <0>;
544 fsl,pinmux-ids = <
bc3875f1
LW		 545 MX28_PAD_PWM0__I2C1_SCL
546 MX28_PAD_PWM1__I2C1_SDA
de7e934f 547 >;
4191c340
LW		 548 fsl,drive-strength = <MXS_DRIVE_8mA>;
549 fsl,voltage = <MXS_VOLTAGE_HIGH>;
550 fsl,pull-up = <MXS_PULL_ENABLE>;
de7e934f
MR		 551 };
552
530f1d41
SG		 553 saif0_pins_a: saif0@0 {
554 reg = <0>;
f14da767 555 fsl,pinmux-ids = <
bc3875f1
LW		 556 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
557 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
558 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
559 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
f14da767 560 >;
4191c340
LW		 561 fsl,drive-strength = <MXS_DRIVE_12mA>;
562 fsl,voltage = <MXS_VOLTAGE_HIGH>;
563 fsl,pull-up = <MXS_PULL_ENABLE>;
530f1d41
SG		 564 };
565
2e1dd9fc
LW		 566 saif0_pins_b: saif0@1 {
567 reg = <1>;
568 fsl,pinmux-ids = <
bc3875f1
LW		 569 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
570 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
571 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
2e1dd9fc 572 >;
4191c340
LW		 573 fsl,drive-strength = <MXS_DRIVE_12mA>;
574 fsl,voltage = <MXS_VOLTAGE_HIGH>;
575 fsl,pull-up = <MXS_PULL_ENABLE>;
2e1dd9fc
LW		 576 };
577
530f1d41
SG		 578 saif1_pins_a: saif1@0 {
579 reg = <0>;
f14da767 580 fsl,pinmux-ids = <
bc3875f1 581 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
f14da767 582 >;
4191c340
LW		 583 fsl,drive-strength = <MXS_DRIVE_12mA>;
584 fsl,voltage = <MXS_VOLTAGE_HIGH>;
585 fsl,pull-up = <MXS_PULL_ENABLE>;
530f1d41 586 };
52f7176b 587
e1a4d18f
SG		 588 pwm0_pins_a: pwm0@0 {
589 reg = <0>;
590 fsl,pinmux-ids = <
bc3875f1 591 MX28_PAD_PWM0__PWM_0
e1a4d18f 592 >;
4191c340
LW		 593 fsl,drive-strength = <MXS_DRIVE_4mA>;
594 fsl,voltage = <MXS_VOLTAGE_HIGH>;
595 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 596 };
597
52f7176b
SG		 598 pwm2_pins_a: pwm2@0 {
599 reg = <0>;
600 fsl,pinmux-ids = <
bc3875f1 601 MX28_PAD_PWM2__PWM_2
52f7176b 602 >;
4191c340
LW		 603 fsl,drive-strength = <MXS_DRIVE_4mA>;
604 fsl,voltage = <MXS_VOLTAGE_HIGH>;
605 fsl,pull-up = <MXS_PULL_DISABLE>;
52f7176b 606 };
a915ee42 607
2bde51cb
JB		 608 pwm3_pins_a: pwm3@0 {
609 reg = <0>;
610 fsl,pinmux-ids = <
bc3875f1 611 MX28_PAD_PWM3__PWM_3
2bde51cb 612 >;
4191c340
LW		 613 fsl,drive-strength = <MXS_DRIVE_4mA>;
614 fsl,voltage = <MXS_VOLTAGE_HIGH>;
615 fsl,pull-up = <MXS_PULL_DISABLE>;
2bde51cb
JB		 616 };
617
d248620c
MR		 618 pwm3_pins_b: pwm3@1 {
619 reg = <1>;
620 fsl,pinmux-ids = <
bc3875f1 621 MX28_PAD_SAIF0_MCLK__PWM_3
d248620c 622 >;
4191c340
LW		 623 fsl,drive-strength = <MXS_DRIVE_4mA>;
624 fsl,voltage = <MXS_VOLTAGE_HIGH>;
625 fsl,pull-up = <MXS_PULL_DISABLE>;
d248620c
MR		 626 };
627
2f44211f
MR		 628 pwm4_pins_a: pwm4@0 {
629 reg = <0>;
630 fsl,pinmux-ids = <
bc3875f1 631 MX28_PAD_PWM4__PWM_4
2f44211f 632 >;
4191c340
LW		 633 fsl,drive-strength = <MXS_DRIVE_4mA>;
634 fsl,voltage = <MXS_VOLTAGE_HIGH>;
635 fsl,pull-up = <MXS_PULL_DISABLE>;
2f44211f
MR		 636 };
637
a915ee42
SG		 638 lcdif_24bit_pins_a: lcdif-24bit@0 {
639 reg = <0>;
640 fsl,pinmux-ids = <
bc3875f1
LW		 641 MX28_PAD_LCD_D00__LCD_D0
642 MX28_PAD_LCD_D01__LCD_D1
643 MX28_PAD_LCD_D02__LCD_D2
644 MX28_PAD_LCD_D03__LCD_D3
645 MX28_PAD_LCD_D04__LCD_D4
646 MX28_PAD_LCD_D05__LCD_D5
647 MX28_PAD_LCD_D06__LCD_D6
648 MX28_PAD_LCD_D07__LCD_D7
649 MX28_PAD_LCD_D08__LCD_D8
650 MX28_PAD_LCD_D09__LCD_D9
651 MX28_PAD_LCD_D10__LCD_D10
652 MX28_PAD_LCD_D11__LCD_D11
653 MX28_PAD_LCD_D12__LCD_D12
654 MX28_PAD_LCD_D13__LCD_D13
655 MX28_PAD_LCD_D14__LCD_D14
656 MX28_PAD_LCD_D15__LCD_D15
657 MX28_PAD_LCD_D16__LCD_D16
658 MX28_PAD_LCD_D17__LCD_D17
659 MX28_PAD_LCD_D18__LCD_D18
660 MX28_PAD_LCD_D19__LCD_D19
661 MX28_PAD_LCD_D20__LCD_D20
662 MX28_PAD_LCD_D21__LCD_D21
663 MX28_PAD_LCD_D22__LCD_D22
664 MX28_PAD_LCD_D23__LCD_D23
a915ee42 665 >;
4191c340
LW		 666 fsl,drive-strength = <MXS_DRIVE_4mA>;
667 fsl,voltage = <MXS_VOLTAGE_HIGH>;
668 fsl,pull-up = <MXS_PULL_DISABLE>;
a915ee42 669 };
6ca44acf 670
ec985eb2
DC		 671 lcdif_18bit_pins_a: lcdif-18bit@0 {
672 reg = <0>;
673 fsl,pinmux-ids = <
674 MX28_PAD_LCD_D00__LCD_D0
675 MX28_PAD_LCD_D01__LCD_D1
676 MX28_PAD_LCD_D02__LCD_D2
677 MX28_PAD_LCD_D03__LCD_D3
678 MX28_PAD_LCD_D04__LCD_D4
679 MX28_PAD_LCD_D05__LCD_D5
680 MX28_PAD_LCD_D06__LCD_D6
681 MX28_PAD_LCD_D07__LCD_D7
682 MX28_PAD_LCD_D08__LCD_D8
683 MX28_PAD_LCD_D09__LCD_D9
684 MX28_PAD_LCD_D10__LCD_D10
685 MX28_PAD_LCD_D11__LCD_D11
686 MX28_PAD_LCD_D12__LCD_D12
687 MX28_PAD_LCD_D13__LCD_D13
688 MX28_PAD_LCD_D14__LCD_D14
689 MX28_PAD_LCD_D15__LCD_D15
690 MX28_PAD_LCD_D16__LCD_D16
691 MX28_PAD_LCD_D17__LCD_D17
692 >;
693 fsl,drive-strength = <MXS_DRIVE_4mA>;
694 fsl,voltage = <MXS_VOLTAGE_HIGH>;
695 fsl,pull-up = <MXS_PULL_DISABLE>;
696 };
697
4ced2a40
GGM		 698 lcdif_16bit_pins_a: lcdif-16bit@0 {
699 reg = <0>;
700 fsl,pinmux-ids = <
bc3875f1
LW		 701 MX28_PAD_LCD_D00__LCD_D0
702 MX28_PAD_LCD_D01__LCD_D1
703 MX28_PAD_LCD_D02__LCD_D2
704 MX28_PAD_LCD_D03__LCD_D3
705 MX28_PAD_LCD_D04__LCD_D4
706 MX28_PAD_LCD_D05__LCD_D5
707 MX28_PAD_LCD_D06__LCD_D6
708 MX28_PAD_LCD_D07__LCD_D7
709 MX28_PAD_LCD_D08__LCD_D8
710 MX28_PAD_LCD_D09__LCD_D9
711 MX28_PAD_LCD_D10__LCD_D10
712 MX28_PAD_LCD_D11__LCD_D11
713 MX28_PAD_LCD_D12__LCD_D12
714 MX28_PAD_LCD_D13__LCD_D13
715 MX28_PAD_LCD_D14__LCD_D14
716 MX28_PAD_LCD_D15__LCD_D15
4ced2a40 717 >;
4191c340
LW		 718 fsl,drive-strength = <MXS_DRIVE_4mA>;
719 fsl,voltage = <MXS_VOLTAGE_HIGH>;
720 fsl,pull-up = <MXS_PULL_DISABLE>;
4ced2a40
GGM		 721 };
722
23ad6f65
LW		 723 lcdif_sync_pins_a: lcdif-sync@0 {
724 reg = <0>;
725 fsl,pinmux-ids = <
bc3875f1
LW		 726 MX28_PAD_LCD_RS__LCD_DOTCLK
727 MX28_PAD_LCD_CS__LCD_ENABLE
728 MX28_PAD_LCD_RD_E__LCD_VSYNC
729 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
23ad6f65 730 >;
4191c340
LW		 731 fsl,drive-strength = <MXS_DRIVE_4mA>;
732 fsl,voltage = <MXS_VOLTAGE_HIGH>;
733 fsl,pull-up = <MXS_PULL_DISABLE>;
23ad6f65
LW		 734 };
735
6ca44acf
SG		 736 can0_pins_a: can0@0 {
737 reg = <0>;
738 fsl,pinmux-ids = <
bc3875f1
LW		 739 MX28_PAD_GPMI_RDY2__CAN0_TX
740 MX28_PAD_GPMI_RDY3__CAN0_RX
6ca44acf 741 >;
4191c340
LW		 742 fsl,drive-strength = <MXS_DRIVE_4mA>;
743 fsl,voltage = <MXS_VOLTAGE_HIGH>;
744 fsl,pull-up = <MXS_PULL_DISABLE>;
6ca44acf
SG		 745 };
746
747 can1_pins_a: can1@0 {
748 reg = <0>;
749 fsl,pinmux-ids = <
bc3875f1
LW		 750 MX28_PAD_GPMI_CE2N__CAN1_TX
751 MX28_PAD_GPMI_CE3N__CAN1_RX
6ca44acf 752 >;
4191c340
LW		 753 fsl,drive-strength = <MXS_DRIVE_4mA>;
754 fsl,voltage = <MXS_VOLTAGE_HIGH>;
755 fsl,pull-up = <MXS_PULL_DISABLE>;
6ca44acf 756 };
7f122213
MV		 757
758 spi2_pins_a: spi2@0 {
759 reg = <0>;
760 fsl,pinmux-ids = <
bc3875f1
LW		 761 MX28_PAD_SSP2_SCK__SSP2_SCK
762 MX28_PAD_SSP2_MOSI__SSP2_CMD
763 MX28_PAD_SSP2_MISO__SSP2_D0
764 MX28_PAD_SSP2_SS0__SSP2_D3
7f122213 765 >;
4191c340
LW		 766 fsl,drive-strength = <MXS_DRIVE_8mA>;
767 fsl,voltage = <MXS_VOLTAGE_HIGH>;
768 fsl,pull-up = <MXS_PULL_ENABLE>;
7f122213 769 };
bb2f1261 770
3314d2be
LW		 771 spi3_pins_a: spi3@0 {
772 reg = <0>;
773 fsl,pinmux-ids = <
bc3875f1
LW		 774 MX28_PAD_AUART2_RX__SSP3_D4
775 MX28_PAD_AUART2_TX__SSP3_D5
776 MX28_PAD_SSP3_SCK__SSP3_SCK
777 MX28_PAD_SSP3_MOSI__SSP3_CMD
778 MX28_PAD_SSP3_MISO__SSP3_D0
779 MX28_PAD_SSP3_SS0__SSP3_D3
3314d2be 780 >;
4191c340
LW		 781 fsl,drive-strength = <MXS_DRIVE_8mA>;
782 fsl,voltage = <MXS_VOLTAGE_HIGH>;
783 fsl,pull-up = <MXS_PULL_DISABLE>;
3314d2be
LW		 784 };
785
c8e42bc9 786 usb0_pins_a: usb0@0 {
bb2f1261
MV		 787 reg = <0>;
788 fsl,pinmux-ids = <
bc3875f1 789 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
bb2f1261 790 >;
4191c340
LW		 791 fsl,drive-strength = <MXS_DRIVE_12mA>;
792 fsl,voltage = <MXS_VOLTAGE_HIGH>;
793 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261
MV		 794 };
795
c8e42bc9 796 usb0_pins_b: usb0@1 {
bb2f1261
MV		 797 reg = <1>;
798 fsl,pinmux-ids = <
bc3875f1 799 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
bb2f1261 800 >;
4191c340
LW		 801 fsl,drive-strength = <MXS_DRIVE_12mA>;
802 fsl,voltage = <MXS_VOLTAGE_HIGH>;
803 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261
MV		 804 };
805
c8e42bc9 806 usb1_pins_a: usb1@0 {
bb2f1261
MV		 807 reg = <0>;
808 fsl,pinmux-ids = <
bc3875f1 809 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
bb2f1261 810 >;
4191c340
LW		 811 fsl,drive-strength = <MXS_DRIVE_12mA>;
812 fsl,voltage = <MXS_VOLTAGE_HIGH>;
813 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261 814 };
69c02f95
FE		 815
816 usb0_id_pins_a: usb0id@0 {
817 reg = <0>;
818 fsl,pinmux-ids = <
e96e1782 819 MX28_PAD_AUART1_RTS__USB0_ID
bb2f1261 820 >;
e96e1782
LW		 821 fsl,drive-strength = <MXS_DRIVE_12mA>;
822 fsl,voltage = <MXS_VOLTAGE_HIGH>;
823 fsl,pull-up = <MXS_PULL_ENABLE>;
bb2f1261 824 };
bb89b8d2
DC		 825
826 usb0_id_pins_b: usb0id1@0 {
827 reg = <0>;
828 fsl,pinmux-ids = <
829 MX28_PAD_PWM2__USB0_ID
830 >;
831 fsl,drive-strength = <MXS_DRIVE_12mA>;
832 fsl,voltage = <MXS_VOLTAGE_HIGH>;
833 fsl,pull-up = <MXS_PULL_ENABLE>;
834 };
835
bc3a59c1
DA		 836 };
837
296f8cd3 838 digctl: digctl@8001c000 {
115581cf 839 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
0f06cde7 840 reg = <0x8001c000 0x2000>;
bc3a59c1
DA		 841 interrupts = <89>;
842 status = "disabled";
843 };
844
296f8cd3 845 etm: etm@80022000 {
0f06cde7 846 reg = <0x80022000 0x2000>;
bc3a59c1
DA		 847 status = "disabled";
848 };
849
f30fb03d 850 dma_apbx: dma-apbx@80024000 {
84f3570a 851 compatible = "fsl,imx28-dma-apbx";
0f06cde7 852 reg = <0x80024000 0x2000>;
f30fb03d
SG		 853 interrupts = <78 79 66 0
854 80 81 68 69
855 70 71 72 73
856 74 75 76 77>;
857 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
858 "saif0", "saif1", "i2c0", "i2c1",
859 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
860 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
861 #dma-cells = <1>;
862 dma-channels = <16>;
b598b9f3 863 clocks = <&clks 26>;
bc3a59c1
DA		 864 };
865
296f8cd3 866 dcp: dcp@80028000 {
7d56a28f 867 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
0f06cde7 868 reg = <0x80028000 0x2000>;
bc3a59c1 869 interrupts = <52 53 54>;
7d56a28f 870 status = "okay";
bc3a59c1
DA		 871 };
872
296f8cd3 873 pxp: pxp@8002a000 {
0f06cde7 874 reg = <0x8002a000 0x2000>;
bc3a59c1
DA		 875 interrupts = <39>;
876 status = "disabled";
877 };
878
296f8cd3 879 ocotp: ocotp@8002c000 {
69d75a02 880 compatible = "fsl,ocotp";
0f06cde7 881 reg = <0x8002c000 0x2000>;
bc3a59c1
DA		 882 status = "disabled";
883 };
884
885 axi-ahb@8002e000 {
0f06cde7 886 reg = <0x8002e000 0x2000>;
bc3a59c1
DA		 887 status = "disabled";
888 };
889
296f8cd3 890 lcdif: lcdif@80030000 {
a915ee42 891 compatible = "fsl,imx28-lcdif";
0f06cde7 892 reg = <0x80030000 0x2000>;
7f2b9288 893 interrupts = <38>;
b598b9f3 894 clocks = <&clks 55>;
f30fb03d
SG		 895 dmas = <&dma_apbh 13>;
896 dma-names = "rx";
bc3a59c1
DA		 897 status = "disabled";
898 };
899
900 can0: can@80032000 {
6ca44acf 901 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 902 reg = <0x80032000 0x2000>;
bc3a59c1 903 interrupts = <8>;
b598b9f3
SG		 904 clocks = <&clks 58>, <&clks 58>;
905 clock-names = "ipg", "per";
bc3a59c1
DA		 906 status = "disabled";
907 };
908
909 can1: can@80034000 {
6ca44acf 910 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 911 reg = <0x80034000 0x2000>;
bc3a59c1 912 interrupts = <9>;
b598b9f3
SG		 913 clocks = <&clks 59>, <&clks 59>;
914 clock-names = "ipg", "per";
bc3a59c1
DA		 915 status = "disabled";
916 };
917
296f8cd3 918 simdbg: simdbg@8003c000 {
0f06cde7 919 reg = <0x8003c000 0x200>;
bc3a59c1
DA		 920 status = "disabled";
921 };
922
296f8cd3 923 simgpmisel: simgpmisel@8003c200 {
0f06cde7 924 reg = <0x8003c200 0x100>;
bc3a59c1
DA		 925 status = "disabled";
926 };
927
296f8cd3 928 simsspsel: simsspsel@8003c300 {
0f06cde7 929 reg = <0x8003c300 0x100>;
bc3a59c1
DA		 930 status = "disabled";
931 };
932
296f8cd3 933 simmemsel: simmemsel@8003c400 {
0f06cde7 934 reg = <0x8003c400 0x100>;
bc3a59c1
DA		 935 status = "disabled";
936 };
937
296f8cd3 938 gpiomon: gpiomon@8003c500 {
0f06cde7 939 reg = <0x8003c500 0x100>;
bc3a59c1
DA		 940 status = "disabled";
941 };
942
296f8cd3 943 simenet: simenet@8003c700 {
0f06cde7 944 reg = <0x8003c700 0x100>;
bc3a59c1
DA		 945 status = "disabled";
946 };
947
296f8cd3 948 armjtag: armjtag@8003c800 {
0f06cde7 949 reg = <0x8003c800 0x100>;
bc3a59c1
DA		 950 status = "disabled";
951 };
07a3ce7f 952 };
bc3a59c1
DA		 953
954 apbx@80040000 {
955 compatible = "simple-bus";
956 #address-cells = <1>;
957 #size-cells = <1>;
958 reg = <0x80040000 0x40000>;
959 ranges;
960
b598b9f3 961 clks: clkctrl@80040000 {
8f7cf881 962 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
0f06cde7 963 reg = <0x80040000 0x2000>;
b598b9f3 964 #clock-cells = <1>;
bc3a59c1
DA		 965 };
966
967 saif0: saif@80042000 {
530f1d41 968 compatible = "fsl,imx28-saif";
0f06cde7 969 reg = <0x80042000 0x2000>;
7f2b9288 970 interrupts = <59>;
66acaf3f 971 #clock-cells = <0>;
b598b9f3 972 clocks = <&clks 53>;
f30fb03d
SG		 973 dmas = <&dma_apbx 4>;
974 dma-names = "rx-tx";
bc3a59c1
DA		 975 status = "disabled";
976 };
977
296f8cd3 978 power: power@80044000 {
0f06cde7 979 reg = <0x80044000 0x2000>;
bc3a59c1
DA		 980 status = "disabled";
981 };
982
983 saif1: saif@80046000 {
530f1d41 984 compatible = "fsl,imx28-saif";
0f06cde7 985 reg = <0x80046000 0x2000>;
7f2b9288 986 interrupts = <58>;
b598b9f3 987 clocks = <&clks 54>;
f30fb03d
SG		 988 dmas = <&dma_apbx 5>;
989 dma-names = "rx-tx";
bc3a59c1
DA		 990 status = "disabled";
991 };
992
296f8cd3 993 lradc: lradc@80050000 {
aef35104 994 compatible = "fsl,imx28-lradc";
0f06cde7 995 reg = <0x80050000 0x2000>;
aef35104
MV		 996 interrupts = <10 14 15 16 17 18 19
997 20 21 22 23 24 25>;
bc3a59c1 998 status = "disabled";
18da755d 999 clocks = <&clks 41>;
40dde681 1000 #io-channel-cells = <1>;
bc3a59c1
DA		 1001 };
1002
296f8cd3 1003 spdif: spdif@80054000 {
0f06cde7 1004 reg = <0x80054000 0x2000>;
7f2b9288 1005 interrupts = <45>;
f30fb03d
SG		 1006 dmas = <&dma_apbx 2>;
1007 dma-names = "tx";
bc3a59c1
DA		 1008 status = "disabled";
1009 };
1010
296f8cd3 1011 mxs_rtc: rtc@80056000 {
f98c990c 1012 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
0f06cde7 1013 reg = <0x80056000 0x2000>;
f98c990c 1014 interrupts = <29>;
bc3a59c1
DA		 1015 };
1016
1017 i2c0: i2c@80058000 {
2a96e391
SG		 1018 #address-cells = <1>;
1019 #size-cells = <0>;
1020 compatible = "fsl,imx28-i2c";
0f06cde7 1021 reg = <0x80058000 0x2000>;
7f2b9288 1022 interrupts = <111>;
cd4f2d4a 1023 clock-frequency = <100000>;
f30fb03d
SG		 1024 dmas = <&dma_apbx 6>;
1025 dma-names = "rx-tx";
bc3a59c1
DA		 1026 status = "disabled";
1027 };
1028
1029 i2c1: i2c@8005a000 {
2a96e391
SG		 1030 #address-cells = <1>;
1031 #size-cells = <0>;
1032 compatible = "fsl,imx28-i2c";
0f06cde7 1033 reg = <0x8005a000 0x2000>;
7f2b9288 1034 interrupts = <110>;
cd4f2d4a 1035 clock-frequency = <100000>;
f30fb03d
SG		 1036 dmas = <&dma_apbx 7>;
1037 dma-names = "rx-tx";
bc3a59c1
DA		 1038 status = "disabled";
1039 };
1040
52f7176b
SG		 1041 pwm: pwm@80064000 {
1042 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
0f06cde7 1043 reg = <0x80064000 0x2000>;
b598b9f3 1044 clocks = <&clks 44>;
52f7176b
SG		 1045 #pwm-cells = <2>;
1046 fsl,pwm-number = <8>;
bc3a59c1
DA		 1047 status = "disabled";
1048 };
1049
296f8cd3 1050 timer: timrot@80068000 {
eeca6e60 1051 compatible = "fsl,imx28-timrot", "fsl,timrot";
0f06cde7 1052 reg = <0x80068000 0x2000>;
eeca6e60 1053 interrupts = <48 49 50 51>;
2efb9504 1054 clocks = <&clks 26>;
bc3a59c1
DA		 1055 };
1056
1057 auart0: serial@8006a000 {
80d969e4 1058 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1059 reg = <0x8006a000 0x2000>;
7f2b9288 1060 interrupts = <112>;
f30fb03d
SG		 1061 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1062 dma-names = "rx", "tx";
b598b9f3 1063 clocks = <&clks 45>;
bc3a59c1
DA		 1064 status = "disabled";
1065 };
1066
1067 auart1: serial@8006c000 {
80d969e4 1068 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1069 reg = <0x8006c000 0x2000>;
7f2b9288 1070 interrupts = <113>;
f30fb03d
SG		 1071 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1072 dma-names = "rx", "tx";
b598b9f3 1073 clocks = <&clks 45>;
bc3a59c1
DA		 1074 status = "disabled";
1075 };
1076
1077 auart2: serial@8006e000 {
80d969e4 1078 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1079 reg = <0x8006e000 0x2000>;
7f2b9288 1080 interrupts = <114>;
f30fb03d
SG		 1081 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1082 dma-names = "rx", "tx";
b598b9f3 1083 clocks = <&clks 45>;
bc3a59c1
DA		 1084 status = "disabled";
1085 };
1086
1087 auart3: serial@80070000 {
80d969e4 1088 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1089 reg = <0x80070000 0x2000>;
7f2b9288 1090 interrupts = <115>;
f30fb03d
SG		 1091 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1092 dma-names = "rx", "tx";
b598b9f3 1093 clocks = <&clks 45>;
bc3a59c1
DA		 1094 status = "disabled";
1095 };
1096
1097 auart4: serial@80072000 {
80d969e4 1098 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1099 reg = <0x80072000 0x2000>;
7f2b9288 1100 interrupts = <116>;
f30fb03d
SG		 1101 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1102 dma-names = "rx", "tx";
b598b9f3 1103 clocks = <&clks 45>;
bc3a59c1
DA		 1104 status = "disabled";
1105 };
1106
1107 duart: serial@80074000 {
1108 compatible = "arm,pl011", "arm,primecell";
1109 reg = <0x80074000 0x1000>;
1110 interrupts = <47>;
b598b9f3
SG		 1111 clocks = <&clks 45>, <&clks 26>;
1112 clock-names = "uart", "apb_pclk";
bc3a59c1
DA		 1113 status = "disabled";
1114 };
1115
1116 usbphy0: usbphy@8007c000 {
5da01270 1117 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 1118 reg = <0x8007c000 0x2000>;
b598b9f3 1119 clocks = <&clks 62>;
bc3a59c1
DA		 1120 status = "disabled";
1121 };
1122
1123 usbphy1: usbphy@8007e000 {
5da01270 1124 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 1125 reg = <0x8007e000 0x2000>;
b598b9f3 1126 clocks = <&clks 63>;
bc3a59c1
DA		 1127 status = "disabled";
1128 };
1129 };
1130 };
1131
1132 ahb@80080000 {
1133 compatible = "simple-bus";
1134 #address-cells = <1>;
1135 #size-cells = <1>;
1136 reg = <0x80080000 0x80000>;
1137 ranges;
1138
5da01270
RZ		 1139 usb0: usb@80080000 {
1140 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 1141 reg = <0x80080000 0x10000>;
5da01270 1142 interrupts = <93>;
b598b9f3 1143 clocks = <&clks 60>;
5da01270 1144 fsl,usbphy = <&usbphy0>;
bc3a59c1
DA		 1145 status = "disabled";
1146 };
1147
5da01270
RZ		 1148 usb1: usb@80090000 {
1149 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 1150 reg = <0x80090000 0x10000>;
5da01270 1151 interrupts = <92>;
b598b9f3 1152 clocks = <&clks 61>;
5da01270 1153 fsl,usbphy = <&usbphy1>;
bc3a59c1
DA		 1154 status = "disabled";
1155 };
1156
296f8cd3 1157 dflpt: dflpt@800c0000 {
bc3a59c1
DA		 1158 reg = <0x800c0000 0x10000>;
1159 status = "disabled";
1160 };
1161
1162 mac0: ethernet@800f0000 {
1163 compatible = "fsl,imx28-fec";
1164 reg = <0x800f0000 0x4000>;
1165 interrupts = <101>;
f231a9fe
WS		 1166 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1167 clock-names = "ipg", "ahb", "enet_out";
bc3a59c1
DA		 1168 status = "disabled";
1169 };
1170
1171 mac1: ethernet@800f4000 {
1172 compatible = "fsl,imx28-fec";
1173 reg = <0x800f4000 0x4000>;
1174 interrupts = <102>;
b598b9f3
SG		 1175 clocks = <&clks 57>, <&clks 57>;
1176 clock-names = "ipg", "ahb";
bc3a59c1
DA		 1177 status = "disabled";
1178 };
1179
296f8cd3 1180 etn_switch: switch@800f8000 {
bc3a59c1
DA		 1181 reg = <0x800f8000 0x8000>;
1182 status = "disabled";
1183 };
bc3a59c1 1184 };
f92dfb02
AB		 1185
1186 iio_hwmon {
1187 compatible = "iio-hwmon";
1188 io-channels = <&lradc 8>;
1189 };
bc3a59c1 1190};
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