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Commit | Line | Data |
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bc3a59c1 DA |
1 | /* |
2 | * Copyright 2012 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | /include/ "skeleton.dtsi" | |
13 | ||
14 | / { | |
15 | interrupt-parent = <&icoll>; | |
16 | ||
ce4c6f9b SG |
17 | aliases { |
18 | gpio0 = &gpio0; | |
19 | gpio1 = &gpio1; | |
20 | gpio2 = &gpio2; | |
21 | gpio3 = &gpio3; | |
22 | gpio4 = &gpio4; | |
530f1d41 SG |
23 | saif0 = &saif0; |
24 | saif1 = &saif1; | |
80d969e4 FE |
25 | serial0 = &auart0; |
26 | serial1 = &auart1; | |
27 | serial2 = &auart2; | |
28 | serial3 = &auart3; | |
29 | serial4 = &auart4; | |
ce4c6f9b SG |
30 | }; |
31 | ||
bc3a59c1 DA |
32 | cpus { |
33 | cpu@0 { | |
34 | compatible = "arm,arm926ejs"; | |
35 | }; | |
36 | }; | |
37 | ||
38 | apb@80000000 { | |
39 | compatible = "simple-bus"; | |
40 | #address-cells = <1>; | |
41 | #size-cells = <1>; | |
42 | reg = <0x80000000 0x80000>; | |
43 | ranges; | |
44 | ||
45 | apbh@80000000 { | |
46 | compatible = "simple-bus"; | |
47 | #address-cells = <1>; | |
48 | #size-cells = <1>; | |
49 | reg = <0x80000000 0x3c900>; | |
50 | ranges; | |
51 | ||
52 | icoll: interrupt-controller@80000000 { | |
53 | compatible = "fsl,imx28-icoll", "fsl,mxs-icoll"; | |
54 | interrupt-controller; | |
55 | #interrupt-cells = <1>; | |
56 | reg = <0x80000000 0x2000>; | |
57 | }; | |
58 | ||
59 | hsadc@80002000 { | |
60 | reg = <0x80002000 2000>; | |
61 | interrupts = <13 87>; | |
62 | status = "disabled"; | |
63 | }; | |
64 | ||
65 | dma-apbh@80004000 { | |
84f3570a | 66 | compatible = "fsl,imx28-dma-apbh"; |
bc3a59c1 | 67 | reg = <0x80004000 2000>; |
bc3a59c1 DA |
68 | }; |
69 | ||
70 | perfmon@80006000 { | |
71 | reg = <0x80006000 800>; | |
72 | interrupts = <27>; | |
73 | status = "disabled"; | |
74 | }; | |
75 | ||
7a8e5149 HS |
76 | gpmi-nand@8000c000 { |
77 | compatible = "fsl,imx28-gpmi-nand"; | |
78 | #address-cells = <1>; | |
79 | #size-cells = <1>; | |
80 | reg = <0x8000c000 2000>, <0x8000a000 2000>; | |
81 | reg-names = "gpmi-nand", "bch"; | |
82 | interrupts = <88>, <41>; | |
83 | interrupt-names = "gpmi-dma", "bch"; | |
84 | fsl,gpmi-dma-channel = <4>; | |
bc3a59c1 DA |
85 | status = "disabled"; |
86 | }; | |
87 | ||
88 | ssp0: ssp@80010000 { | |
89 | reg = <0x80010000 2000>; | |
90 | interrupts = <96 82>; | |
35d23047 | 91 | fsl,ssp-dma-channel = <0>; |
bc3a59c1 DA |
92 | status = "disabled"; |
93 | }; | |
94 | ||
95 | ssp1: ssp@80012000 { | |
96 | reg = <0x80012000 2000>; | |
97 | interrupts = <97 83>; | |
35d23047 | 98 | fsl,ssp-dma-channel = <1>; |
bc3a59c1 DA |
99 | status = "disabled"; |
100 | }; | |
101 | ||
102 | ssp2: ssp@80014000 { | |
103 | reg = <0x80014000 2000>; | |
104 | interrupts = <98 84>; | |
35d23047 | 105 | fsl,ssp-dma-channel = <2>; |
bc3a59c1 DA |
106 | status = "disabled"; |
107 | }; | |
108 | ||
109 | ssp3: ssp@80016000 { | |
110 | reg = <0x80016000 2000>; | |
111 | interrupts = <99 85>; | |
35d23047 | 112 | fsl,ssp-dma-channel = <3>; |
bc3a59c1 DA |
113 | status = "disabled"; |
114 | }; | |
115 | ||
116 | pinctrl@80018000 { | |
117 | #address-cells = <1>; | |
118 | #size-cells = <0>; | |
ce4c6f9b | 119 | compatible = "fsl,imx28-pinctrl", "simple-bus"; |
bc3a59c1 DA |
120 | reg = <0x80018000 2000>; |
121 | ||
ce4c6f9b SG |
122 | gpio0: gpio@0 { |
123 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
124 | interrupts = <127>; | |
125 | gpio-controller; | |
126 | #gpio-cells = <2>; | |
127 | interrupt-controller; | |
128 | #interrupt-cells = <2>; | |
129 | }; | |
130 | ||
131 | gpio1: gpio@1 { | |
132 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
133 | interrupts = <126>; | |
134 | gpio-controller; | |
135 | #gpio-cells = <2>; | |
136 | interrupt-controller; | |
137 | #interrupt-cells = <2>; | |
138 | }; | |
139 | ||
140 | gpio2: gpio@2 { | |
141 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
142 | interrupts = <125>; | |
143 | gpio-controller; | |
144 | #gpio-cells = <2>; | |
145 | interrupt-controller; | |
146 | #interrupt-cells = <2>; | |
147 | }; | |
148 | ||
149 | gpio3: gpio@3 { | |
150 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
151 | interrupts = <124>; | |
152 | gpio-controller; | |
153 | #gpio-cells = <2>; | |
154 | interrupt-controller; | |
155 | #interrupt-cells = <2>; | |
156 | }; | |
157 | ||
158 | gpio4: gpio@4 { | |
159 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
160 | interrupts = <123>; | |
161 | gpio-controller; | |
162 | #gpio-cells = <2>; | |
163 | interrupt-controller; | |
164 | #interrupt-cells = <2>; | |
165 | }; | |
166 | ||
bc3a59c1 DA |
167 | duart_pins_a: duart@0 { |
168 | reg = <0>; | |
f14da767 SG |
169 | fsl,pinmux-ids = < |
170 | 0x3102 /* MX28_PAD_PWM0__DUART_RX */ | |
171 | 0x3112 /* MX28_PAD_PWM1__DUART_TX */ | |
172 | >; | |
bc3a59c1 DA |
173 | fsl,drive-strength = <0>; |
174 | fsl,voltage = <1>; | |
175 | fsl,pull-up = <0>; | |
176 | }; | |
177 | ||
8385e7c1 MR |
178 | duart_pins_b: duart@1 { |
179 | reg = <1>; | |
f14da767 SG |
180 | fsl,pinmux-ids = < |
181 | 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ | |
182 | 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ | |
183 | >; | |
8385e7c1 MR |
184 | fsl,drive-strength = <0>; |
185 | fsl,voltage = <1>; | |
186 | fsl,pull-up = <0>; | |
187 | }; | |
188 | ||
7a8e5149 HS |
189 | gpmi_pins_a: gpmi-nand@0 { |
190 | reg = <0>; | |
f14da767 SG |
191 | fsl,pinmux-ids = < |
192 | 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */ | |
193 | 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */ | |
194 | 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */ | |
195 | 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */ | |
196 | 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */ | |
197 | 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */ | |
198 | 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */ | |
199 | 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */ | |
200 | 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */ | |
f14da767 | 201 | 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */ |
f14da767 SG |
202 | 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ |
203 | 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ | |
204 | 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */ | |
205 | 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */ | |
206 | 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ | |
207 | >; | |
7a8e5149 HS |
208 | fsl,drive-strength = <0>; |
209 | fsl,voltage = <1>; | |
210 | fsl,pull-up = <0>; | |
211 | }; | |
212 | ||
213 | gpmi_status_cfg: gpmi-status-cfg { | |
f14da767 SG |
214 | fsl,pinmux-ids = < |
215 | 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ | |
216 | 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ | |
217 | 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ | |
218 | >; | |
7a8e5149 HS |
219 | fsl,drive-strength = <2>; |
220 | }; | |
221 | ||
80d969e4 FE |
222 | auart0_pins_a: auart0@0 { |
223 | reg = <0>; | |
f14da767 SG |
224 | fsl,pinmux-ids = < |
225 | 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ | |
226 | 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ | |
227 | 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */ | |
228 | 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */ | |
229 | >; | |
80d969e4 FE |
230 | fsl,drive-strength = <0>; |
231 | fsl,voltage = <1>; | |
232 | fsl,pull-up = <0>; | |
233 | }; | |
234 | ||
235 | auart3_pins_a: auart3@0 { | |
236 | reg = <0>; | |
f14da767 SG |
237 | fsl,pinmux-ids = < |
238 | 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */ | |
239 | 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */ | |
240 | 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */ | |
241 | 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */ | |
242 | >; | |
80d969e4 FE |
243 | fsl,drive-strength = <0>; |
244 | fsl,voltage = <1>; | |
245 | fsl,pull-up = <0>; | |
246 | }; | |
247 | ||
bc3a59c1 DA |
248 | mac0_pins_a: mac0@0 { |
249 | reg = <0>; | |
f14da767 SG |
250 | fsl,pinmux-ids = < |
251 | 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */ | |
252 | 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */ | |
253 | 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */ | |
254 | 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */ | |
255 | 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */ | |
256 | 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */ | |
257 | 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */ | |
258 | 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */ | |
259 | 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */ | |
260 | >; | |
bc3a59c1 DA |
261 | fsl,drive-strength = <1>; |
262 | fsl,voltage = <1>; | |
263 | fsl,pull-up = <1>; | |
264 | }; | |
265 | ||
266 | mac1_pins_a: mac1@0 { | |
267 | reg = <0>; | |
f14da767 SG |
268 | fsl,pinmux-ids = < |
269 | 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */ | |
270 | 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */ | |
271 | 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */ | |
272 | 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */ | |
273 | 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */ | |
274 | 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */ | |
275 | >; | |
bc3a59c1 DA |
276 | fsl,drive-strength = <1>; |
277 | fsl,voltage = <1>; | |
278 | fsl,pull-up = <1>; | |
279 | }; | |
35d23047 SG |
280 | |
281 | mmc0_8bit_pins_a: mmc0-8bit@0 { | |
282 | reg = <0>; | |
f14da767 SG |
283 | fsl,pinmux-ids = < |
284 | 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ | |
285 | 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ | |
286 | 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ | |
287 | 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ | |
288 | 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */ | |
289 | 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */ | |
290 | 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */ | |
291 | 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */ | |
292 | 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ | |
293 | 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ | |
294 | 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ | |
295 | >; | |
35d23047 SG |
296 | fsl,drive-strength = <1>; |
297 | fsl,voltage = <1>; | |
298 | fsl,pull-up = <1>; | |
299 | }; | |
300 | ||
8385e7c1 MR |
301 | mmc0_4bit_pins_a: mmc0-4bit@0 { |
302 | reg = <0>; | |
f14da767 SG |
303 | fsl,pinmux-ids = < |
304 | 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ | |
305 | 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ | |
306 | 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ | |
307 | 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ | |
308 | 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ | |
309 | 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ | |
310 | 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ | |
311 | >; | |
8385e7c1 MR |
312 | fsl,drive-strength = <1>; |
313 | fsl,voltage = <1>; | |
314 | fsl,pull-up = <1>; | |
315 | }; | |
316 | ||
35d23047 | 317 | mmc0_cd_cfg: mmc0-cd-cfg { |
f14da767 SG |
318 | fsl,pinmux-ids = < |
319 | 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ | |
320 | >; | |
35d23047 SG |
321 | fsl,pull-up = <0>; |
322 | }; | |
323 | ||
324 | mmc0_sck_cfg: mmc0-sck-cfg { | |
f14da767 SG |
325 | fsl,pinmux-ids = < |
326 | 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ | |
327 | >; | |
35d23047 SG |
328 | fsl,drive-strength = <2>; |
329 | fsl,pull-up = <0>; | |
330 | }; | |
2a96e391 SG |
331 | |
332 | i2c0_pins_a: i2c0@0 { | |
333 | reg = <0>; | |
f14da767 SG |
334 | fsl,pinmux-ids = < |
335 | 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */ | |
336 | 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */ | |
337 | >; | |
2a96e391 SG |
338 | fsl,drive-strength = <1>; |
339 | fsl,voltage = <1>; | |
340 | fsl,pull-up = <1>; | |
341 | }; | |
530f1d41 SG |
342 | |
343 | saif0_pins_a: saif0@0 { | |
344 | reg = <0>; | |
f14da767 SG |
345 | fsl,pinmux-ids = < |
346 | 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */ | |
347 | 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */ | |
348 | 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */ | |
349 | 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */ | |
350 | >; | |
530f1d41 SG |
351 | fsl,drive-strength = <2>; |
352 | fsl,voltage = <1>; | |
353 | fsl,pull-up = <1>; | |
354 | }; | |
355 | ||
356 | saif1_pins_a: saif1@0 { | |
357 | reg = <0>; | |
f14da767 SG |
358 | fsl,pinmux-ids = < |
359 | 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */ | |
360 | >; | |
530f1d41 SG |
361 | fsl,drive-strength = <2>; |
362 | fsl,voltage = <1>; | |
363 | fsl,pull-up = <1>; | |
364 | }; | |
52f7176b SG |
365 | |
366 | pwm2_pins_a: pwm2@0 { | |
367 | reg = <0>; | |
368 | fsl,pinmux-ids = < | |
369 | 0x3120 /* MX28_PAD_PWM2__PWM_2 */ | |
370 | >; | |
371 | fsl,drive-strength = <0>; | |
372 | fsl,voltage = <1>; | |
373 | fsl,pull-up = <0>; | |
374 | }; | |
a915ee42 SG |
375 | |
376 | lcdif_24bit_pins_a: lcdif-24bit@0 { | |
377 | reg = <0>; | |
378 | fsl,pinmux-ids = < | |
379 | 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ | |
380 | 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ | |
381 | 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ | |
382 | 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ | |
383 | 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ | |
384 | 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ | |
385 | 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ | |
386 | 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ | |
387 | 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ | |
388 | 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ | |
389 | 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ | |
390 | 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ | |
391 | 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ | |
392 | 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ | |
393 | 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ | |
394 | 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ | |
395 | 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ | |
396 | 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ | |
397 | 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */ | |
398 | 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */ | |
399 | 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */ | |
400 | 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */ | |
401 | 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */ | |
402 | 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */ | |
a915ee42 SG |
403 | >; |
404 | fsl,drive-strength = <0>; | |
405 | fsl,voltage = <1>; | |
406 | fsl,pull-up = <0>; | |
407 | }; | |
6ca44acf SG |
408 | |
409 | can0_pins_a: can0@0 { | |
410 | reg = <0>; | |
411 | fsl,pinmux-ids = < | |
412 | 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */ | |
413 | 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */ | |
414 | >; | |
415 | fsl,drive-strength = <0>; | |
416 | fsl,voltage = <1>; | |
417 | fsl,pull-up = <0>; | |
418 | }; | |
419 | ||
420 | can1_pins_a: can1@0 { | |
421 | reg = <0>; | |
422 | fsl,pinmux-ids = < | |
423 | 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */ | |
424 | 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */ | |
425 | >; | |
426 | fsl,drive-strength = <0>; | |
427 | fsl,voltage = <1>; | |
428 | fsl,pull-up = <0>; | |
429 | }; | |
bc3a59c1 DA |
430 | }; |
431 | ||
432 | digctl@8001c000 { | |
433 | reg = <0x8001c000 2000>; | |
434 | interrupts = <89>; | |
435 | status = "disabled"; | |
436 | }; | |
437 | ||
438 | etm@80022000 { | |
439 | reg = <0x80022000 2000>; | |
440 | status = "disabled"; | |
441 | }; | |
442 | ||
443 | dma-apbx@80024000 { | |
84f3570a | 444 | compatible = "fsl,imx28-dma-apbx"; |
bc3a59c1 | 445 | reg = <0x80024000 2000>; |
bc3a59c1 DA |
446 | }; |
447 | ||
448 | dcp@80028000 { | |
449 | reg = <0x80028000 2000>; | |
450 | interrupts = <52 53 54>; | |
451 | status = "disabled"; | |
452 | }; | |
453 | ||
454 | pxp@8002a000 { | |
455 | reg = <0x8002a000 2000>; | |
456 | interrupts = <39>; | |
457 | status = "disabled"; | |
458 | }; | |
459 | ||
460 | ocotp@8002c000 { | |
461 | reg = <0x8002c000 2000>; | |
462 | status = "disabled"; | |
463 | }; | |
464 | ||
465 | axi-ahb@8002e000 { | |
466 | reg = <0x8002e000 2000>; | |
467 | status = "disabled"; | |
468 | }; | |
469 | ||
470 | lcdif@80030000 { | |
a915ee42 | 471 | compatible = "fsl,imx28-lcdif"; |
bc3a59c1 DA |
472 | reg = <0x80030000 2000>; |
473 | interrupts = <38 86>; | |
474 | status = "disabled"; | |
475 | }; | |
476 | ||
477 | can0: can@80032000 { | |
6ca44acf | 478 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; |
bc3a59c1 DA |
479 | reg = <0x80032000 2000>; |
480 | interrupts = <8>; | |
481 | status = "disabled"; | |
482 | }; | |
483 | ||
484 | can1: can@80034000 { | |
6ca44acf | 485 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; |
bc3a59c1 DA |
486 | reg = <0x80034000 2000>; |
487 | interrupts = <9>; | |
488 | status = "disabled"; | |
489 | }; | |
490 | ||
491 | simdbg@8003c000 { | |
492 | reg = <0x8003c000 200>; | |
493 | status = "disabled"; | |
494 | }; | |
495 | ||
496 | simgpmisel@8003c200 { | |
497 | reg = <0x8003c200 100>; | |
498 | status = "disabled"; | |
499 | }; | |
500 | ||
501 | simsspsel@8003c300 { | |
502 | reg = <0x8003c300 100>; | |
503 | status = "disabled"; | |
504 | }; | |
505 | ||
506 | simmemsel@8003c400 { | |
507 | reg = <0x8003c400 100>; | |
508 | status = "disabled"; | |
509 | }; | |
510 | ||
511 | gpiomon@8003c500 { | |
512 | reg = <0x8003c500 100>; | |
513 | status = "disabled"; | |
514 | }; | |
515 | ||
516 | simenet@8003c700 { | |
517 | reg = <0x8003c700 100>; | |
518 | status = "disabled"; | |
519 | }; | |
520 | ||
521 | armjtag@8003c800 { | |
522 | reg = <0x8003c800 100>; | |
523 | status = "disabled"; | |
524 | }; | |
525 | }; | |
526 | ||
527 | apbx@80040000 { | |
528 | compatible = "simple-bus"; | |
529 | #address-cells = <1>; | |
530 | #size-cells = <1>; | |
531 | reg = <0x80040000 0x40000>; | |
532 | ranges; | |
533 | ||
534 | clkctl@80040000 { | |
535 | reg = <0x80040000 2000>; | |
536 | status = "disabled"; | |
537 | }; | |
538 | ||
539 | saif0: saif@80042000 { | |
530f1d41 | 540 | compatible = "fsl,imx28-saif"; |
bc3a59c1 DA |
541 | reg = <0x80042000 2000>; |
542 | interrupts = <59 80>; | |
530f1d41 | 543 | fsl,saif-dma-channel = <4>; |
bc3a59c1 DA |
544 | status = "disabled"; |
545 | }; | |
546 | ||
547 | power@80044000 { | |
548 | reg = <0x80044000 2000>; | |
549 | status = "disabled"; | |
550 | }; | |
551 | ||
552 | saif1: saif@80046000 { | |
530f1d41 | 553 | compatible = "fsl,imx28-saif"; |
bc3a59c1 DA |
554 | reg = <0x80046000 2000>; |
555 | interrupts = <58 81>; | |
530f1d41 | 556 | fsl,saif-dma-channel = <5>; |
bc3a59c1 DA |
557 | status = "disabled"; |
558 | }; | |
559 | ||
560 | lradc@80050000 { | |
561 | reg = <0x80050000 2000>; | |
562 | status = "disabled"; | |
563 | }; | |
564 | ||
565 | spdif@80054000 { | |
566 | reg = <0x80054000 2000>; | |
567 | interrupts = <45 66>; | |
568 | status = "disabled"; | |
569 | }; | |
570 | ||
571 | rtc@80056000 { | |
f98c990c | 572 | compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; |
bc3a59c1 | 573 | reg = <0x80056000 2000>; |
f98c990c | 574 | interrupts = <29>; |
bc3a59c1 DA |
575 | }; |
576 | ||
577 | i2c0: i2c@80058000 { | |
2a96e391 SG |
578 | #address-cells = <1>; |
579 | #size-cells = <0>; | |
580 | compatible = "fsl,imx28-i2c"; | |
bc3a59c1 DA |
581 | reg = <0x80058000 2000>; |
582 | interrupts = <111 68>; | |
583 | status = "disabled"; | |
584 | }; | |
585 | ||
586 | i2c1: i2c@8005a000 { | |
2a96e391 SG |
587 | #address-cells = <1>; |
588 | #size-cells = <0>; | |
589 | compatible = "fsl,imx28-i2c"; | |
bc3a59c1 DA |
590 | reg = <0x8005a000 2000>; |
591 | interrupts = <110 69>; | |
592 | status = "disabled"; | |
593 | }; | |
594 | ||
52f7176b SG |
595 | pwm: pwm@80064000 { |
596 | compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; | |
bc3a59c1 | 597 | reg = <0x80064000 2000>; |
52f7176b SG |
598 | #pwm-cells = <2>; |
599 | fsl,pwm-number = <8>; | |
bc3a59c1 DA |
600 | status = "disabled"; |
601 | }; | |
602 | ||
603 | timrot@80068000 { | |
604 | reg = <0x80068000 2000>; | |
605 | status = "disabled"; | |
606 | }; | |
607 | ||
608 | auart0: serial@8006a000 { | |
80d969e4 | 609 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 DA |
610 | reg = <0x8006a000 0x2000>; |
611 | interrupts = <112 70 71>; | |
612 | status = "disabled"; | |
613 | }; | |
614 | ||
615 | auart1: serial@8006c000 { | |
80d969e4 | 616 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 DA |
617 | reg = <0x8006c000 0x2000>; |
618 | interrupts = <113 72 73>; | |
619 | status = "disabled"; | |
620 | }; | |
621 | ||
622 | auart2: serial@8006e000 { | |
80d969e4 | 623 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 DA |
624 | reg = <0x8006e000 0x2000>; |
625 | interrupts = <114 74 75>; | |
626 | status = "disabled"; | |
627 | }; | |
628 | ||
629 | auart3: serial@80070000 { | |
80d969e4 | 630 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 DA |
631 | reg = <0x80070000 0x2000>; |
632 | interrupts = <115 76 77>; | |
633 | status = "disabled"; | |
634 | }; | |
635 | ||
636 | auart4: serial@80072000 { | |
80d969e4 | 637 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 DA |
638 | reg = <0x80072000 0x2000>; |
639 | interrupts = <116 78 79>; | |
640 | status = "disabled"; | |
641 | }; | |
642 | ||
643 | duart: serial@80074000 { | |
644 | compatible = "arm,pl011", "arm,primecell"; | |
645 | reg = <0x80074000 0x1000>; | |
646 | interrupts = <47>; | |
647 | status = "disabled"; | |
648 | }; | |
649 | ||
650 | usbphy0: usbphy@8007c000 { | |
651 | reg = <0x8007c000 0x2000>; | |
652 | status = "disabled"; | |
653 | }; | |
654 | ||
655 | usbphy1: usbphy@8007e000 { | |
656 | reg = <0x8007e000 0x2000>; | |
657 | status = "disabled"; | |
658 | }; | |
659 | }; | |
660 | }; | |
661 | ||
662 | ahb@80080000 { | |
663 | compatible = "simple-bus"; | |
664 | #address-cells = <1>; | |
665 | #size-cells = <1>; | |
666 | reg = <0x80080000 0x80000>; | |
667 | ranges; | |
668 | ||
669 | usbctrl0: usbctrl@80080000 { | |
670 | reg = <0x80080000 0x10000>; | |
671 | status = "disabled"; | |
672 | }; | |
673 | ||
674 | usbctrl1: usbctrl@80090000 { | |
675 | reg = <0x80090000 0x10000>; | |
676 | status = "disabled"; | |
677 | }; | |
678 | ||
679 | dflpt@800c0000 { | |
680 | reg = <0x800c0000 0x10000>; | |
681 | status = "disabled"; | |
682 | }; | |
683 | ||
684 | mac0: ethernet@800f0000 { | |
685 | compatible = "fsl,imx28-fec"; | |
686 | reg = <0x800f0000 0x4000>; | |
687 | interrupts = <101>; | |
688 | status = "disabled"; | |
689 | }; | |
690 | ||
691 | mac1: ethernet@800f4000 { | |
692 | compatible = "fsl,imx28-fec"; | |
693 | reg = <0x800f4000 0x4000>; | |
694 | interrupts = <102>; | |
695 | status = "disabled"; | |
696 | }; | |
697 | ||
698 | switch@800f8000 { | |
699 | reg = <0x800f8000 0x8000>; | |
700 | status = "disabled"; | |
701 | }; | |
702 | ||
703 | }; | |
704 | }; |