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Commit | Line | Data |
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bc3a59c1 DA |
1 | /* |
2 | * Copyright 2012 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
25fc228e | 12 | #include <dt-bindings/gpio/gpio.h> |
bc3875f1 LW |
13 | #include "skeleton.dtsi" |
14 | #include "imx28-pinfunc.h" | |
bc3a59c1 DA |
15 | |
16 | / { | |
17 | interrupt-parent = <&icoll>; | |
18 | ||
ce4c6f9b | 19 | aliases { |
6bf6eb09 FE |
20 | ethernet0 = &mac0; |
21 | ethernet1 = &mac1; | |
ce4c6f9b SG |
22 | gpio0 = &gpio0; |
23 | gpio1 = &gpio1; | |
24 | gpio2 = &gpio2; | |
25 | gpio3 = &gpio3; | |
26 | gpio4 = &gpio4; | |
530f1d41 SG |
27 | saif0 = &saif0; |
28 | saif1 = &saif1; | |
80d969e4 FE |
29 | serial0 = &auart0; |
30 | serial1 = &auart1; | |
31 | serial2 = &auart2; | |
32 | serial3 = &auart3; | |
33 | serial4 = &auart4; | |
6bf6eb09 FE |
34 | spi0 = &ssp1; |
35 | spi1 = &ssp2; | |
1f35cc6a PC |
36 | usbphy0 = &usbphy0; |
37 | usbphy1 = &usbphy1; | |
ce4c6f9b SG |
38 | }; |
39 | ||
bc3a59c1 | 40 | cpus { |
7925e89f LP |
41 | #address-cells = <0>; |
42 | #size-cells = <0>; | |
43 | ||
44 | cpu { | |
45 | compatible = "arm,arm926ej-s"; | |
46 | device_type = "cpu"; | |
bc3a59c1 DA |
47 | }; |
48 | }; | |
49 | ||
50 | apb@80000000 { | |
51 | compatible = "simple-bus"; | |
52 | #address-cells = <1>; | |
53 | #size-cells = <1>; | |
54 | reg = <0x80000000 0x80000>; | |
55 | ranges; | |
56 | ||
57 | apbh@80000000 { | |
58 | compatible = "simple-bus"; | |
59 | #address-cells = <1>; | |
60 | #size-cells = <1>; | |
61 | reg = <0x80000000 0x3c900>; | |
62 | ranges; | |
63 | ||
64 | icoll: interrupt-controller@80000000 { | |
83a84efc | 65 | compatible = "fsl,imx28-icoll", "fsl,icoll"; |
bc3a59c1 DA |
66 | interrupt-controller; |
67 | #interrupt-cells = <1>; | |
68 | reg = <0x80000000 0x2000>; | |
69 | }; | |
70 | ||
296f8cd3 | 71 | hsadc: hsadc@80002000 { |
0f06cde7 | 72 | reg = <0x80002000 0x2000>; |
7f2b9288 | 73 | interrupts = <13>; |
f30fb03d SG |
74 | dmas = <&dma_apbh 12>; |
75 | dma-names = "rx"; | |
bc3a59c1 DA |
76 | status = "disabled"; |
77 | }; | |
78 | ||
f30fb03d | 79 | dma_apbh: dma-apbh@80004000 { |
84f3570a | 80 | compatible = "fsl,imx28-dma-apbh"; |
0f06cde7 | 81 | reg = <0x80004000 0x2000>; |
f30fb03d SG |
82 | interrupts = <82 83 84 85 |
83 | 88 88 88 88 | |
84 | 88 88 88 88 | |
85 | 87 86 0 0>; | |
86 | interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3", | |
87 | "gpmi0", "gmpi1", "gpmi2", "gmpi3", | |
88 | "gpmi4", "gmpi5", "gpmi6", "gmpi7", | |
89 | "hsadc", "lcdif", "empty", "empty"; | |
90 | #dma-cells = <1>; | |
91 | dma-channels = <16>; | |
b598b9f3 | 92 | clocks = <&clks 25>; |
bc3a59c1 DA |
93 | }; |
94 | ||
296f8cd3 | 95 | perfmon: perfmon@80006000 { |
0f06cde7 | 96 | reg = <0x80006000 0x800>; |
bc3a59c1 DA |
97 | interrupts = <27>; |
98 | status = "disabled"; | |
99 | }; | |
100 | ||
296f8cd3 | 101 | gpmi: gpmi-nand@8000c000 { |
7a8e5149 HS |
102 | compatible = "fsl,imx28-gpmi-nand"; |
103 | #address-cells = <1>; | |
104 | #size-cells = <1>; | |
0f06cde7 | 105 | reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; |
7a8e5149 | 106 | reg-names = "gpmi-nand", "bch"; |
7f2b9288 SG |
107 | interrupts = <41>; |
108 | interrupt-names = "bch"; | |
b598b9f3 | 109 | clocks = <&clks 50>; |
b6442559 | 110 | clock-names = "gpmi_io"; |
f30fb03d SG |
111 | dmas = <&dma_apbh 4>; |
112 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
113 | status = "disabled"; |
114 | }; | |
115 | ||
116 | ssp0: ssp@80010000 { | |
41bf5706 MR |
117 | #address-cells = <1>; |
118 | #size-cells = <0>; | |
0f06cde7 | 119 | reg = <0x80010000 0x2000>; |
7f2b9288 | 120 | interrupts = <96>; |
b598b9f3 | 121 | clocks = <&clks 46>; |
f30fb03d SG |
122 | dmas = <&dma_apbh 0>; |
123 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
124 | status = "disabled"; |
125 | }; | |
126 | ||
127 | ssp1: ssp@80012000 { | |
41bf5706 MR |
128 | #address-cells = <1>; |
129 | #size-cells = <0>; | |
0f06cde7 | 130 | reg = <0x80012000 0x2000>; |
7f2b9288 | 131 | interrupts = <97>; |
b598b9f3 | 132 | clocks = <&clks 47>; |
f30fb03d SG |
133 | dmas = <&dma_apbh 1>; |
134 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
135 | status = "disabled"; |
136 | }; | |
137 | ||
138 | ssp2: ssp@80014000 { | |
41bf5706 MR |
139 | #address-cells = <1>; |
140 | #size-cells = <0>; | |
0f06cde7 | 141 | reg = <0x80014000 0x2000>; |
7f2b9288 | 142 | interrupts = <98>; |
b598b9f3 | 143 | clocks = <&clks 48>; |
f30fb03d SG |
144 | dmas = <&dma_apbh 2>; |
145 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
146 | status = "disabled"; |
147 | }; | |
148 | ||
149 | ssp3: ssp@80016000 { | |
41bf5706 MR |
150 | #address-cells = <1>; |
151 | #size-cells = <0>; | |
0f06cde7 | 152 | reg = <0x80016000 0x2000>; |
7f2b9288 | 153 | interrupts = <99>; |
b598b9f3 | 154 | clocks = <&clks 49>; |
f30fb03d SG |
155 | dmas = <&dma_apbh 3>; |
156 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
157 | status = "disabled"; |
158 | }; | |
159 | ||
296f8cd3 | 160 | pinctrl: pinctrl@80018000 { |
bc3a59c1 DA |
161 | #address-cells = <1>; |
162 | #size-cells = <0>; | |
ce4c6f9b | 163 | compatible = "fsl,imx28-pinctrl", "simple-bus"; |
0f06cde7 | 164 | reg = <0x80018000 0x2000>; |
bc3a59c1 | 165 | |
ce4c6f9b SG |
166 | gpio0: gpio@0 { |
167 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
168 | interrupts = <127>; | |
169 | gpio-controller; | |
170 | #gpio-cells = <2>; | |
171 | interrupt-controller; | |
172 | #interrupt-cells = <2>; | |
173 | }; | |
174 | ||
175 | gpio1: gpio@1 { | |
176 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
177 | interrupts = <126>; | |
178 | gpio-controller; | |
179 | #gpio-cells = <2>; | |
180 | interrupt-controller; | |
181 | #interrupt-cells = <2>; | |
182 | }; | |
183 | ||
184 | gpio2: gpio@2 { | |
185 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
186 | interrupts = <125>; | |
187 | gpio-controller; | |
188 | #gpio-cells = <2>; | |
189 | interrupt-controller; | |
190 | #interrupt-cells = <2>; | |
191 | }; | |
192 | ||
193 | gpio3: gpio@3 { | |
194 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
195 | interrupts = <124>; | |
196 | gpio-controller; | |
197 | #gpio-cells = <2>; | |
198 | interrupt-controller; | |
199 | #interrupt-cells = <2>; | |
200 | }; | |
201 | ||
202 | gpio4: gpio@4 { | |
203 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
204 | interrupts = <123>; | |
205 | gpio-controller; | |
206 | #gpio-cells = <2>; | |
207 | interrupt-controller; | |
208 | #interrupt-cells = <2>; | |
209 | }; | |
210 | ||
bc3a59c1 DA |
211 | duart_pins_a: duart@0 { |
212 | reg = <0>; | |
f14da767 | 213 | fsl,pinmux-ids = < |
bc3875f1 LW |
214 | MX28_PAD_PWM0__DUART_RX |
215 | MX28_PAD_PWM1__DUART_TX | |
f14da767 | 216 | >; |
4191c340 LW |
217 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
218 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
219 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
bc3a59c1 DA |
220 | }; |
221 | ||
8385e7c1 MR |
222 | duart_pins_b: duart@1 { |
223 | reg = <1>; | |
f14da767 | 224 | fsl,pinmux-ids = < |
bc3875f1 LW |
225 | MX28_PAD_AUART0_CTS__DUART_RX |
226 | MX28_PAD_AUART0_RTS__DUART_TX | |
f14da767 | 227 | >; |
4191c340 LW |
228 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
229 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
230 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
8385e7c1 MR |
231 | }; |
232 | ||
e1a4d18f SG |
233 | duart_4pins_a: duart-4pins@0 { |
234 | reg = <0>; | |
235 | fsl,pinmux-ids = < | |
bc3875f1 LW |
236 | MX28_PAD_AUART0_CTS__DUART_RX |
237 | MX28_PAD_AUART0_RTS__DUART_TX | |
238 | MX28_PAD_AUART0_RX__DUART_CTS | |
239 | MX28_PAD_AUART0_TX__DUART_RTS | |
e1a4d18f | 240 | >; |
4191c340 LW |
241 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
242 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
243 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
e1a4d18f SG |
244 | }; |
245 | ||
7a8e5149 HS |
246 | gpmi_pins_a: gpmi-nand@0 { |
247 | reg = <0>; | |
f14da767 | 248 | fsl,pinmux-ids = < |
bc3875f1 LW |
249 | MX28_PAD_GPMI_D00__GPMI_D0 |
250 | MX28_PAD_GPMI_D01__GPMI_D1 | |
251 | MX28_PAD_GPMI_D02__GPMI_D2 | |
252 | MX28_PAD_GPMI_D03__GPMI_D3 | |
253 | MX28_PAD_GPMI_D04__GPMI_D4 | |
254 | MX28_PAD_GPMI_D05__GPMI_D5 | |
255 | MX28_PAD_GPMI_D06__GPMI_D6 | |
256 | MX28_PAD_GPMI_D07__GPMI_D7 | |
257 | MX28_PAD_GPMI_CE0N__GPMI_CE0N | |
258 | MX28_PAD_GPMI_RDY0__GPMI_READY0 | |
259 | MX28_PAD_GPMI_RDN__GPMI_RDN | |
260 | MX28_PAD_GPMI_WRN__GPMI_WRN | |
261 | MX28_PAD_GPMI_ALE__GPMI_ALE | |
262 | MX28_PAD_GPMI_CLE__GPMI_CLE | |
263 | MX28_PAD_GPMI_RESETN__GPMI_RESETN | |
f14da767 | 264 | >; |
4191c340 LW |
265 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
266 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
267 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
7a8e5149 HS |
268 | }; |
269 | ||
270 | gpmi_status_cfg: gpmi-status-cfg { | |
f14da767 | 271 | fsl,pinmux-ids = < |
bc3875f1 LW |
272 | MX28_PAD_GPMI_RDN__GPMI_RDN |
273 | MX28_PAD_GPMI_WRN__GPMI_WRN | |
274 | MX28_PAD_GPMI_RESETN__GPMI_RESETN | |
f14da767 | 275 | >; |
4191c340 | 276 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
7a8e5149 HS |
277 | }; |
278 | ||
80d969e4 FE |
279 | auart0_pins_a: auart0@0 { |
280 | reg = <0>; | |
f14da767 | 281 | fsl,pinmux-ids = < |
bc3875f1 LW |
282 | MX28_PAD_AUART0_RX__AUART0_RX |
283 | MX28_PAD_AUART0_TX__AUART0_TX | |
284 | MX28_PAD_AUART0_CTS__AUART0_CTS | |
285 | MX28_PAD_AUART0_RTS__AUART0_RTS | |
f14da767 | 286 | >; |
4191c340 LW |
287 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
288 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
289 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
8fa62e11 MV |
290 | }; |
291 | ||
292 | auart0_2pins_a: auart0-2pins@0 { | |
293 | reg = <0>; | |
294 | fsl,pinmux-ids = < | |
bc3875f1 LW |
295 | MX28_PAD_AUART0_RX__AUART0_RX |
296 | MX28_PAD_AUART0_TX__AUART0_TX | |
8fa62e11 | 297 | >; |
4191c340 LW |
298 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
299 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
300 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
80d969e4 FE |
301 | }; |
302 | ||
e1a4d18f SG |
303 | auart1_pins_a: auart1@0 { |
304 | reg = <0>; | |
305 | fsl,pinmux-ids = < | |
bc3875f1 LW |
306 | MX28_PAD_AUART1_RX__AUART1_RX |
307 | MX28_PAD_AUART1_TX__AUART1_TX | |
308 | MX28_PAD_AUART1_CTS__AUART1_CTS | |
309 | MX28_PAD_AUART1_RTS__AUART1_RTS | |
e1a4d18f | 310 | >; |
4191c340 LW |
311 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
312 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
313 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
e1a4d18f SG |
314 | }; |
315 | ||
3143bbb4 SG |
316 | auart1_2pins_a: auart1-2pins@0 { |
317 | reg = <0>; | |
318 | fsl,pinmux-ids = < | |
bc3875f1 LW |
319 | MX28_PAD_AUART1_RX__AUART1_RX |
320 | MX28_PAD_AUART1_TX__AUART1_TX | |
3143bbb4 | 321 | >; |
4191c340 LW |
322 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
323 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
324 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
3143bbb4 SG |
325 | }; |
326 | ||
327 | auart2_2pins_a: auart2-2pins@0 { | |
328 | reg = <0>; | |
329 | fsl,pinmux-ids = < | |
bc3875f1 LW |
330 | MX28_PAD_SSP2_SCK__AUART2_RX |
331 | MX28_PAD_SSP2_MOSI__AUART2_TX | |
3143bbb4 | 332 | >; |
4191c340 LW |
333 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
334 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
335 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
3143bbb4 SG |
336 | }; |
337 | ||
f8040cf5 EB |
338 | auart2_2pins_b: auart2-2pins@1 { |
339 | reg = <1>; | |
340 | fsl,pinmux-ids = < | |
bc3875f1 LW |
341 | MX28_PAD_AUART2_RX__AUART2_RX |
342 | MX28_PAD_AUART2_TX__AUART2_TX | |
f8040cf5 | 343 | >; |
4191c340 LW |
344 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
345 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
346 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
f8040cf5 EB |
347 | }; |
348 | ||
cd0214c3 AM |
349 | auart2_pins_a: auart2-pins@0 { |
350 | reg = <0>; | |
351 | fsl,pinmux-ids = < | |
352 | MX28_PAD_AUART2_RX__AUART2_RX | |
353 | MX28_PAD_AUART2_TX__AUART2_TX | |
354 | MX28_PAD_AUART2_CTS__AUART2_CTS | |
355 | MX28_PAD_AUART2_RTS__AUART2_RTS | |
356 | >; | |
357 | fsl,drive-strength = <MXS_DRIVE_4mA>; | |
358 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
359 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
360 | }; | |
361 | ||
80d969e4 FE |
362 | auart3_pins_a: auart3@0 { |
363 | reg = <0>; | |
f14da767 | 364 | fsl,pinmux-ids = < |
bc3875f1 LW |
365 | MX28_PAD_AUART3_RX__AUART3_RX |
366 | MX28_PAD_AUART3_TX__AUART3_TX | |
367 | MX28_PAD_AUART3_CTS__AUART3_CTS | |
368 | MX28_PAD_AUART3_RTS__AUART3_RTS | |
f14da767 | 369 | >; |
4191c340 LW |
370 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
371 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
372 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
80d969e4 FE |
373 | }; |
374 | ||
3143bbb4 SG |
375 | auart3_2pins_a: auart3-2pins@0 { |
376 | reg = <0>; | |
377 | fsl,pinmux-ids = < | |
bc3875f1 LW |
378 | MX28_PAD_SSP2_MISO__AUART3_RX |
379 | MX28_PAD_SSP2_SS0__AUART3_TX | |
3143bbb4 | 380 | >; |
4191c340 LW |
381 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
382 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
383 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
3143bbb4 SG |
384 | }; |
385 | ||
4812e746 EB |
386 | auart3_2pins_b: auart3-2pins@1 { |
387 | reg = <1>; | |
388 | fsl,pinmux-ids = < | |
bc3875f1 LW |
389 | MX28_PAD_AUART3_RX__AUART3_RX |
390 | MX28_PAD_AUART3_TX__AUART3_TX | |
4812e746 | 391 | >; |
4191c340 LW |
392 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
393 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
394 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
4812e746 EB |
395 | }; |
396 | ||
33678d12 EB |
397 | auart4_2pins_a: auart4@0 { |
398 | reg = <0>; | |
399 | fsl,pinmux-ids = < | |
bc3875f1 LW |
400 | MX28_PAD_SSP3_SCK__AUART4_TX |
401 | MX28_PAD_SSP3_MOSI__AUART4_RX | |
33678d12 | 402 | >; |
4191c340 LW |
403 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
404 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
405 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
33678d12 EB |
406 | }; |
407 | ||
bc3a59c1 DA |
408 | mac0_pins_a: mac0@0 { |
409 | reg = <0>; | |
f14da767 | 410 | fsl,pinmux-ids = < |
bc3875f1 LW |
411 | MX28_PAD_ENET0_MDC__ENET0_MDC |
412 | MX28_PAD_ENET0_MDIO__ENET0_MDIO | |
413 | MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | |
414 | MX28_PAD_ENET0_RXD0__ENET0_RXD0 | |
415 | MX28_PAD_ENET0_RXD1__ENET0_RXD1 | |
416 | MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | |
417 | MX28_PAD_ENET0_TXD0__ENET0_TXD0 | |
418 | MX28_PAD_ENET0_TXD1__ENET0_TXD1 | |
419 | MX28_PAD_ENET_CLK__CLKCTRL_ENET | |
f14da767 | 420 | >; |
4191c340 LW |
421 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
422 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
423 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
bc3a59c1 DA |
424 | }; |
425 | ||
426 | mac1_pins_a: mac1@0 { | |
427 | reg = <0>; | |
f14da767 | 428 | fsl,pinmux-ids = < |
bc3875f1 LW |
429 | MX28_PAD_ENET0_CRS__ENET1_RX_EN |
430 | MX28_PAD_ENET0_RXD2__ENET1_RXD0 | |
431 | MX28_PAD_ENET0_RXD3__ENET1_RXD1 | |
432 | MX28_PAD_ENET0_COL__ENET1_TX_EN | |
433 | MX28_PAD_ENET0_TXD2__ENET1_TXD0 | |
434 | MX28_PAD_ENET0_TXD3__ENET1_TXD1 | |
f14da767 | 435 | >; |
4191c340 LW |
436 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
437 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
438 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
bc3a59c1 | 439 | }; |
35d23047 SG |
440 | |
441 | mmc0_8bit_pins_a: mmc0-8bit@0 { | |
442 | reg = <0>; | |
f14da767 | 443 | fsl,pinmux-ids = < |
bc3875f1 LW |
444 | MX28_PAD_SSP0_DATA0__SSP0_D0 |
445 | MX28_PAD_SSP0_DATA1__SSP0_D1 | |
446 | MX28_PAD_SSP0_DATA2__SSP0_D2 | |
447 | MX28_PAD_SSP0_DATA3__SSP0_D3 | |
448 | MX28_PAD_SSP0_DATA4__SSP0_D4 | |
449 | MX28_PAD_SSP0_DATA5__SSP0_D5 | |
450 | MX28_PAD_SSP0_DATA6__SSP0_D6 | |
451 | MX28_PAD_SSP0_DATA7__SSP0_D7 | |
452 | MX28_PAD_SSP0_CMD__SSP0_CMD | |
453 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | |
454 | MX28_PAD_SSP0_SCK__SSP0_SCK | |
f14da767 | 455 | >; |
4191c340 LW |
456 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
457 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
458 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
35d23047 SG |
459 | }; |
460 | ||
8385e7c1 MR |
461 | mmc0_4bit_pins_a: mmc0-4bit@0 { |
462 | reg = <0>; | |
f14da767 | 463 | fsl,pinmux-ids = < |
bc3875f1 LW |
464 | MX28_PAD_SSP0_DATA0__SSP0_D0 |
465 | MX28_PAD_SSP0_DATA1__SSP0_D1 | |
466 | MX28_PAD_SSP0_DATA2__SSP0_D2 | |
467 | MX28_PAD_SSP0_DATA3__SSP0_D3 | |
468 | MX28_PAD_SSP0_CMD__SSP0_CMD | |
469 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | |
470 | MX28_PAD_SSP0_SCK__SSP0_SCK | |
f14da767 | 471 | >; |
4191c340 LW |
472 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
473 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
474 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
8385e7c1 MR |
475 | }; |
476 | ||
35d23047 | 477 | mmc0_cd_cfg: mmc0-cd-cfg { |
f14da767 | 478 | fsl,pinmux-ids = < |
bc3875f1 | 479 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
f14da767 | 480 | >; |
4191c340 | 481 | fsl,pull-up = <MXS_PULL_DISABLE>; |
35d23047 SG |
482 | }; |
483 | ||
484 | mmc0_sck_cfg: mmc0-sck-cfg { | |
f14da767 | 485 | fsl,pinmux-ids = < |
bc3875f1 | 486 | MX28_PAD_SSP0_SCK__SSP0_SCK |
f14da767 | 487 | >; |
4191c340 LW |
488 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
489 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
35d23047 | 490 | }; |
2a96e391 | 491 | |
77d6386b MKB |
492 | mmc1_4bit_pins_a: mmc1-4bit@0 { |
493 | reg = <0>; | |
494 | fsl,pinmux-ids = < | |
495 | MX28_PAD_GPMI_D00__SSP1_D0 | |
496 | MX28_PAD_GPMI_D01__SSP1_D1 | |
497 | MX28_PAD_GPMI_D02__SSP1_D2 | |
498 | MX28_PAD_GPMI_D03__SSP1_D3 | |
499 | MX28_PAD_GPMI_RDY1__SSP1_CMD | |
500 | MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | |
501 | MX28_PAD_GPMI_WRN__SSP1_SCK | |
502 | >; | |
503 | fsl,drive-strength = <MXS_DRIVE_8mA>; | |
504 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
505 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
506 | }; | |
507 | ||
508 | mmc1_cd_cfg: mmc1-cd-cfg { | |
509 | fsl,pinmux-ids = < | |
510 | MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | |
511 | >; | |
512 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
513 | }; | |
514 | ||
515 | mmc1_sck_cfg: mmc1-sck-cfg { | |
516 | fsl,pinmux-ids = < | |
517 | MX28_PAD_GPMI_WRN__SSP1_SCK | |
518 | >; | |
519 | fsl,drive-strength = <MXS_DRIVE_12mA>; | |
520 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
521 | }; | |
522 | ||
523 | ||
5550e8e9 MV |
524 | mmc2_4bit_pins_a: mmc2-4bit@0 { |
525 | reg = <0>; | |
526 | fsl,pinmux-ids = < | |
527 | MX28_PAD_SSP0_DATA4__SSP2_D0 | |
528 | MX28_PAD_SSP1_SCK__SSP2_D1 | |
529 | MX28_PAD_SSP1_CMD__SSP2_D2 | |
530 | MX28_PAD_SSP0_DATA5__SSP2_D3 | |
531 | MX28_PAD_SSP0_DATA6__SSP2_CMD | |
532 | MX28_PAD_AUART1_RX__SSP2_CARD_DETECT | |
533 | MX28_PAD_SSP0_DATA7__SSP2_SCK | |
534 | >; | |
535 | fsl,drive-strength = <MXS_DRIVE_8mA>; | |
536 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
537 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
538 | }; | |
539 | ||
540 | mmc2_cd_cfg: mmc2-cd-cfg { | |
541 | fsl,pinmux-ids = < | |
542 | MX28_PAD_AUART1_RX__SSP2_CARD_DETECT | |
543 | >; | |
544 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
545 | }; | |
546 | ||
547 | mmc2_sck_cfg: mmc2-sck-cfg { | |
548 | fsl,pinmux-ids = < | |
549 | MX28_PAD_SSP0_DATA7__SSP2_SCK | |
550 | >; | |
551 | fsl,drive-strength = <MXS_DRIVE_12mA>; | |
552 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
35d23047 | 553 | }; |
2a96e391 SG |
554 | |
555 | i2c0_pins_a: i2c0@0 { | |
556 | reg = <0>; | |
f14da767 | 557 | fsl,pinmux-ids = < |
bc3875f1 LW |
558 | MX28_PAD_I2C0_SCL__I2C0_SCL |
559 | MX28_PAD_I2C0_SDA__I2C0_SDA | |
f14da767 | 560 | >; |
4191c340 LW |
561 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
562 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
563 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
2a96e391 | 564 | }; |
530f1d41 | 565 | |
5c697ea2 MR |
566 | i2c0_pins_b: i2c0@1 { |
567 | reg = <1>; | |
568 | fsl,pinmux-ids = < | |
bc3875f1 LW |
569 | MX28_PAD_AUART0_RX__I2C0_SCL |
570 | MX28_PAD_AUART0_TX__I2C0_SDA | |
5c697ea2 | 571 | >; |
4191c340 LW |
572 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
573 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
574 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
5c697ea2 MR |
575 | }; |
576 | ||
de7e934f MR |
577 | i2c1_pins_a: i2c1@0 { |
578 | reg = <0>; | |
579 | fsl,pinmux-ids = < | |
bc3875f1 LW |
580 | MX28_PAD_PWM0__I2C1_SCL |
581 | MX28_PAD_PWM1__I2C1_SDA | |
de7e934f | 582 | >; |
4191c340 LW |
583 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
584 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
585 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
de7e934f MR |
586 | }; |
587 | ||
530f1d41 SG |
588 | saif0_pins_a: saif0@0 { |
589 | reg = <0>; | |
f14da767 | 590 | fsl,pinmux-ids = < |
bc3875f1 LW |
591 | MX28_PAD_SAIF0_MCLK__SAIF0_MCLK |
592 | MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK | |
593 | MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK | |
594 | MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 | |
f14da767 | 595 | >; |
4191c340 LW |
596 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
597 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
598 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
530f1d41 SG |
599 | }; |
600 | ||
2e1dd9fc LW |
601 | saif0_pins_b: saif0@1 { |
602 | reg = <1>; | |
603 | fsl,pinmux-ids = < | |
bc3875f1 LW |
604 | MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK |
605 | MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK | |
606 | MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 | |
2e1dd9fc | 607 | >; |
4191c340 LW |
608 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
609 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
610 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
2e1dd9fc LW |
611 | }; |
612 | ||
530f1d41 SG |
613 | saif1_pins_a: saif1@0 { |
614 | reg = <0>; | |
f14da767 | 615 | fsl,pinmux-ids = < |
bc3875f1 | 616 | MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
f14da767 | 617 | >; |
4191c340 LW |
618 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
619 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
620 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
530f1d41 | 621 | }; |
52f7176b | 622 | |
e1a4d18f SG |
623 | pwm0_pins_a: pwm0@0 { |
624 | reg = <0>; | |
625 | fsl,pinmux-ids = < | |
bc3875f1 | 626 | MX28_PAD_PWM0__PWM_0 |
e1a4d18f | 627 | >; |
4191c340 LW |
628 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
629 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
630 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
e1a4d18f SG |
631 | }; |
632 | ||
52f7176b SG |
633 | pwm2_pins_a: pwm2@0 { |
634 | reg = <0>; | |
635 | fsl,pinmux-ids = < | |
bc3875f1 | 636 | MX28_PAD_PWM2__PWM_2 |
52f7176b | 637 | >; |
4191c340 LW |
638 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
639 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
640 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
52f7176b | 641 | }; |
a915ee42 | 642 | |
2bde51cb JB |
643 | pwm3_pins_a: pwm3@0 { |
644 | reg = <0>; | |
645 | fsl,pinmux-ids = < | |
bc3875f1 | 646 | MX28_PAD_PWM3__PWM_3 |
2bde51cb | 647 | >; |
4191c340 LW |
648 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
649 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
650 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
2bde51cb JB |
651 | }; |
652 | ||
d248620c MR |
653 | pwm3_pins_b: pwm3@1 { |
654 | reg = <1>; | |
655 | fsl,pinmux-ids = < | |
bc3875f1 | 656 | MX28_PAD_SAIF0_MCLK__PWM_3 |
d248620c | 657 | >; |
4191c340 LW |
658 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
659 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
660 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
d248620c MR |
661 | }; |
662 | ||
2f44211f MR |
663 | pwm4_pins_a: pwm4@0 { |
664 | reg = <0>; | |
665 | fsl,pinmux-ids = < | |
bc3875f1 | 666 | MX28_PAD_PWM4__PWM_4 |
2f44211f | 667 | >; |
4191c340 LW |
668 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
669 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
670 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
2f44211f MR |
671 | }; |
672 | ||
a915ee42 SG |
673 | lcdif_24bit_pins_a: lcdif-24bit@0 { |
674 | reg = <0>; | |
675 | fsl,pinmux-ids = < | |
bc3875f1 LW |
676 | MX28_PAD_LCD_D00__LCD_D0 |
677 | MX28_PAD_LCD_D01__LCD_D1 | |
678 | MX28_PAD_LCD_D02__LCD_D2 | |
679 | MX28_PAD_LCD_D03__LCD_D3 | |
680 | MX28_PAD_LCD_D04__LCD_D4 | |
681 | MX28_PAD_LCD_D05__LCD_D5 | |
682 | MX28_PAD_LCD_D06__LCD_D6 | |
683 | MX28_PAD_LCD_D07__LCD_D7 | |
684 | MX28_PAD_LCD_D08__LCD_D8 | |
685 | MX28_PAD_LCD_D09__LCD_D9 | |
686 | MX28_PAD_LCD_D10__LCD_D10 | |
687 | MX28_PAD_LCD_D11__LCD_D11 | |
688 | MX28_PAD_LCD_D12__LCD_D12 | |
689 | MX28_PAD_LCD_D13__LCD_D13 | |
690 | MX28_PAD_LCD_D14__LCD_D14 | |
691 | MX28_PAD_LCD_D15__LCD_D15 | |
692 | MX28_PAD_LCD_D16__LCD_D16 | |
693 | MX28_PAD_LCD_D17__LCD_D17 | |
694 | MX28_PAD_LCD_D18__LCD_D18 | |
695 | MX28_PAD_LCD_D19__LCD_D19 | |
696 | MX28_PAD_LCD_D20__LCD_D20 | |
697 | MX28_PAD_LCD_D21__LCD_D21 | |
698 | MX28_PAD_LCD_D22__LCD_D22 | |
699 | MX28_PAD_LCD_D23__LCD_D23 | |
a915ee42 | 700 | >; |
4191c340 LW |
701 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
702 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
703 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
a915ee42 | 704 | }; |
6ca44acf | 705 | |
ec985eb2 DC |
706 | lcdif_18bit_pins_a: lcdif-18bit@0 { |
707 | reg = <0>; | |
708 | fsl,pinmux-ids = < | |
709 | MX28_PAD_LCD_D00__LCD_D0 | |
710 | MX28_PAD_LCD_D01__LCD_D1 | |
711 | MX28_PAD_LCD_D02__LCD_D2 | |
712 | MX28_PAD_LCD_D03__LCD_D3 | |
713 | MX28_PAD_LCD_D04__LCD_D4 | |
714 | MX28_PAD_LCD_D05__LCD_D5 | |
715 | MX28_PAD_LCD_D06__LCD_D6 | |
716 | MX28_PAD_LCD_D07__LCD_D7 | |
717 | MX28_PAD_LCD_D08__LCD_D8 | |
718 | MX28_PAD_LCD_D09__LCD_D9 | |
719 | MX28_PAD_LCD_D10__LCD_D10 | |
720 | MX28_PAD_LCD_D11__LCD_D11 | |
721 | MX28_PAD_LCD_D12__LCD_D12 | |
722 | MX28_PAD_LCD_D13__LCD_D13 | |
723 | MX28_PAD_LCD_D14__LCD_D14 | |
724 | MX28_PAD_LCD_D15__LCD_D15 | |
725 | MX28_PAD_LCD_D16__LCD_D16 | |
726 | MX28_PAD_LCD_D17__LCD_D17 | |
727 | >; | |
728 | fsl,drive-strength = <MXS_DRIVE_4mA>; | |
729 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
730 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
731 | }; | |
732 | ||
4ced2a40 GGM |
733 | lcdif_16bit_pins_a: lcdif-16bit@0 { |
734 | reg = <0>; | |
735 | fsl,pinmux-ids = < | |
bc3875f1 LW |
736 | MX28_PAD_LCD_D00__LCD_D0 |
737 | MX28_PAD_LCD_D01__LCD_D1 | |
738 | MX28_PAD_LCD_D02__LCD_D2 | |
739 | MX28_PAD_LCD_D03__LCD_D3 | |
740 | MX28_PAD_LCD_D04__LCD_D4 | |
741 | MX28_PAD_LCD_D05__LCD_D5 | |
742 | MX28_PAD_LCD_D06__LCD_D6 | |
743 | MX28_PAD_LCD_D07__LCD_D7 | |
744 | MX28_PAD_LCD_D08__LCD_D8 | |
745 | MX28_PAD_LCD_D09__LCD_D9 | |
746 | MX28_PAD_LCD_D10__LCD_D10 | |
747 | MX28_PAD_LCD_D11__LCD_D11 | |
748 | MX28_PAD_LCD_D12__LCD_D12 | |
749 | MX28_PAD_LCD_D13__LCD_D13 | |
750 | MX28_PAD_LCD_D14__LCD_D14 | |
751 | MX28_PAD_LCD_D15__LCD_D15 | |
4ced2a40 | 752 | >; |
4191c340 LW |
753 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
754 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
755 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
4ced2a40 GGM |
756 | }; |
757 | ||
23ad6f65 LW |
758 | lcdif_sync_pins_a: lcdif-sync@0 { |
759 | reg = <0>; | |
760 | fsl,pinmux-ids = < | |
bc3875f1 LW |
761 | MX28_PAD_LCD_RS__LCD_DOTCLK |
762 | MX28_PAD_LCD_CS__LCD_ENABLE | |
763 | MX28_PAD_LCD_RD_E__LCD_VSYNC | |
764 | MX28_PAD_LCD_WR_RWN__LCD_HSYNC | |
23ad6f65 | 765 | >; |
4191c340 LW |
766 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
767 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
768 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
23ad6f65 LW |
769 | }; |
770 | ||
6ca44acf SG |
771 | can0_pins_a: can0@0 { |
772 | reg = <0>; | |
773 | fsl,pinmux-ids = < | |
bc3875f1 LW |
774 | MX28_PAD_GPMI_RDY2__CAN0_TX |
775 | MX28_PAD_GPMI_RDY3__CAN0_RX | |
6ca44acf | 776 | >; |
4191c340 LW |
777 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
778 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
779 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
6ca44acf SG |
780 | }; |
781 | ||
782 | can1_pins_a: can1@0 { | |
783 | reg = <0>; | |
784 | fsl,pinmux-ids = < | |
bc3875f1 LW |
785 | MX28_PAD_GPMI_CE2N__CAN1_TX |
786 | MX28_PAD_GPMI_CE3N__CAN1_RX | |
6ca44acf | 787 | >; |
4191c340 LW |
788 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
789 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
790 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
6ca44acf | 791 | }; |
7f122213 MV |
792 | |
793 | spi2_pins_a: spi2@0 { | |
794 | reg = <0>; | |
795 | fsl,pinmux-ids = < | |
bc3875f1 LW |
796 | MX28_PAD_SSP2_SCK__SSP2_SCK |
797 | MX28_PAD_SSP2_MOSI__SSP2_CMD | |
798 | MX28_PAD_SSP2_MISO__SSP2_D0 | |
799 | MX28_PAD_SSP2_SS0__SSP2_D3 | |
7f122213 | 800 | >; |
4191c340 LW |
801 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
802 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
803 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
7f122213 | 804 | }; |
bb2f1261 | 805 | |
3314d2be LW |
806 | spi3_pins_a: spi3@0 { |
807 | reg = <0>; | |
808 | fsl,pinmux-ids = < | |
bc3875f1 LW |
809 | MX28_PAD_AUART2_RX__SSP3_D4 |
810 | MX28_PAD_AUART2_TX__SSP3_D5 | |
811 | MX28_PAD_SSP3_SCK__SSP3_SCK | |
812 | MX28_PAD_SSP3_MOSI__SSP3_CMD | |
813 | MX28_PAD_SSP3_MISO__SSP3_D0 | |
814 | MX28_PAD_SSP3_SS0__SSP3_D3 | |
3314d2be | 815 | >; |
4191c340 LW |
816 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
817 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
818 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
3314d2be LW |
819 | }; |
820 | ||
c8e42bc9 | 821 | usb0_pins_a: usb0@0 { |
bb2f1261 MV |
822 | reg = <0>; |
823 | fsl,pinmux-ids = < | |
bc3875f1 | 824 | MX28_PAD_SSP2_SS2__USB0_OVERCURRENT |
bb2f1261 | 825 | >; |
4191c340 LW |
826 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
827 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
828 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
bb2f1261 MV |
829 | }; |
830 | ||
c8e42bc9 | 831 | usb0_pins_b: usb0@1 { |
bb2f1261 MV |
832 | reg = <1>; |
833 | fsl,pinmux-ids = < | |
bc3875f1 | 834 | MX28_PAD_AUART1_CTS__USB0_OVERCURRENT |
bb2f1261 | 835 | >; |
4191c340 LW |
836 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
837 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
838 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
bb2f1261 MV |
839 | }; |
840 | ||
c8e42bc9 | 841 | usb1_pins_a: usb1@0 { |
bb2f1261 MV |
842 | reg = <0>; |
843 | fsl,pinmux-ids = < | |
bc3875f1 | 844 | MX28_PAD_SSP2_SS1__USB1_OVERCURRENT |
bb2f1261 | 845 | >; |
4191c340 LW |
846 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
847 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
848 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
bb2f1261 | 849 | }; |
69c02f95 FE |
850 | |
851 | usb0_id_pins_a: usb0id@0 { | |
852 | reg = <0>; | |
853 | fsl,pinmux-ids = < | |
e96e1782 | 854 | MX28_PAD_AUART1_RTS__USB0_ID |
bb2f1261 | 855 | >; |
e96e1782 LW |
856 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
857 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
858 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
bb2f1261 | 859 | }; |
bb89b8d2 DC |
860 | |
861 | usb0_id_pins_b: usb0id1@0 { | |
862 | reg = <0>; | |
863 | fsl,pinmux-ids = < | |
864 | MX28_PAD_PWM2__USB0_ID | |
865 | >; | |
866 | fsl,drive-strength = <MXS_DRIVE_12mA>; | |
867 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
868 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
869 | }; | |
870 | ||
bc3a59c1 DA |
871 | }; |
872 | ||
296f8cd3 | 873 | digctl: digctl@8001c000 { |
115581cf | 874 | compatible = "fsl,imx28-digctl", "fsl,imx23-digctl"; |
0f06cde7 | 875 | reg = <0x8001c000 0x2000>; |
bc3a59c1 DA |
876 | interrupts = <89>; |
877 | status = "disabled"; | |
878 | }; | |
879 | ||
296f8cd3 | 880 | etm: etm@80022000 { |
0f06cde7 | 881 | reg = <0x80022000 0x2000>; |
bc3a59c1 DA |
882 | status = "disabled"; |
883 | }; | |
884 | ||
f30fb03d | 885 | dma_apbx: dma-apbx@80024000 { |
84f3570a | 886 | compatible = "fsl,imx28-dma-apbx"; |
0f06cde7 | 887 | reg = <0x80024000 0x2000>; |
f30fb03d SG |
888 | interrupts = <78 79 66 0 |
889 | 80 81 68 69 | |
890 | 70 71 72 73 | |
891 | 74 75 76 77>; | |
892 | interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty", | |
893 | "saif0", "saif1", "i2c0", "i2c1", | |
894 | "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", | |
895 | "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; | |
896 | #dma-cells = <1>; | |
897 | dma-channels = <16>; | |
b598b9f3 | 898 | clocks = <&clks 26>; |
bc3a59c1 DA |
899 | }; |
900 | ||
296f8cd3 | 901 | dcp: dcp@80028000 { |
7d56a28f | 902 | compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; |
0f06cde7 | 903 | reg = <0x80028000 0x2000>; |
bc3a59c1 | 904 | interrupts = <52 53 54>; |
7d56a28f | 905 | status = "okay"; |
bc3a59c1 DA |
906 | }; |
907 | ||
296f8cd3 | 908 | pxp: pxp@8002a000 { |
0f06cde7 | 909 | reg = <0x8002a000 0x2000>; |
bc3a59c1 DA |
910 | interrupts = <39>; |
911 | status = "disabled"; | |
912 | }; | |
913 | ||
296f8cd3 | 914 | ocotp: ocotp@8002c000 { |
69d75a02 | 915 | compatible = "fsl,ocotp"; |
0f06cde7 | 916 | reg = <0x8002c000 0x2000>; |
bc3a59c1 DA |
917 | status = "disabled"; |
918 | }; | |
919 | ||
920 | axi-ahb@8002e000 { | |
0f06cde7 | 921 | reg = <0x8002e000 0x2000>; |
bc3a59c1 DA |
922 | status = "disabled"; |
923 | }; | |
924 | ||
296f8cd3 | 925 | lcdif: lcdif@80030000 { |
a915ee42 | 926 | compatible = "fsl,imx28-lcdif"; |
0f06cde7 | 927 | reg = <0x80030000 0x2000>; |
7f2b9288 | 928 | interrupts = <38>; |
b598b9f3 | 929 | clocks = <&clks 55>; |
f30fb03d SG |
930 | dmas = <&dma_apbh 13>; |
931 | dma-names = "rx"; | |
bc3a59c1 DA |
932 | status = "disabled"; |
933 | }; | |
934 | ||
935 | can0: can@80032000 { | |
6ca44acf | 936 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; |
0f06cde7 | 937 | reg = <0x80032000 0x2000>; |
bc3a59c1 | 938 | interrupts = <8>; |
b598b9f3 SG |
939 | clocks = <&clks 58>, <&clks 58>; |
940 | clock-names = "ipg", "per"; | |
bc3a59c1 DA |
941 | status = "disabled"; |
942 | }; | |
943 | ||
944 | can1: can@80034000 { | |
6ca44acf | 945 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; |
0f06cde7 | 946 | reg = <0x80034000 0x2000>; |
bc3a59c1 | 947 | interrupts = <9>; |
b598b9f3 SG |
948 | clocks = <&clks 59>, <&clks 59>; |
949 | clock-names = "ipg", "per"; | |
bc3a59c1 DA |
950 | status = "disabled"; |
951 | }; | |
952 | ||
296f8cd3 | 953 | simdbg: simdbg@8003c000 { |
0f06cde7 | 954 | reg = <0x8003c000 0x200>; |
bc3a59c1 DA |
955 | status = "disabled"; |
956 | }; | |
957 | ||
296f8cd3 | 958 | simgpmisel: simgpmisel@8003c200 { |
0f06cde7 | 959 | reg = <0x8003c200 0x100>; |
bc3a59c1 DA |
960 | status = "disabled"; |
961 | }; | |
962 | ||
296f8cd3 | 963 | simsspsel: simsspsel@8003c300 { |
0f06cde7 | 964 | reg = <0x8003c300 0x100>; |
bc3a59c1 DA |
965 | status = "disabled"; |
966 | }; | |
967 | ||
296f8cd3 | 968 | simmemsel: simmemsel@8003c400 { |
0f06cde7 | 969 | reg = <0x8003c400 0x100>; |
bc3a59c1 DA |
970 | status = "disabled"; |
971 | }; | |
972 | ||
296f8cd3 | 973 | gpiomon: gpiomon@8003c500 { |
0f06cde7 | 974 | reg = <0x8003c500 0x100>; |
bc3a59c1 DA |
975 | status = "disabled"; |
976 | }; | |
977 | ||
296f8cd3 | 978 | simenet: simenet@8003c700 { |
0f06cde7 | 979 | reg = <0x8003c700 0x100>; |
bc3a59c1 DA |
980 | status = "disabled"; |
981 | }; | |
982 | ||
296f8cd3 | 983 | armjtag: armjtag@8003c800 { |
0f06cde7 | 984 | reg = <0x8003c800 0x100>; |
bc3a59c1 DA |
985 | status = "disabled"; |
986 | }; | |
07a3ce7f | 987 | }; |
bc3a59c1 DA |
988 | |
989 | apbx@80040000 { | |
990 | compatible = "simple-bus"; | |
991 | #address-cells = <1>; | |
992 | #size-cells = <1>; | |
993 | reg = <0x80040000 0x40000>; | |
994 | ranges; | |
995 | ||
b598b9f3 | 996 | clks: clkctrl@80040000 { |
8f7cf881 | 997 | compatible = "fsl,imx28-clkctrl", "fsl,clkctrl"; |
0f06cde7 | 998 | reg = <0x80040000 0x2000>; |
b598b9f3 | 999 | #clock-cells = <1>; |
bc3a59c1 DA |
1000 | }; |
1001 | ||
1002 | saif0: saif@80042000 { | |
530f1d41 | 1003 | compatible = "fsl,imx28-saif"; |
0f06cde7 | 1004 | reg = <0x80042000 0x2000>; |
7f2b9288 | 1005 | interrupts = <59>; |
66acaf3f | 1006 | #clock-cells = <0>; |
b598b9f3 | 1007 | clocks = <&clks 53>; |
f30fb03d SG |
1008 | dmas = <&dma_apbx 4>; |
1009 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
1010 | status = "disabled"; |
1011 | }; | |
1012 | ||
296f8cd3 | 1013 | power: power@80044000 { |
0f06cde7 | 1014 | reg = <0x80044000 0x2000>; |
bc3a59c1 DA |
1015 | status = "disabled"; |
1016 | }; | |
1017 | ||
1018 | saif1: saif@80046000 { | |
530f1d41 | 1019 | compatible = "fsl,imx28-saif"; |
0f06cde7 | 1020 | reg = <0x80046000 0x2000>; |
7f2b9288 | 1021 | interrupts = <58>; |
b598b9f3 | 1022 | clocks = <&clks 54>; |
f30fb03d SG |
1023 | dmas = <&dma_apbx 5>; |
1024 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
1025 | status = "disabled"; |
1026 | }; | |
1027 | ||
296f8cd3 | 1028 | lradc: lradc@80050000 { |
aef35104 | 1029 | compatible = "fsl,imx28-lradc"; |
0f06cde7 | 1030 | reg = <0x80050000 0x2000>; |
aef35104 MV |
1031 | interrupts = <10 14 15 16 17 18 19 |
1032 | 20 21 22 23 24 25>; | |
bc3a59c1 | 1033 | status = "disabled"; |
18da755d | 1034 | clocks = <&clks 41>; |
40dde681 | 1035 | #io-channel-cells = <1>; |
bc3a59c1 DA |
1036 | }; |
1037 | ||
296f8cd3 | 1038 | spdif: spdif@80054000 { |
0f06cde7 | 1039 | reg = <0x80054000 0x2000>; |
7f2b9288 | 1040 | interrupts = <45>; |
f30fb03d SG |
1041 | dmas = <&dma_apbx 2>; |
1042 | dma-names = "tx"; | |
bc3a59c1 DA |
1043 | status = "disabled"; |
1044 | }; | |
1045 | ||
296f8cd3 | 1046 | mxs_rtc: rtc@80056000 { |
f98c990c | 1047 | compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; |
0f06cde7 | 1048 | reg = <0x80056000 0x2000>; |
f98c990c | 1049 | interrupts = <29>; |
bc3a59c1 DA |
1050 | }; |
1051 | ||
1052 | i2c0: i2c@80058000 { | |
2a96e391 SG |
1053 | #address-cells = <1>; |
1054 | #size-cells = <0>; | |
1055 | compatible = "fsl,imx28-i2c"; | |
0f06cde7 | 1056 | reg = <0x80058000 0x2000>; |
7f2b9288 | 1057 | interrupts = <111>; |
cd4f2d4a | 1058 | clock-frequency = <100000>; |
f30fb03d SG |
1059 | dmas = <&dma_apbx 6>; |
1060 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
1061 | status = "disabled"; |
1062 | }; | |
1063 | ||
1064 | i2c1: i2c@8005a000 { | |
2a96e391 SG |
1065 | #address-cells = <1>; |
1066 | #size-cells = <0>; | |
1067 | compatible = "fsl,imx28-i2c"; | |
0f06cde7 | 1068 | reg = <0x8005a000 0x2000>; |
7f2b9288 | 1069 | interrupts = <110>; |
cd4f2d4a | 1070 | clock-frequency = <100000>; |
f30fb03d SG |
1071 | dmas = <&dma_apbx 7>; |
1072 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
1073 | status = "disabled"; |
1074 | }; | |
1075 | ||
52f7176b SG |
1076 | pwm: pwm@80064000 { |
1077 | compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; | |
0f06cde7 | 1078 | reg = <0x80064000 0x2000>; |
b598b9f3 | 1079 | clocks = <&clks 44>; |
52f7176b SG |
1080 | #pwm-cells = <2>; |
1081 | fsl,pwm-number = <8>; | |
bc3a59c1 DA |
1082 | status = "disabled"; |
1083 | }; | |
1084 | ||
296f8cd3 | 1085 | timer: timrot@80068000 { |
eeca6e60 | 1086 | compatible = "fsl,imx28-timrot", "fsl,timrot"; |
0f06cde7 | 1087 | reg = <0x80068000 0x2000>; |
eeca6e60 | 1088 | interrupts = <48 49 50 51>; |
2efb9504 | 1089 | clocks = <&clks 26>; |
bc3a59c1 DA |
1090 | }; |
1091 | ||
1092 | auart0: serial@8006a000 { | |
80d969e4 | 1093 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 | 1094 | reg = <0x8006a000 0x2000>; |
7f2b9288 | 1095 | interrupts = <112>; |
f30fb03d SG |
1096 | dmas = <&dma_apbx 8>, <&dma_apbx 9>; |
1097 | dma-names = "rx", "tx"; | |
b598b9f3 | 1098 | clocks = <&clks 45>; |
bc3a59c1 DA |
1099 | status = "disabled"; |
1100 | }; | |
1101 | ||
1102 | auart1: serial@8006c000 { | |
80d969e4 | 1103 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 | 1104 | reg = <0x8006c000 0x2000>; |
7f2b9288 | 1105 | interrupts = <113>; |
f30fb03d SG |
1106 | dmas = <&dma_apbx 10>, <&dma_apbx 11>; |
1107 | dma-names = "rx", "tx"; | |
b598b9f3 | 1108 | clocks = <&clks 45>; |
bc3a59c1 DA |
1109 | status = "disabled"; |
1110 | }; | |
1111 | ||
1112 | auart2: serial@8006e000 { | |
80d969e4 | 1113 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 | 1114 | reg = <0x8006e000 0x2000>; |
7f2b9288 | 1115 | interrupts = <114>; |
f30fb03d SG |
1116 | dmas = <&dma_apbx 12>, <&dma_apbx 13>; |
1117 | dma-names = "rx", "tx"; | |
b598b9f3 | 1118 | clocks = <&clks 45>; |
bc3a59c1 DA |
1119 | status = "disabled"; |
1120 | }; | |
1121 | ||
1122 | auart3: serial@80070000 { | |
80d969e4 | 1123 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 | 1124 | reg = <0x80070000 0x2000>; |
7f2b9288 | 1125 | interrupts = <115>; |
f30fb03d SG |
1126 | dmas = <&dma_apbx 14>, <&dma_apbx 15>; |
1127 | dma-names = "rx", "tx"; | |
b598b9f3 | 1128 | clocks = <&clks 45>; |
bc3a59c1 DA |
1129 | status = "disabled"; |
1130 | }; | |
1131 | ||
1132 | auart4: serial@80072000 { | |
80d969e4 | 1133 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 | 1134 | reg = <0x80072000 0x2000>; |
7f2b9288 | 1135 | interrupts = <116>; |
f30fb03d SG |
1136 | dmas = <&dma_apbx 0>, <&dma_apbx 1>; |
1137 | dma-names = "rx", "tx"; | |
b598b9f3 | 1138 | clocks = <&clks 45>; |
bc3a59c1 DA |
1139 | status = "disabled"; |
1140 | }; | |
1141 | ||
1142 | duart: serial@80074000 { | |
1143 | compatible = "arm,pl011", "arm,primecell"; | |
1144 | reg = <0x80074000 0x1000>; | |
1145 | interrupts = <47>; | |
b598b9f3 SG |
1146 | clocks = <&clks 45>, <&clks 26>; |
1147 | clock-names = "uart", "apb_pclk"; | |
bc3a59c1 DA |
1148 | status = "disabled"; |
1149 | }; | |
1150 | ||
1151 | usbphy0: usbphy@8007c000 { | |
5da01270 | 1152 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; |
bc3a59c1 | 1153 | reg = <0x8007c000 0x2000>; |
b598b9f3 | 1154 | clocks = <&clks 62>; |
bc3a59c1 DA |
1155 | status = "disabled"; |
1156 | }; | |
1157 | ||
1158 | usbphy1: usbphy@8007e000 { | |
5da01270 | 1159 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; |
bc3a59c1 | 1160 | reg = <0x8007e000 0x2000>; |
b598b9f3 | 1161 | clocks = <&clks 63>; |
bc3a59c1 DA |
1162 | status = "disabled"; |
1163 | }; | |
1164 | }; | |
1165 | }; | |
1166 | ||
1167 | ahb@80080000 { | |
1168 | compatible = "simple-bus"; | |
1169 | #address-cells = <1>; | |
1170 | #size-cells = <1>; | |
1171 | reg = <0x80080000 0x80000>; | |
1172 | ranges; | |
1173 | ||
5da01270 RZ |
1174 | usb0: usb@80080000 { |
1175 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; | |
bc3a59c1 | 1176 | reg = <0x80080000 0x10000>; |
5da01270 | 1177 | interrupts = <93>; |
b598b9f3 | 1178 | clocks = <&clks 60>; |
5da01270 | 1179 | fsl,usbphy = <&usbphy0>; |
bc3a59c1 DA |
1180 | status = "disabled"; |
1181 | }; | |
1182 | ||
5da01270 RZ |
1183 | usb1: usb@80090000 { |
1184 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; | |
bc3a59c1 | 1185 | reg = <0x80090000 0x10000>; |
5da01270 | 1186 | interrupts = <92>; |
b598b9f3 | 1187 | clocks = <&clks 61>; |
5da01270 | 1188 | fsl,usbphy = <&usbphy1>; |
bc3a59c1 DA |
1189 | status = "disabled"; |
1190 | }; | |
1191 | ||
296f8cd3 | 1192 | dflpt: dflpt@800c0000 { |
bc3a59c1 DA |
1193 | reg = <0x800c0000 0x10000>; |
1194 | status = "disabled"; | |
1195 | }; | |
1196 | ||
1197 | mac0: ethernet@800f0000 { | |
1198 | compatible = "fsl,imx28-fec"; | |
1199 | reg = <0x800f0000 0x4000>; | |
1200 | interrupts = <101>; | |
f231a9fe WS |
1201 | clocks = <&clks 57>, <&clks 57>, <&clks 64>; |
1202 | clock-names = "ipg", "ahb", "enet_out"; | |
bc3a59c1 DA |
1203 | status = "disabled"; |
1204 | }; | |
1205 | ||
1206 | mac1: ethernet@800f4000 { | |
1207 | compatible = "fsl,imx28-fec"; | |
1208 | reg = <0x800f4000 0x4000>; | |
1209 | interrupts = <102>; | |
b598b9f3 SG |
1210 | clocks = <&clks 57>, <&clks 57>; |
1211 | clock-names = "ipg", "ahb"; | |
bc3a59c1 DA |
1212 | status = "disabled"; |
1213 | }; | |
1214 | ||
296f8cd3 | 1215 | etn_switch: switch@800f8000 { |
bc3a59c1 DA |
1216 | reg = <0x800f8000 0x8000>; |
1217 | status = "disabled"; | |
1218 | }; | |
bc3a59c1 | 1219 | }; |
f92dfb02 AB |
1220 | |
1221 | iio_hwmon { | |
1222 | compatible = "iio-hwmon"; | |
1223 | io-channels = <&lradc 8>; | |
1224 | }; | |
bc3a59c1 | 1225 | }; |