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Merge branches 'for-4.4/upstream-fixes', 'for-4.5/async-suspend', 'for-4.5/container...
[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / imx28.dtsi
CommitLineData
bc3a59c1
DA		 1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
25fc228e 12#include <dt-bindings/gpio/gpio.h>
bc3875f1
LW		 13#include "skeleton.dtsi"
14#include "imx28-pinfunc.h"
bc3a59c1
DA		 15
16/ {
17 interrupt-parent = <&icoll>;
18
ce4c6f9b 19 aliases {
6bf6eb09
FE		 20 ethernet0 = &mac0;
21 ethernet1 = &mac1;
ce4c6f9b
SG		 22 gpio0 = &gpio0;
23 gpio1 = &gpio1;
24 gpio2 = &gpio2;
25 gpio3 = &gpio3;
26 gpio4 = &gpio4;
530f1d41
SG		 27 saif0 = &saif0;
28 saif1 = &saif1;
80d969e4
FE		 29 serial0 = &auart0;
30 serial1 = &auart1;
31 serial2 = &auart2;
32 serial3 = &auart3;
33 serial4 = &auart4;
6bf6eb09
FE		 34 spi0 = &ssp1;
35 spi1 = &ssp2;
1f35cc6a
PC		 36 usbphy0 = &usbphy0;
37 usbphy1 = &usbphy1;
ce4c6f9b
SG		 38 };
39
bc3a59c1 40 cpus {
7925e89f
LP		 41 #address-cells = <0>;
42 #size-cells = <0>;
43
44 cpu {
45 compatible = "arm,arm926ej-s";
46 device_type = "cpu";
bc3a59c1
DA		 47 };
48 };
49
50 apb@80000000 {
51 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
54 reg = <0x80000000 0x80000>;
55 ranges;
56
57 apbh@80000000 {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 reg = <0x80000000 0x3c900>;
62 ranges;
63
64 icoll: interrupt-controller@80000000 {
83a84efc 65 compatible = "fsl,imx28-icoll", "fsl,icoll";
bc3a59c1
DA		 66 interrupt-controller;
67 #interrupt-cells = <1>;
68 reg = <0x80000000 0x2000>;
69 };
70
296f8cd3 71 hsadc: hsadc@80002000 {
0f06cde7 72 reg = <0x80002000 0x2000>;
7f2b9288 73 interrupts = <13>;
f30fb03d
SG		 74 dmas = <&dma_apbh 12>;
75 dma-names = "rx";
bc3a59c1
DA		 76 status = "disabled";
77 };
78
f30fb03d 79 dma_apbh: dma-apbh@80004000 {
84f3570a 80 compatible = "fsl,imx28-dma-apbh";
0f06cde7 81 reg = <0x80004000 0x2000>;
f30fb03d
SG		 82 interrupts = <82 83 84 85
83 88 88 88 88
84 88 88 88 88
85 87 86 0 0>;
86 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
87 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
88 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
89 "hsadc", "lcdif", "empty", "empty";
90 #dma-cells = <1>;
91 dma-channels = <16>;
b598b9f3 92 clocks = <&clks 25>;
bc3a59c1
DA		 93 };
94
296f8cd3 95 perfmon: perfmon@80006000 {
0f06cde7 96 reg = <0x80006000 0x800>;
bc3a59c1
DA		 97 interrupts = <27>;
98 status = "disabled";
99 };
100
296f8cd3 101 gpmi: gpmi-nand@8000c000 {
7a8e5149
HS		 102 compatible = "fsl,imx28-gpmi-nand";
103 #address-cells = <1>;
104 #size-cells = <1>;
0f06cde7 105 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
7a8e5149 106 reg-names = "gpmi-nand", "bch";
7f2b9288
SG		 107 interrupts = <41>;
108 interrupt-names = "bch";
b598b9f3 109 clocks = <&clks 50>;
b6442559 110 clock-names = "gpmi_io";
f30fb03d
SG		 111 dmas = <&dma_apbh 4>;
112 dma-names = "rx-tx";
bc3a59c1
DA		 113 status = "disabled";
114 };
115
116 ssp0: ssp@80010000 {
41bf5706
MR		 117 #address-cells = <1>;
118 #size-cells = <0>;
0f06cde7 119 reg = <0x80010000 0x2000>;
7f2b9288 120 interrupts = <96>;
b598b9f3 121 clocks = <&clks 46>;
f30fb03d
SG		 122 dmas = <&dma_apbh 0>;
123 dma-names = "rx-tx";
bc3a59c1
DA		 124 status = "disabled";
125 };
126
127 ssp1: ssp@80012000 {
41bf5706
MR		 128 #address-cells = <1>;
129 #size-cells = <0>;
0f06cde7 130 reg = <0x80012000 0x2000>;
7f2b9288 131 interrupts = <97>;
b598b9f3 132 clocks = <&clks 47>;
f30fb03d
SG		 133 dmas = <&dma_apbh 1>;
134 dma-names = "rx-tx";
bc3a59c1
DA		 135 status = "disabled";
136 };
137
138 ssp2: ssp@80014000 {
41bf5706
MR		 139 #address-cells = <1>;
140 #size-cells = <0>;
0f06cde7 141 reg = <0x80014000 0x2000>;
7f2b9288 142 interrupts = <98>;
b598b9f3 143 clocks = <&clks 48>;
f30fb03d
SG		 144 dmas = <&dma_apbh 2>;
145 dma-names = "rx-tx";
bc3a59c1
DA		 146 status = "disabled";
147 };
148
149 ssp3: ssp@80016000 {
41bf5706
MR		 150 #address-cells = <1>;
151 #size-cells = <0>;
0f06cde7 152 reg = <0x80016000 0x2000>;
7f2b9288 153 interrupts = <99>;
b598b9f3 154 clocks = <&clks 49>;
f30fb03d
SG		 155 dmas = <&dma_apbh 3>;
156 dma-names = "rx-tx";
bc3a59c1
DA		 157 status = "disabled";
158 };
159
296f8cd3 160 pinctrl: pinctrl@80018000 {
bc3a59c1
DA		 161 #address-cells = <1>;
162 #size-cells = <0>;
ce4c6f9b 163 compatible = "fsl,imx28-pinctrl", "simple-bus";
0f06cde7 164 reg = <0x80018000 0x2000>;
bc3a59c1 165
ce4c6f9b
SG		 166 gpio0: gpio@0 {
167 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
168 interrupts = <127>;
169 gpio-controller;
170 #gpio-cells = <2>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 };
174
175 gpio1: gpio@1 {
176 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
177 interrupts = <126>;
178 gpio-controller;
179 #gpio-cells = <2>;
180 interrupt-controller;
181 #interrupt-cells = <2>;
182 };
183
184 gpio2: gpio@2 {
185 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
186 interrupts = <125>;
187 gpio-controller;
188 #gpio-cells = <2>;
189 interrupt-controller;
190 #interrupt-cells = <2>;
191 };
192
193 gpio3: gpio@3 {
194 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
195 interrupts = <124>;
196 gpio-controller;
197 #gpio-cells = <2>;
198 interrupt-controller;
199 #interrupt-cells = <2>;
200 };
201
202 gpio4: gpio@4 {
203 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
204 interrupts = <123>;
205 gpio-controller;
206 #gpio-cells = <2>;
207 interrupt-controller;
208 #interrupt-cells = <2>;
209 };
210
bc3a59c1
DA		 211 duart_pins_a: duart@0 {
212 reg = <0>;
f14da767 213 fsl,pinmux-ids = <
bc3875f1
LW		 214 MX28_PAD_PWM0__DUART_RX
215 MX28_PAD_PWM1__DUART_TX
f14da767 216 >;
4191c340
LW		 217 fsl,drive-strength = <MXS_DRIVE_4mA>;
218 fsl,voltage = <MXS_VOLTAGE_HIGH>;
219 fsl,pull-up = <MXS_PULL_DISABLE>;
bc3a59c1
DA		 220 };
221
8385e7c1
MR		 222 duart_pins_b: duart@1 {
223 reg = <1>;
f14da767 224 fsl,pinmux-ids = <
bc3875f1
LW		 225 MX28_PAD_AUART0_CTS__DUART_RX
226 MX28_PAD_AUART0_RTS__DUART_TX
f14da767 227 >;
4191c340
LW		 228 fsl,drive-strength = <MXS_DRIVE_4mA>;
229 fsl,voltage = <MXS_VOLTAGE_HIGH>;
230 fsl,pull-up = <MXS_PULL_DISABLE>;
8385e7c1
MR		 231 };
232
e1a4d18f
SG		 233 duart_4pins_a: duart-4pins@0 {
234 reg = <0>;
235 fsl,pinmux-ids = <
bc3875f1
LW		 236 MX28_PAD_AUART0_CTS__DUART_RX
237 MX28_PAD_AUART0_RTS__DUART_TX
238 MX28_PAD_AUART0_RX__DUART_CTS
239 MX28_PAD_AUART0_TX__DUART_RTS
e1a4d18f 240 >;
4191c340
LW		 241 fsl,drive-strength = <MXS_DRIVE_4mA>;
242 fsl,voltage = <MXS_VOLTAGE_HIGH>;
243 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 244 };
245
7a8e5149
HS		 246 gpmi_pins_a: gpmi-nand@0 {
247 reg = <0>;
f14da767 248 fsl,pinmux-ids = <
bc3875f1
LW		 249 MX28_PAD_GPMI_D00__GPMI_D0
250 MX28_PAD_GPMI_D01__GPMI_D1
251 MX28_PAD_GPMI_D02__GPMI_D2
252 MX28_PAD_GPMI_D03__GPMI_D3
253 MX28_PAD_GPMI_D04__GPMI_D4
254 MX28_PAD_GPMI_D05__GPMI_D5
255 MX28_PAD_GPMI_D06__GPMI_D6
256 MX28_PAD_GPMI_D07__GPMI_D7
257 MX28_PAD_GPMI_CE0N__GPMI_CE0N
258 MX28_PAD_GPMI_RDY0__GPMI_READY0
259 MX28_PAD_GPMI_RDN__GPMI_RDN
260 MX28_PAD_GPMI_WRN__GPMI_WRN
261 MX28_PAD_GPMI_ALE__GPMI_ALE
262 MX28_PAD_GPMI_CLE__GPMI_CLE
263 MX28_PAD_GPMI_RESETN__GPMI_RESETN
f14da767 264 >;
4191c340
LW		 265 fsl,drive-strength = <MXS_DRIVE_4mA>;
266 fsl,voltage = <MXS_VOLTAGE_HIGH>;
267 fsl,pull-up = <MXS_PULL_DISABLE>;
7a8e5149
HS		 268 };
269
270 gpmi_status_cfg: gpmi-status-cfg {
f14da767 271 fsl,pinmux-ids = <
bc3875f1
LW		 272 MX28_PAD_GPMI_RDN__GPMI_RDN
273 MX28_PAD_GPMI_WRN__GPMI_WRN
274 MX28_PAD_GPMI_RESETN__GPMI_RESETN
f14da767 275 >;
4191c340 276 fsl,drive-strength = <MXS_DRIVE_12mA>;
7a8e5149
HS		 277 };
278
80d969e4
FE		 279 auart0_pins_a: auart0@0 {
280 reg = <0>;
f14da767 281 fsl,pinmux-ids = <
bc3875f1
LW		 282 MX28_PAD_AUART0_RX__AUART0_RX
283 MX28_PAD_AUART0_TX__AUART0_TX
284 MX28_PAD_AUART0_CTS__AUART0_CTS
285 MX28_PAD_AUART0_RTS__AUART0_RTS
f14da767 286 >;
4191c340
LW		 287 fsl,drive-strength = <MXS_DRIVE_4mA>;
288 fsl,voltage = <MXS_VOLTAGE_HIGH>;
289 fsl,pull-up = <MXS_PULL_DISABLE>;
8fa62e11
MV		 290 };
291
292 auart0_2pins_a: auart0-2pins@0 {
293 reg = <0>;
294 fsl,pinmux-ids = <
bc3875f1
LW		 295 MX28_PAD_AUART0_RX__AUART0_RX
296 MX28_PAD_AUART0_TX__AUART0_TX
8fa62e11 297 >;
4191c340
LW		 298 fsl,drive-strength = <MXS_DRIVE_4mA>;
299 fsl,voltage = <MXS_VOLTAGE_HIGH>;
300 fsl,pull-up = <MXS_PULL_DISABLE>;
80d969e4
FE		 301 };
302
e1a4d18f
SG		 303 auart1_pins_a: auart1@0 {
304 reg = <0>;
305 fsl,pinmux-ids = <
bc3875f1
LW		 306 MX28_PAD_AUART1_RX__AUART1_RX
307 MX28_PAD_AUART1_TX__AUART1_TX
308 MX28_PAD_AUART1_CTS__AUART1_CTS
309 MX28_PAD_AUART1_RTS__AUART1_RTS
e1a4d18f 310 >;
4191c340
LW		 311 fsl,drive-strength = <MXS_DRIVE_4mA>;
312 fsl,voltage = <MXS_VOLTAGE_HIGH>;
313 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 314 };
315
3143bbb4
SG		 316 auart1_2pins_a: auart1-2pins@0 {
317 reg = <0>;
318 fsl,pinmux-ids = <
bc3875f1
LW		 319 MX28_PAD_AUART1_RX__AUART1_RX
320 MX28_PAD_AUART1_TX__AUART1_TX
3143bbb4 321 >;
4191c340
LW		 322 fsl,drive-strength = <MXS_DRIVE_4mA>;
323 fsl,voltage = <MXS_VOLTAGE_HIGH>;
324 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 325 };
326
327 auart2_2pins_a: auart2-2pins@0 {
328 reg = <0>;
329 fsl,pinmux-ids = <
bc3875f1
LW		 330 MX28_PAD_SSP2_SCK__AUART2_RX
331 MX28_PAD_SSP2_MOSI__AUART2_TX
3143bbb4 332 >;
4191c340
LW		 333 fsl,drive-strength = <MXS_DRIVE_4mA>;
334 fsl,voltage = <MXS_VOLTAGE_HIGH>;
335 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 336 };
337
f8040cf5
EB		 338 auart2_2pins_b: auart2-2pins@1 {
339 reg = <1>;
340 fsl,pinmux-ids = <
bc3875f1
LW		 341 MX28_PAD_AUART2_RX__AUART2_RX
342 MX28_PAD_AUART2_TX__AUART2_TX
f8040cf5 343 >;
4191c340
LW		 344 fsl,drive-strength = <MXS_DRIVE_4mA>;
345 fsl,voltage = <MXS_VOLTAGE_HIGH>;
346 fsl,pull-up = <MXS_PULL_DISABLE>;
f8040cf5
EB		 347 };
348
cd0214c3
AM		 349 auart2_pins_a: auart2-pins@0 {
350 reg = <0>;
351 fsl,pinmux-ids = <
352 MX28_PAD_AUART2_RX__AUART2_RX
353 MX28_PAD_AUART2_TX__AUART2_TX
354 MX28_PAD_AUART2_CTS__AUART2_CTS
355 MX28_PAD_AUART2_RTS__AUART2_RTS
356 >;
357 fsl,drive-strength = <MXS_DRIVE_4mA>;
358 fsl,voltage = <MXS_VOLTAGE_HIGH>;
359 fsl,pull-up = <MXS_PULL_DISABLE>;
360 };
361
80d969e4
FE		 362 auart3_pins_a: auart3@0 {
363 reg = <0>;
f14da767 364 fsl,pinmux-ids = <
bc3875f1
LW		 365 MX28_PAD_AUART3_RX__AUART3_RX
366 MX28_PAD_AUART3_TX__AUART3_TX
367 MX28_PAD_AUART3_CTS__AUART3_CTS
368 MX28_PAD_AUART3_RTS__AUART3_RTS
f14da767 369 >;
4191c340
LW		 370 fsl,drive-strength = <MXS_DRIVE_4mA>;
371 fsl,voltage = <MXS_VOLTAGE_HIGH>;
372 fsl,pull-up = <MXS_PULL_DISABLE>;
80d969e4
FE		 373 };
374
3143bbb4
SG		 375 auart3_2pins_a: auart3-2pins@0 {
376 reg = <0>;
377 fsl,pinmux-ids = <
bc3875f1
LW		 378 MX28_PAD_SSP2_MISO__AUART3_RX
379 MX28_PAD_SSP2_SS0__AUART3_TX
3143bbb4 380 >;
4191c340
LW		 381 fsl,drive-strength = <MXS_DRIVE_4mA>;
382 fsl,voltage = <MXS_VOLTAGE_HIGH>;
383 fsl,pull-up = <MXS_PULL_DISABLE>;
3143bbb4
SG		 384 };
385
4812e746
EB		 386 auart3_2pins_b: auart3-2pins@1 {
387 reg = <1>;
388 fsl,pinmux-ids = <
bc3875f1
LW		 389 MX28_PAD_AUART3_RX__AUART3_RX
390 MX28_PAD_AUART3_TX__AUART3_TX
4812e746 391 >;
4191c340
LW		 392 fsl,drive-strength = <MXS_DRIVE_4mA>;
393 fsl,voltage = <MXS_VOLTAGE_HIGH>;
394 fsl,pull-up = <MXS_PULL_DISABLE>;
4812e746
EB		 395 };
396
33678d12
EB		 397 auart4_2pins_a: auart4@0 {
398 reg = <0>;
399 fsl,pinmux-ids = <
bc3875f1
LW		 400 MX28_PAD_SSP3_SCK__AUART4_TX
401 MX28_PAD_SSP3_MOSI__AUART4_RX
33678d12 402 >;
4191c340
LW		 403 fsl,drive-strength = <MXS_DRIVE_4mA>;
404 fsl,voltage = <MXS_VOLTAGE_HIGH>;
405 fsl,pull-up = <MXS_PULL_DISABLE>;
33678d12
EB		 406 };
407
bc3a59c1
DA		 408 mac0_pins_a: mac0@0 {
409 reg = <0>;
f14da767 410 fsl,pinmux-ids = <
bc3875f1
LW		 411 MX28_PAD_ENET0_MDC__ENET0_MDC
412 MX28_PAD_ENET0_MDIO__ENET0_MDIO
413 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
414 MX28_PAD_ENET0_RXD0__ENET0_RXD0
415 MX28_PAD_ENET0_RXD1__ENET0_RXD1
416 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
417 MX28_PAD_ENET0_TXD0__ENET0_TXD0
418 MX28_PAD_ENET0_TXD1__ENET0_TXD1
419 MX28_PAD_ENET_CLK__CLKCTRL_ENET
f14da767 420 >;
4191c340
LW		 421 fsl,drive-strength = <MXS_DRIVE_8mA>;
422 fsl,voltage = <MXS_VOLTAGE_HIGH>;
423 fsl,pull-up = <MXS_PULL_ENABLE>;
bc3a59c1
DA		 424 };
425
426 mac1_pins_a: mac1@0 {
427 reg = <0>;
f14da767 428 fsl,pinmux-ids = <
bc3875f1
LW		 429 MX28_PAD_ENET0_CRS__ENET1_RX_EN
430 MX28_PAD_ENET0_RXD2__ENET1_RXD0
431 MX28_PAD_ENET0_RXD3__ENET1_RXD1
432 MX28_PAD_ENET0_COL__ENET1_TX_EN
433 MX28_PAD_ENET0_TXD2__ENET1_TXD0
434 MX28_PAD_ENET0_TXD3__ENET1_TXD1
f14da767 435 >;
4191c340
LW		 436 fsl,drive-strength = <MXS_DRIVE_8mA>;
437 fsl,voltage = <MXS_VOLTAGE_HIGH>;
438 fsl,pull-up = <MXS_PULL_ENABLE>;
bc3a59c1 439 };
35d23047
SG		 440
441 mmc0_8bit_pins_a: mmc0-8bit@0 {
442 reg = <0>;
f14da767 443 fsl,pinmux-ids = <
bc3875f1
LW		 444 MX28_PAD_SSP0_DATA0__SSP0_D0
445 MX28_PAD_SSP0_DATA1__SSP0_D1
446 MX28_PAD_SSP0_DATA2__SSP0_D2
447 MX28_PAD_SSP0_DATA3__SSP0_D3
448 MX28_PAD_SSP0_DATA4__SSP0_D4
449 MX28_PAD_SSP0_DATA5__SSP0_D5
450 MX28_PAD_SSP0_DATA6__SSP0_D6
451 MX28_PAD_SSP0_DATA7__SSP0_D7
452 MX28_PAD_SSP0_CMD__SSP0_CMD
453 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
454 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 455 >;
4191c340
LW		 456 fsl,drive-strength = <MXS_DRIVE_8mA>;
457 fsl,voltage = <MXS_VOLTAGE_HIGH>;
458 fsl,pull-up = <MXS_PULL_ENABLE>;
35d23047
SG		 459 };
460
8385e7c1
MR		 461 mmc0_4bit_pins_a: mmc0-4bit@0 {
462 reg = <0>;
f14da767 463 fsl,pinmux-ids = <
bc3875f1
LW		 464 MX28_PAD_SSP0_DATA0__SSP0_D0
465 MX28_PAD_SSP0_DATA1__SSP0_D1
466 MX28_PAD_SSP0_DATA2__SSP0_D2
467 MX28_PAD_SSP0_DATA3__SSP0_D3
468 MX28_PAD_SSP0_CMD__SSP0_CMD
469 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
470 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 471 >;
4191c340
LW		 472 fsl,drive-strength = <MXS_DRIVE_8mA>;
473 fsl,voltage = <MXS_VOLTAGE_HIGH>;
474 fsl,pull-up = <MXS_PULL_ENABLE>;
8385e7c1
MR		 475 };
476
35d23047 477 mmc0_cd_cfg: mmc0-cd-cfg {
f14da767 478 fsl,pinmux-ids = <
bc3875f1 479 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
f14da767 480 >;
4191c340 481 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047
SG		 482 };
483
484 mmc0_sck_cfg: mmc0-sck-cfg {
f14da767 485 fsl,pinmux-ids = <
bc3875f1 486 MX28_PAD_SSP0_SCK__SSP0_SCK
f14da767 487 >;
4191c340
LW		 488 fsl,drive-strength = <MXS_DRIVE_12mA>;
489 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047 490 };
2a96e391 491
77d6386b
MKB		 492 mmc1_4bit_pins_a: mmc1-4bit@0 {
493 reg = <0>;
494 fsl,pinmux-ids = <
495 MX28_PAD_GPMI_D00__SSP1_D0
496 MX28_PAD_GPMI_D01__SSP1_D1
497 MX28_PAD_GPMI_D02__SSP1_D2
498 MX28_PAD_GPMI_D03__SSP1_D3
499 MX28_PAD_GPMI_RDY1__SSP1_CMD
500 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
501 MX28_PAD_GPMI_WRN__SSP1_SCK
502 >;
503 fsl,drive-strength = <MXS_DRIVE_8mA>;
504 fsl,voltage = <MXS_VOLTAGE_HIGH>;
505 fsl,pull-up = <MXS_PULL_ENABLE>;
506 };
507
508 mmc1_cd_cfg: mmc1-cd-cfg {
509 fsl,pinmux-ids = <
510 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
511 >;
512 fsl,pull-up = <MXS_PULL_DISABLE>;
513 };
514
515 mmc1_sck_cfg: mmc1-sck-cfg {
516 fsl,pinmux-ids = <
517 MX28_PAD_GPMI_WRN__SSP1_SCK
518 >;
519 fsl,drive-strength = <MXS_DRIVE_12mA>;
520 fsl,pull-up = <MXS_PULL_DISABLE>;
521 };
522
523
5550e8e9
MV		 524 mmc2_4bit_pins_a: mmc2-4bit@0 {
525 reg = <0>;
526 fsl,pinmux-ids = <
527 MX28_PAD_SSP0_DATA4__SSP2_D0
528 MX28_PAD_SSP1_SCK__SSP2_D1
529 MX28_PAD_SSP1_CMD__SSP2_D2
530 MX28_PAD_SSP0_DATA5__SSP2_D3
531 MX28_PAD_SSP0_DATA6__SSP2_CMD
532 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
533 MX28_PAD_SSP0_DATA7__SSP2_SCK
534 >;
535 fsl,drive-strength = <MXS_DRIVE_8mA>;
536 fsl,voltage = <MXS_VOLTAGE_HIGH>;
537 fsl,pull-up = <MXS_PULL_ENABLE>;
538 };
539
540 mmc2_cd_cfg: mmc2-cd-cfg {
541 fsl,pinmux-ids = <
542 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
543 >;
544 fsl,pull-up = <MXS_PULL_DISABLE>;
545 };
546
547 mmc2_sck_cfg: mmc2-sck-cfg {
548 fsl,pinmux-ids = <
549 MX28_PAD_SSP0_DATA7__SSP2_SCK
550 >;
551 fsl,drive-strength = <MXS_DRIVE_12mA>;
552 fsl,pull-up = <MXS_PULL_DISABLE>;
35d23047 553 };
2a96e391
SG		 554
555 i2c0_pins_a: i2c0@0 {
556 reg = <0>;
f14da767 557 fsl,pinmux-ids = <
bc3875f1
LW		 558 MX28_PAD_I2C0_SCL__I2C0_SCL
559 MX28_PAD_I2C0_SDA__I2C0_SDA
f14da767 560 >;
4191c340
LW		 561 fsl,drive-strength = <MXS_DRIVE_8mA>;
562 fsl,voltage = <MXS_VOLTAGE_HIGH>;
563 fsl,pull-up = <MXS_PULL_ENABLE>;
2a96e391 564 };
530f1d41 565
5c697ea2
MR		 566 i2c0_pins_b: i2c0@1 {
567 reg = <1>;
568 fsl,pinmux-ids = <
bc3875f1
LW		 569 MX28_PAD_AUART0_RX__I2C0_SCL
570 MX28_PAD_AUART0_TX__I2C0_SDA
5c697ea2 571 >;
4191c340
LW		 572 fsl,drive-strength = <MXS_DRIVE_8mA>;
573 fsl,voltage = <MXS_VOLTAGE_HIGH>;
574 fsl,pull-up = <MXS_PULL_ENABLE>;
5c697ea2
MR		 575 };
576
de7e934f
MR		 577 i2c1_pins_a: i2c1@0 {
578 reg = <0>;
579 fsl,pinmux-ids = <
bc3875f1
LW		 580 MX28_PAD_PWM0__I2C1_SCL
581 MX28_PAD_PWM1__I2C1_SDA
de7e934f 582 >;
4191c340
LW		 583 fsl,drive-strength = <MXS_DRIVE_8mA>;
584 fsl,voltage = <MXS_VOLTAGE_HIGH>;
585 fsl,pull-up = <MXS_PULL_ENABLE>;
de7e934f
MR		 586 };
587
17c63dd0
UKK		 588 i2c1_pins_b: i2c1@1 {
589 reg = <1>;
590 fsl,pinmux-ids = <
591 MX28_PAD_AUART2_CTS__I2C1_SCL
592 MX28_PAD_AUART2_RTS__I2C1_SDA
593 >;
594 fsl,drive-strength = <MXS_DRIVE_8mA>;
595 fsl,voltage = <MXS_VOLTAGE_HIGH>;
596 fsl,pull-up = <MXS_PULL_ENABLE>;
597 };
598
530f1d41
SG		 599 saif0_pins_a: saif0@0 {
600 reg = <0>;
f14da767 601 fsl,pinmux-ids = <
bc3875f1
LW		 602 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
603 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
604 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
605 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
f14da767 606 >;
4191c340
LW		 607 fsl,drive-strength = <MXS_DRIVE_12mA>;
608 fsl,voltage = <MXS_VOLTAGE_HIGH>;
609 fsl,pull-up = <MXS_PULL_ENABLE>;
530f1d41
SG		 610 };
611
2e1dd9fc
LW		 612 saif0_pins_b: saif0@1 {
613 reg = <1>;
614 fsl,pinmux-ids = <
bc3875f1
LW		 615 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
616 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
617 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
2e1dd9fc 618 >;
4191c340
LW		 619 fsl,drive-strength = <MXS_DRIVE_12mA>;
620 fsl,voltage = <MXS_VOLTAGE_HIGH>;
621 fsl,pull-up = <MXS_PULL_ENABLE>;
2e1dd9fc
LW		 622 };
623
530f1d41
SG		 624 saif1_pins_a: saif1@0 {
625 reg = <0>;
f14da767 626 fsl,pinmux-ids = <
bc3875f1 627 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
f14da767 628 >;
4191c340
LW		 629 fsl,drive-strength = <MXS_DRIVE_12mA>;
630 fsl,voltage = <MXS_VOLTAGE_HIGH>;
631 fsl,pull-up = <MXS_PULL_ENABLE>;
530f1d41 632 };
52f7176b 633
e1a4d18f
SG		 634 pwm0_pins_a: pwm0@0 {
635 reg = <0>;
636 fsl,pinmux-ids = <
bc3875f1 637 MX28_PAD_PWM0__PWM_0
e1a4d18f 638 >;
4191c340
LW		 639 fsl,drive-strength = <MXS_DRIVE_4mA>;
640 fsl,voltage = <MXS_VOLTAGE_HIGH>;
641 fsl,pull-up = <MXS_PULL_DISABLE>;
e1a4d18f
SG		 642 };
643
52f7176b
SG		 644 pwm2_pins_a: pwm2@0 {
645 reg = <0>;
646 fsl,pinmux-ids = <
bc3875f1 647 MX28_PAD_PWM2__PWM_2
52f7176b 648 >;
4191c340
LW		 649 fsl,drive-strength = <MXS_DRIVE_4mA>;
650 fsl,voltage = <MXS_VOLTAGE_HIGH>;
651 fsl,pull-up = <MXS_PULL_DISABLE>;
52f7176b 652 };
a915ee42 653
2bde51cb
JB		 654 pwm3_pins_a: pwm3@0 {
655 reg = <0>;
656 fsl,pinmux-ids = <
bc3875f1 657 MX28_PAD_PWM3__PWM_3
2bde51cb 658 >;
4191c340
LW		 659 fsl,drive-strength = <MXS_DRIVE_4mA>;
660 fsl,voltage = <MXS_VOLTAGE_HIGH>;
661 fsl,pull-up = <MXS_PULL_DISABLE>;
2bde51cb
JB		 662 };
663
d248620c
MR		 664 pwm3_pins_b: pwm3@1 {
665 reg = <1>;
666 fsl,pinmux-ids = <
bc3875f1 667 MX28_PAD_SAIF0_MCLK__PWM_3
d248620c 668 >;
4191c340
LW		 669 fsl,drive-strength = <MXS_DRIVE_4mA>;
670 fsl,voltage = <MXS_VOLTAGE_HIGH>;
671 fsl,pull-up = <MXS_PULL_DISABLE>;
d248620c
MR		 672 };
673
2f44211f
MR		 674 pwm4_pins_a: pwm4@0 {
675 reg = <0>;
676 fsl,pinmux-ids = <
bc3875f1 677 MX28_PAD_PWM4__PWM_4
2f44211f 678 >;
4191c340
LW		 679 fsl,drive-strength = <MXS_DRIVE_4mA>;
680 fsl,voltage = <MXS_VOLTAGE_HIGH>;
681 fsl,pull-up = <MXS_PULL_DISABLE>;
2f44211f
MR		 682 };
683
a915ee42
SG		 684 lcdif_24bit_pins_a: lcdif-24bit@0 {
685 reg = <0>;
686 fsl,pinmux-ids = <
bc3875f1
LW		 687 MX28_PAD_LCD_D00__LCD_D0
688 MX28_PAD_LCD_D01__LCD_D1
689 MX28_PAD_LCD_D02__LCD_D2
690 MX28_PAD_LCD_D03__LCD_D3
691 MX28_PAD_LCD_D04__LCD_D4
692 MX28_PAD_LCD_D05__LCD_D5
693 MX28_PAD_LCD_D06__LCD_D6
694 MX28_PAD_LCD_D07__LCD_D7
695 MX28_PAD_LCD_D08__LCD_D8
696 MX28_PAD_LCD_D09__LCD_D9
697 MX28_PAD_LCD_D10__LCD_D10
698 MX28_PAD_LCD_D11__LCD_D11
699 MX28_PAD_LCD_D12__LCD_D12
700 MX28_PAD_LCD_D13__LCD_D13
701 MX28_PAD_LCD_D14__LCD_D14
702 MX28_PAD_LCD_D15__LCD_D15
703 MX28_PAD_LCD_D16__LCD_D16
704 MX28_PAD_LCD_D17__LCD_D17
705 MX28_PAD_LCD_D18__LCD_D18
706 MX28_PAD_LCD_D19__LCD_D19
707 MX28_PAD_LCD_D20__LCD_D20
708 MX28_PAD_LCD_D21__LCD_D21
709 MX28_PAD_LCD_D22__LCD_D22
710 MX28_PAD_LCD_D23__LCD_D23
a915ee42 711 >;
4191c340
LW		 712 fsl,drive-strength = <MXS_DRIVE_4mA>;
713 fsl,voltage = <MXS_VOLTAGE_HIGH>;
714 fsl,pull-up = <MXS_PULL_DISABLE>;
a915ee42 715 };
6ca44acf 716
ec985eb2
DC		 717 lcdif_18bit_pins_a: lcdif-18bit@0 {
718 reg = <0>;
719 fsl,pinmux-ids = <
720 MX28_PAD_LCD_D00__LCD_D0
721 MX28_PAD_LCD_D01__LCD_D1
722 MX28_PAD_LCD_D02__LCD_D2
723 MX28_PAD_LCD_D03__LCD_D3
724 MX28_PAD_LCD_D04__LCD_D4
725 MX28_PAD_LCD_D05__LCD_D5
726 MX28_PAD_LCD_D06__LCD_D6
727 MX28_PAD_LCD_D07__LCD_D7
728 MX28_PAD_LCD_D08__LCD_D8
729 MX28_PAD_LCD_D09__LCD_D9
730 MX28_PAD_LCD_D10__LCD_D10
731 MX28_PAD_LCD_D11__LCD_D11
732 MX28_PAD_LCD_D12__LCD_D12
733 MX28_PAD_LCD_D13__LCD_D13
734 MX28_PAD_LCD_D14__LCD_D14
735 MX28_PAD_LCD_D15__LCD_D15
736 MX28_PAD_LCD_D16__LCD_D16
737 MX28_PAD_LCD_D17__LCD_D17
738 >;
739 fsl,drive-strength = <MXS_DRIVE_4mA>;
740 fsl,voltage = <MXS_VOLTAGE_HIGH>;
741 fsl,pull-up = <MXS_PULL_DISABLE>;
742 };
743
4ced2a40
GGM		 744 lcdif_16bit_pins_a: lcdif-16bit@0 {
745 reg = <0>;
746 fsl,pinmux-ids = <
bc3875f1
LW		 747 MX28_PAD_LCD_D00__LCD_D0
748 MX28_PAD_LCD_D01__LCD_D1
749 MX28_PAD_LCD_D02__LCD_D2
750 MX28_PAD_LCD_D03__LCD_D3
751 MX28_PAD_LCD_D04__LCD_D4
752 MX28_PAD_LCD_D05__LCD_D5
753 MX28_PAD_LCD_D06__LCD_D6
754 MX28_PAD_LCD_D07__LCD_D7
755 MX28_PAD_LCD_D08__LCD_D8
756 MX28_PAD_LCD_D09__LCD_D9
757 MX28_PAD_LCD_D10__LCD_D10
758 MX28_PAD_LCD_D11__LCD_D11
759 MX28_PAD_LCD_D12__LCD_D12
760 MX28_PAD_LCD_D13__LCD_D13
761 MX28_PAD_LCD_D14__LCD_D14
762 MX28_PAD_LCD_D15__LCD_D15
4ced2a40 763 >;
4191c340
LW		 764 fsl,drive-strength = <MXS_DRIVE_4mA>;
765 fsl,voltage = <MXS_VOLTAGE_HIGH>;
766 fsl,pull-up = <MXS_PULL_DISABLE>;
4ced2a40
GGM		 767 };
768
23ad6f65
LW		 769 lcdif_sync_pins_a: lcdif-sync@0 {
770 reg = <0>;
771 fsl,pinmux-ids = <
bc3875f1
LW		 772 MX28_PAD_LCD_RS__LCD_DOTCLK
773 MX28_PAD_LCD_CS__LCD_ENABLE
774 MX28_PAD_LCD_RD_E__LCD_VSYNC
775 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
23ad6f65 776 >;
4191c340
LW		 777 fsl,drive-strength = <MXS_DRIVE_4mA>;
778 fsl,voltage = <MXS_VOLTAGE_HIGH>;
779 fsl,pull-up = <MXS_PULL_DISABLE>;
23ad6f65
LW		 780 };
781
6ca44acf
SG		 782 can0_pins_a: can0@0 {
783 reg = <0>;
784 fsl,pinmux-ids = <
bc3875f1
LW		 785 MX28_PAD_GPMI_RDY2__CAN0_TX
786 MX28_PAD_GPMI_RDY3__CAN0_RX
6ca44acf 787 >;
4191c340
LW		 788 fsl,drive-strength = <MXS_DRIVE_4mA>;
789 fsl,voltage = <MXS_VOLTAGE_HIGH>;
790 fsl,pull-up = <MXS_PULL_DISABLE>;
6ca44acf
SG		 791 };
792
793 can1_pins_a: can1@0 {
794 reg = <0>;
795 fsl,pinmux-ids = <
bc3875f1
LW		 796 MX28_PAD_GPMI_CE2N__CAN1_TX
797 MX28_PAD_GPMI_CE3N__CAN1_RX
6ca44acf 798 >;
4191c340
LW		 799 fsl,drive-strength = <MXS_DRIVE_4mA>;
800 fsl,voltage = <MXS_VOLTAGE_HIGH>;
801 fsl,pull-up = <MXS_PULL_DISABLE>;
6ca44acf 802 };
7f122213
MV		 803
804 spi2_pins_a: spi2@0 {
805 reg = <0>;
806 fsl,pinmux-ids = <
bc3875f1
LW		 807 MX28_PAD_SSP2_SCK__SSP2_SCK
808 MX28_PAD_SSP2_MOSI__SSP2_CMD
809 MX28_PAD_SSP2_MISO__SSP2_D0
810 MX28_PAD_SSP2_SS0__SSP2_D3
7f122213 811 >;
4191c340
LW		 812 fsl,drive-strength = <MXS_DRIVE_8mA>;
813 fsl,voltage = <MXS_VOLTAGE_HIGH>;
814 fsl,pull-up = <MXS_PULL_ENABLE>;
7f122213 815 };
bb2f1261 816
3314d2be
LW		 817 spi3_pins_a: spi3@0 {
818 reg = <0>;
819 fsl,pinmux-ids = <
bc3875f1
LW		 820 MX28_PAD_AUART2_RX__SSP3_D4
821 MX28_PAD_AUART2_TX__SSP3_D5
822 MX28_PAD_SSP3_SCK__SSP3_SCK
823 MX28_PAD_SSP3_MOSI__SSP3_CMD
824 MX28_PAD_SSP3_MISO__SSP3_D0
825 MX28_PAD_SSP3_SS0__SSP3_D3
3314d2be 826 >;
4191c340
LW		 827 fsl,drive-strength = <MXS_DRIVE_8mA>;
828 fsl,voltage = <MXS_VOLTAGE_HIGH>;
829 fsl,pull-up = <MXS_PULL_DISABLE>;
3314d2be
LW		 830 };
831
8f0b07a4
UKK		 832 spi3_pins_b: spi3@1 {
833 reg = <1>;
834 fsl,pinmux-ids = <
835 MX28_PAD_SSP3_SCK__SSP3_SCK
836 MX28_PAD_SSP3_MOSI__SSP3_CMD
837 MX28_PAD_SSP3_MISO__SSP3_D0
838 MX28_PAD_SSP3_SS0__SSP3_D3
839 >;
840 fsl,drive-strength = <MXS_DRIVE_8mA>;
841 fsl,voltage = <MXS_VOLTAGE_HIGH>;
842 fsl,pull-up = <MXS_PULL_ENABLE>;
843 };
844
c8e42bc9 845 usb0_pins_a: usb0@0 {
bb2f1261
MV		 846 reg = <0>;
847 fsl,pinmux-ids = <
bc3875f1 848 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
bb2f1261 849 >;
4191c340
LW		 850 fsl,drive-strength = <MXS_DRIVE_12mA>;
851 fsl,voltage = <MXS_VOLTAGE_HIGH>;
852 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261
MV		 853 };
854
c8e42bc9 855 usb0_pins_b: usb0@1 {
bb2f1261
MV		 856 reg = <1>;
857 fsl,pinmux-ids = <
bc3875f1 858 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
bb2f1261 859 >;
4191c340
LW		 860 fsl,drive-strength = <MXS_DRIVE_12mA>;
861 fsl,voltage = <MXS_VOLTAGE_HIGH>;
862 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261
MV		 863 };
864
c8e42bc9 865 usb1_pins_a: usb1@0 {
bb2f1261
MV		 866 reg = <0>;
867 fsl,pinmux-ids = <
bc3875f1 868 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
bb2f1261 869 >;
4191c340
LW		 870 fsl,drive-strength = <MXS_DRIVE_12mA>;
871 fsl,voltage = <MXS_VOLTAGE_HIGH>;
872 fsl,pull-up = <MXS_PULL_DISABLE>;
bb2f1261 873 };
69c02f95
FE		 874
875 usb0_id_pins_a: usb0id@0 {
876 reg = <0>;
877 fsl,pinmux-ids = <
e96e1782 878 MX28_PAD_AUART1_RTS__USB0_ID
bb2f1261 879 >;
e96e1782
LW		 880 fsl,drive-strength = <MXS_DRIVE_12mA>;
881 fsl,voltage = <MXS_VOLTAGE_HIGH>;
882 fsl,pull-up = <MXS_PULL_ENABLE>;
bb2f1261 883 };
bb89b8d2
DC		 884
885 usb0_id_pins_b: usb0id1@0 {
886 reg = <0>;
887 fsl,pinmux-ids = <
888 MX28_PAD_PWM2__USB0_ID
889 >;
890 fsl,drive-strength = <MXS_DRIVE_12mA>;
891 fsl,voltage = <MXS_VOLTAGE_HIGH>;
892 fsl,pull-up = <MXS_PULL_ENABLE>;
893 };
894
bc3a59c1
DA		 895 };
896
296f8cd3 897 digctl: digctl@8001c000 {
115581cf 898 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
0f06cde7 899 reg = <0x8001c000 0x2000>;
bc3a59c1
DA		 900 interrupts = <89>;
901 status = "disabled";
902 };
903
296f8cd3 904 etm: etm@80022000 {
0f06cde7 905 reg = <0x80022000 0x2000>;
bc3a59c1
DA		 906 status = "disabled";
907 };
908
f30fb03d 909 dma_apbx: dma-apbx@80024000 {
84f3570a 910 compatible = "fsl,imx28-dma-apbx";
0f06cde7 911 reg = <0x80024000 0x2000>;
f30fb03d
SG		 912 interrupts = <78 79 66 0
913 80 81 68 69
914 70 71 72 73
915 74 75 76 77>;
4ada77e3 916 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
f30fb03d
SG		 917 "saif0", "saif1", "i2c0", "i2c1",
918 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
919 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
920 #dma-cells = <1>;
921 dma-channels = <16>;
b598b9f3 922 clocks = <&clks 26>;
bc3a59c1
DA		 923 };
924
296f8cd3 925 dcp: dcp@80028000 {
7d56a28f 926 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
0f06cde7 927 reg = <0x80028000 0x2000>;
bc3a59c1 928 interrupts = <52 53 54>;
7d56a28f 929 status = "okay";
bc3a59c1
DA		 930 };
931
296f8cd3 932 pxp: pxp@8002a000 {
0f06cde7 933 reg = <0x8002a000 0x2000>;
bc3a59c1
DA		 934 interrupts = <39>;
935 status = "disabled";
936 };
937
296f8cd3 938 ocotp: ocotp@8002c000 {
a7be1e68
SW		 939 compatible = "fsl,imx28-ocotp", "fsl,ocotp";
940 #address-cells = <1>;
941 #size-cells = <1>;
0f06cde7 942 reg = <0x8002c000 0x2000>;
a7be1e68 943 clocks = <&clks 25>;
bc3a59c1
DA		 944 };
945
946 axi-ahb@8002e000 {
0f06cde7 947 reg = <0x8002e000 0x2000>;
bc3a59c1
DA		 948 status = "disabled";
949 };
950
296f8cd3 951 lcdif: lcdif@80030000 {
a915ee42 952 compatible = "fsl,imx28-lcdif";
0f06cde7 953 reg = <0x80030000 0x2000>;
7f2b9288 954 interrupts = <38>;
b598b9f3 955 clocks = <&clks 55>;
f30fb03d
SG		 956 dmas = <&dma_apbh 13>;
957 dma-names = "rx";
bc3a59c1
DA		 958 status = "disabled";
959 };
960
961 can0: can@80032000 {
6ca44acf 962 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 963 reg = <0x80032000 0x2000>;
bc3a59c1 964 interrupts = <8>;
b598b9f3
SG		 965 clocks = <&clks 58>, <&clks 58>;
966 clock-names = "ipg", "per";
bc3a59c1
DA		 967 status = "disabled";
968 };
969
970 can1: can@80034000 {
6ca44acf 971 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 972 reg = <0x80034000 0x2000>;
bc3a59c1 973 interrupts = <9>;
b598b9f3
SG		 974 clocks = <&clks 59>, <&clks 59>;
975 clock-names = "ipg", "per";
bc3a59c1
DA		 976 status = "disabled";
977 };
978
296f8cd3 979 simdbg: simdbg@8003c000 {
0f06cde7 980 reg = <0x8003c000 0x200>;
bc3a59c1
DA		 981 status = "disabled";
982 };
983
296f8cd3 984 simgpmisel: simgpmisel@8003c200 {
0f06cde7 985 reg = <0x8003c200 0x100>;
bc3a59c1
DA		 986 status = "disabled";
987 };
988
296f8cd3 989 simsspsel: simsspsel@8003c300 {
0f06cde7 990 reg = <0x8003c300 0x100>;
bc3a59c1
DA		 991 status = "disabled";
992 };
993
296f8cd3 994 simmemsel: simmemsel@8003c400 {
0f06cde7 995 reg = <0x8003c400 0x100>;
bc3a59c1
DA		 996 status = "disabled";
997 };
998
296f8cd3 999 gpiomon: gpiomon@8003c500 {
0f06cde7 1000 reg = <0x8003c500 0x100>;
bc3a59c1
DA		 1001 status = "disabled";
1002 };
1003
296f8cd3 1004 simenet: simenet@8003c700 {
0f06cde7 1005 reg = <0x8003c700 0x100>;
bc3a59c1
DA		 1006 status = "disabled";
1007 };
1008
296f8cd3 1009 armjtag: armjtag@8003c800 {
0f06cde7 1010 reg = <0x8003c800 0x100>;
bc3a59c1
DA		 1011 status = "disabled";
1012 };
07a3ce7f 1013 };
bc3a59c1
DA		 1014
1015 apbx@80040000 {
1016 compatible = "simple-bus";
1017 #address-cells = <1>;
1018 #size-cells = <1>;
1019 reg = <0x80040000 0x40000>;
1020 ranges;
1021
b598b9f3 1022 clks: clkctrl@80040000 {
8f7cf881 1023 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
0f06cde7 1024 reg = <0x80040000 0x2000>;
b598b9f3 1025 #clock-cells = <1>;
bc3a59c1
DA		 1026 };
1027
1028 saif0: saif@80042000 {
530f1d41 1029 compatible = "fsl,imx28-saif";
0f06cde7 1030 reg = <0x80042000 0x2000>;
7f2b9288 1031 interrupts = <59>;
66acaf3f 1032 #clock-cells = <0>;
b598b9f3 1033 clocks = <&clks 53>;
f30fb03d
SG		 1034 dmas = <&dma_apbx 4>;
1035 dma-names = "rx-tx";
bc3a59c1
DA		 1036 status = "disabled";
1037 };
1038
296f8cd3 1039 power: power@80044000 {
0f06cde7 1040 reg = <0x80044000 0x2000>;
bc3a59c1
DA		 1041 status = "disabled";
1042 };
1043
1044 saif1: saif@80046000 {
530f1d41 1045 compatible = "fsl,imx28-saif";
0f06cde7 1046 reg = <0x80046000 0x2000>;
7f2b9288 1047 interrupts = <58>;
b598b9f3 1048 clocks = <&clks 54>;
f30fb03d
SG		 1049 dmas = <&dma_apbx 5>;
1050 dma-names = "rx-tx";
bc3a59c1
DA		 1051 status = "disabled";
1052 };
1053
296f8cd3 1054 lradc: lradc@80050000 {
aef35104 1055 compatible = "fsl,imx28-lradc";
0f06cde7 1056 reg = <0x80050000 0x2000>;
aef35104
MV		 1057 interrupts = <10 14 15 16 17 18 19
1058 20 21 22 23 24 25>;
bc3a59c1 1059 status = "disabled";
18da755d 1060 clocks = <&clks 41>;
40dde681 1061 #io-channel-cells = <1>;
bc3a59c1
DA		 1062 };
1063
296f8cd3 1064 spdif: spdif@80054000 {
0f06cde7 1065 reg = <0x80054000 0x2000>;
7f2b9288 1066 interrupts = <45>;
f30fb03d
SG		 1067 dmas = <&dma_apbx 2>;
1068 dma-names = "tx";
bc3a59c1
DA		 1069 status = "disabled";
1070 };
1071
296f8cd3 1072 mxs_rtc: rtc@80056000 {
f98c990c 1073 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
0f06cde7 1074 reg = <0x80056000 0x2000>;
f98c990c 1075 interrupts = <29>;
bc3a59c1
DA		 1076 };
1077
1078 i2c0: i2c@80058000 {
2a96e391
SG		 1079 #address-cells = <1>;
1080 #size-cells = <0>;
1081 compatible = "fsl,imx28-i2c";
0f06cde7 1082 reg = <0x80058000 0x2000>;
7f2b9288 1083 interrupts = <111>;
cd4f2d4a 1084 clock-frequency = <100000>;
f30fb03d
SG		 1085 dmas = <&dma_apbx 6>;
1086 dma-names = "rx-tx";
bc3a59c1
DA		 1087 status = "disabled";
1088 };
1089
1090 i2c1: i2c@8005a000 {
2a96e391
SG		 1091 #address-cells = <1>;
1092 #size-cells = <0>;
1093 compatible = "fsl,imx28-i2c";
0f06cde7 1094 reg = <0x8005a000 0x2000>;
7f2b9288 1095 interrupts = <110>;
cd4f2d4a 1096 clock-frequency = <100000>;
f30fb03d
SG		 1097 dmas = <&dma_apbx 7>;
1098 dma-names = "rx-tx";
bc3a59c1
DA		 1099 status = "disabled";
1100 };
1101
52f7176b
SG		 1102 pwm: pwm@80064000 {
1103 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
0f06cde7 1104 reg = <0x80064000 0x2000>;
b598b9f3 1105 clocks = <&clks 44>;
52f7176b
SG		 1106 #pwm-cells = <2>;
1107 fsl,pwm-number = <8>;
bc3a59c1
DA		 1108 status = "disabled";
1109 };
1110
296f8cd3 1111 timer: timrot@80068000 {
eeca6e60 1112 compatible = "fsl,imx28-timrot", "fsl,timrot";
0f06cde7 1113 reg = <0x80068000 0x2000>;
eeca6e60 1114 interrupts = <48 49 50 51>;
2efb9504 1115 clocks = <&clks 26>;
bc3a59c1
DA		 1116 };
1117
1118 auart0: serial@8006a000 {
80d969e4 1119 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1120 reg = <0x8006a000 0x2000>;
7f2b9288 1121 interrupts = <112>;
f30fb03d
SG		 1122 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1123 dma-names = "rx", "tx";
b598b9f3 1124 clocks = <&clks 45>;
bc3a59c1
DA		 1125 status = "disabled";
1126 };
1127
1128 auart1: serial@8006c000 {
80d969e4 1129 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1130 reg = <0x8006c000 0x2000>;
7f2b9288 1131 interrupts = <113>;
f30fb03d
SG		 1132 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1133 dma-names = "rx", "tx";
b598b9f3 1134 clocks = <&clks 45>;
bc3a59c1
DA		 1135 status = "disabled";
1136 };
1137
1138 auart2: serial@8006e000 {
80d969e4 1139 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1140 reg = <0x8006e000 0x2000>;
7f2b9288 1141 interrupts = <114>;
f30fb03d
SG		 1142 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1143 dma-names = "rx", "tx";
b598b9f3 1144 clocks = <&clks 45>;
bc3a59c1
DA		 1145 status = "disabled";
1146 };
1147
1148 auart3: serial@80070000 {
80d969e4 1149 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1150 reg = <0x80070000 0x2000>;
7f2b9288 1151 interrupts = <115>;
f30fb03d
SG		 1152 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1153 dma-names = "rx", "tx";
b598b9f3 1154 clocks = <&clks 45>;
bc3a59c1
DA		 1155 status = "disabled";
1156 };
1157
1158 auart4: serial@80072000 {
80d969e4 1159 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 1160 reg = <0x80072000 0x2000>;
7f2b9288 1161 interrupts = <116>;
f30fb03d
SG		 1162 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1163 dma-names = "rx", "tx";
b598b9f3 1164 clocks = <&clks 45>;
bc3a59c1
DA		 1165 status = "disabled";
1166 };
1167
1168 duart: serial@80074000 {
1169 compatible = "arm,pl011", "arm,primecell";
1170 reg = <0x80074000 0x1000>;
1171 interrupts = <47>;
b598b9f3
SG		 1172 clocks = <&clks 45>, <&clks 26>;
1173 clock-names = "uart", "apb_pclk";
bc3a59c1
DA		 1174 status = "disabled";
1175 };
1176
1177 usbphy0: usbphy@8007c000 {
5da01270 1178 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 1179 reg = <0x8007c000 0x2000>;
b598b9f3 1180 clocks = <&clks 62>;
bc3a59c1
DA		 1181 status = "disabled";
1182 };
1183
1184 usbphy1: usbphy@8007e000 {
5da01270 1185 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 1186 reg = <0x8007e000 0x2000>;
b598b9f3 1187 clocks = <&clks 63>;
bc3a59c1
DA		 1188 status = "disabled";
1189 };
1190 };
1191 };
1192
1193 ahb@80080000 {
1194 compatible = "simple-bus";
1195 #address-cells = <1>;
1196 #size-cells = <1>;
1197 reg = <0x80080000 0x80000>;
1198 ranges;
1199
5da01270
RZ		 1200 usb0: usb@80080000 {
1201 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 1202 reg = <0x80080000 0x10000>;
5da01270 1203 interrupts = <93>;
b598b9f3 1204 clocks = <&clks 60>;
5da01270 1205 fsl,usbphy = <&usbphy0>;
bc3a59c1
DA		 1206 status = "disabled";
1207 };
1208
5da01270
RZ		 1209 usb1: usb@80090000 {
1210 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 1211 reg = <0x80090000 0x10000>;
5da01270 1212 interrupts = <92>;
b598b9f3 1213 clocks = <&clks 61>;
5da01270 1214 fsl,usbphy = <&usbphy1>;
3ec481ed 1215 dr_mode = "host";
bc3a59c1
DA		 1216 status = "disabled";
1217 };
1218
296f8cd3 1219 dflpt: dflpt@800c0000 {
bc3a59c1
DA		 1220 reg = <0x800c0000 0x10000>;
1221 status = "disabled";
1222 };
1223
1224 mac0: ethernet@800f0000 {
1225 compatible = "fsl,imx28-fec";
1226 reg = <0x800f0000 0x4000>;
1227 interrupts = <101>;
f231a9fe
WS		 1228 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1229 clock-names = "ipg", "ahb", "enet_out";
bc3a59c1
DA		 1230 status = "disabled";
1231 };
1232
1233 mac1: ethernet@800f4000 {
1234 compatible = "fsl,imx28-fec";
1235 reg = <0x800f4000 0x4000>;
1236 interrupts = <102>;
b598b9f3
SG		 1237 clocks = <&clks 57>, <&clks 57>;
1238 clock-names = "ipg", "ahb";
bc3a59c1
DA		 1239 status = "disabled";
1240 };
1241
296f8cd3 1242 etn_switch: switch@800f8000 {
bc3a59c1
DA		 1243 reg = <0x800f8000 0x8000>;
1244 status = "disabled";
1245 };
bc3a59c1 1246 };
f92dfb02
AB		 1247
1248 iio_hwmon {
1249 compatible = "iio-hwmon";
1250 io-channels = <&lradc 8>;
1251 };
bc3a59c1 1252};
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