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bc3a59c1 DA |
1 | /* |
2 | * Copyright 2012 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
bc3875f1 LW |
12 | #include "skeleton.dtsi" |
13 | #include "imx28-pinfunc.h" | |
bc3a59c1 DA |
14 | |
15 | / { | |
16 | interrupt-parent = <&icoll>; | |
17 | ||
ce4c6f9b | 18 | aliases { |
6bf6eb09 FE |
19 | ethernet0 = &mac0; |
20 | ethernet1 = &mac1; | |
ce4c6f9b SG |
21 | gpio0 = &gpio0; |
22 | gpio1 = &gpio1; | |
23 | gpio2 = &gpio2; | |
24 | gpio3 = &gpio3; | |
25 | gpio4 = &gpio4; | |
530f1d41 SG |
26 | saif0 = &saif0; |
27 | saif1 = &saif1; | |
80d969e4 FE |
28 | serial0 = &auart0; |
29 | serial1 = &auart1; | |
30 | serial2 = &auart2; | |
31 | serial3 = &auart3; | |
32 | serial4 = &auart4; | |
6bf6eb09 FE |
33 | spi0 = &ssp1; |
34 | spi1 = &ssp2; | |
ce4c6f9b SG |
35 | }; |
36 | ||
bc3a59c1 | 37 | cpus { |
7925e89f LP |
38 | #address-cells = <0>; |
39 | #size-cells = <0>; | |
40 | ||
41 | cpu { | |
42 | compatible = "arm,arm926ej-s"; | |
43 | device_type = "cpu"; | |
bc3a59c1 DA |
44 | }; |
45 | }; | |
46 | ||
47 | apb@80000000 { | |
48 | compatible = "simple-bus"; | |
49 | #address-cells = <1>; | |
50 | #size-cells = <1>; | |
51 | reg = <0x80000000 0x80000>; | |
52 | ranges; | |
53 | ||
54 | apbh@80000000 { | |
55 | compatible = "simple-bus"; | |
56 | #address-cells = <1>; | |
57 | #size-cells = <1>; | |
58 | reg = <0x80000000 0x3c900>; | |
59 | ranges; | |
60 | ||
61 | icoll: interrupt-controller@80000000 { | |
83a84efc | 62 | compatible = "fsl,imx28-icoll", "fsl,icoll"; |
bc3a59c1 DA |
63 | interrupt-controller; |
64 | #interrupt-cells = <1>; | |
65 | reg = <0x80000000 0x2000>; | |
66 | }; | |
67 | ||
296f8cd3 | 68 | hsadc: hsadc@80002000 { |
0f06cde7 | 69 | reg = <0x80002000 0x2000>; |
7f2b9288 | 70 | interrupts = <13>; |
f30fb03d SG |
71 | dmas = <&dma_apbh 12>; |
72 | dma-names = "rx"; | |
bc3a59c1 DA |
73 | status = "disabled"; |
74 | }; | |
75 | ||
f30fb03d | 76 | dma_apbh: dma-apbh@80004000 { |
84f3570a | 77 | compatible = "fsl,imx28-dma-apbh"; |
0f06cde7 | 78 | reg = <0x80004000 0x2000>; |
f30fb03d SG |
79 | interrupts = <82 83 84 85 |
80 | 88 88 88 88 | |
81 | 88 88 88 88 | |
82 | 87 86 0 0>; | |
83 | interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3", | |
84 | "gpmi0", "gmpi1", "gpmi2", "gmpi3", | |
85 | "gpmi4", "gmpi5", "gpmi6", "gmpi7", | |
86 | "hsadc", "lcdif", "empty", "empty"; | |
87 | #dma-cells = <1>; | |
88 | dma-channels = <16>; | |
b598b9f3 | 89 | clocks = <&clks 25>; |
bc3a59c1 DA |
90 | }; |
91 | ||
296f8cd3 | 92 | perfmon: perfmon@80006000 { |
0f06cde7 | 93 | reg = <0x80006000 0x800>; |
bc3a59c1 DA |
94 | interrupts = <27>; |
95 | status = "disabled"; | |
96 | }; | |
97 | ||
296f8cd3 | 98 | gpmi: gpmi-nand@8000c000 { |
7a8e5149 HS |
99 | compatible = "fsl,imx28-gpmi-nand"; |
100 | #address-cells = <1>; | |
101 | #size-cells = <1>; | |
0f06cde7 | 102 | reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; |
7a8e5149 | 103 | reg-names = "gpmi-nand", "bch"; |
7f2b9288 SG |
104 | interrupts = <41>; |
105 | interrupt-names = "bch"; | |
b598b9f3 | 106 | clocks = <&clks 50>; |
b6442559 | 107 | clock-names = "gpmi_io"; |
f30fb03d SG |
108 | dmas = <&dma_apbh 4>; |
109 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
110 | status = "disabled"; |
111 | }; | |
112 | ||
113 | ssp0: ssp@80010000 { | |
41bf5706 MR |
114 | #address-cells = <1>; |
115 | #size-cells = <0>; | |
0f06cde7 | 116 | reg = <0x80010000 0x2000>; |
7f2b9288 | 117 | interrupts = <96>; |
b598b9f3 | 118 | clocks = <&clks 46>; |
f30fb03d SG |
119 | dmas = <&dma_apbh 0>; |
120 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
121 | status = "disabled"; |
122 | }; | |
123 | ||
124 | ssp1: ssp@80012000 { | |
41bf5706 MR |
125 | #address-cells = <1>; |
126 | #size-cells = <0>; | |
0f06cde7 | 127 | reg = <0x80012000 0x2000>; |
7f2b9288 | 128 | interrupts = <97>; |
b598b9f3 | 129 | clocks = <&clks 47>; |
f30fb03d SG |
130 | dmas = <&dma_apbh 1>; |
131 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
132 | status = "disabled"; |
133 | }; | |
134 | ||
135 | ssp2: ssp@80014000 { | |
41bf5706 MR |
136 | #address-cells = <1>; |
137 | #size-cells = <0>; | |
0f06cde7 | 138 | reg = <0x80014000 0x2000>; |
7f2b9288 | 139 | interrupts = <98>; |
b598b9f3 | 140 | clocks = <&clks 48>; |
f30fb03d SG |
141 | dmas = <&dma_apbh 2>; |
142 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
143 | status = "disabled"; |
144 | }; | |
145 | ||
146 | ssp3: ssp@80016000 { | |
41bf5706 MR |
147 | #address-cells = <1>; |
148 | #size-cells = <0>; | |
0f06cde7 | 149 | reg = <0x80016000 0x2000>; |
7f2b9288 | 150 | interrupts = <99>; |
b598b9f3 | 151 | clocks = <&clks 49>; |
f30fb03d SG |
152 | dmas = <&dma_apbh 3>; |
153 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
154 | status = "disabled"; |
155 | }; | |
156 | ||
296f8cd3 | 157 | pinctrl: pinctrl@80018000 { |
bc3a59c1 DA |
158 | #address-cells = <1>; |
159 | #size-cells = <0>; | |
ce4c6f9b | 160 | compatible = "fsl,imx28-pinctrl", "simple-bus"; |
0f06cde7 | 161 | reg = <0x80018000 0x2000>; |
bc3a59c1 | 162 | |
ce4c6f9b SG |
163 | gpio0: gpio@0 { |
164 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
165 | interrupts = <127>; | |
166 | gpio-controller; | |
167 | #gpio-cells = <2>; | |
168 | interrupt-controller; | |
169 | #interrupt-cells = <2>; | |
170 | }; | |
171 | ||
172 | gpio1: gpio@1 { | |
173 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
174 | interrupts = <126>; | |
175 | gpio-controller; | |
176 | #gpio-cells = <2>; | |
177 | interrupt-controller; | |
178 | #interrupt-cells = <2>; | |
179 | }; | |
180 | ||
181 | gpio2: gpio@2 { | |
182 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
183 | interrupts = <125>; | |
184 | gpio-controller; | |
185 | #gpio-cells = <2>; | |
186 | interrupt-controller; | |
187 | #interrupt-cells = <2>; | |
188 | }; | |
189 | ||
190 | gpio3: gpio@3 { | |
191 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
192 | interrupts = <124>; | |
193 | gpio-controller; | |
194 | #gpio-cells = <2>; | |
195 | interrupt-controller; | |
196 | #interrupt-cells = <2>; | |
197 | }; | |
198 | ||
199 | gpio4: gpio@4 { | |
200 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; | |
201 | interrupts = <123>; | |
202 | gpio-controller; | |
203 | #gpio-cells = <2>; | |
204 | interrupt-controller; | |
205 | #interrupt-cells = <2>; | |
206 | }; | |
207 | ||
bc3a59c1 DA |
208 | duart_pins_a: duart@0 { |
209 | reg = <0>; | |
f14da767 | 210 | fsl,pinmux-ids = < |
bc3875f1 LW |
211 | MX28_PAD_PWM0__DUART_RX |
212 | MX28_PAD_PWM1__DUART_TX | |
f14da767 | 213 | >; |
4191c340 LW |
214 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
215 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
216 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
bc3a59c1 DA |
217 | }; |
218 | ||
8385e7c1 MR |
219 | duart_pins_b: duart@1 { |
220 | reg = <1>; | |
f14da767 | 221 | fsl,pinmux-ids = < |
bc3875f1 LW |
222 | MX28_PAD_AUART0_CTS__DUART_RX |
223 | MX28_PAD_AUART0_RTS__DUART_TX | |
f14da767 | 224 | >; |
4191c340 LW |
225 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
226 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
227 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
8385e7c1 MR |
228 | }; |
229 | ||
e1a4d18f SG |
230 | duart_4pins_a: duart-4pins@0 { |
231 | reg = <0>; | |
232 | fsl,pinmux-ids = < | |
bc3875f1 LW |
233 | MX28_PAD_AUART0_CTS__DUART_RX |
234 | MX28_PAD_AUART0_RTS__DUART_TX | |
235 | MX28_PAD_AUART0_RX__DUART_CTS | |
236 | MX28_PAD_AUART0_TX__DUART_RTS | |
e1a4d18f | 237 | >; |
4191c340 LW |
238 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
239 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
240 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
e1a4d18f SG |
241 | }; |
242 | ||
7a8e5149 HS |
243 | gpmi_pins_a: gpmi-nand@0 { |
244 | reg = <0>; | |
f14da767 | 245 | fsl,pinmux-ids = < |
bc3875f1 LW |
246 | MX28_PAD_GPMI_D00__GPMI_D0 |
247 | MX28_PAD_GPMI_D01__GPMI_D1 | |
248 | MX28_PAD_GPMI_D02__GPMI_D2 | |
249 | MX28_PAD_GPMI_D03__GPMI_D3 | |
250 | MX28_PAD_GPMI_D04__GPMI_D4 | |
251 | MX28_PAD_GPMI_D05__GPMI_D5 | |
252 | MX28_PAD_GPMI_D06__GPMI_D6 | |
253 | MX28_PAD_GPMI_D07__GPMI_D7 | |
254 | MX28_PAD_GPMI_CE0N__GPMI_CE0N | |
255 | MX28_PAD_GPMI_RDY0__GPMI_READY0 | |
256 | MX28_PAD_GPMI_RDN__GPMI_RDN | |
257 | MX28_PAD_GPMI_WRN__GPMI_WRN | |
258 | MX28_PAD_GPMI_ALE__GPMI_ALE | |
259 | MX28_PAD_GPMI_CLE__GPMI_CLE | |
260 | MX28_PAD_GPMI_RESETN__GPMI_RESETN | |
f14da767 | 261 | >; |
4191c340 LW |
262 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
263 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
264 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
7a8e5149 HS |
265 | }; |
266 | ||
267 | gpmi_status_cfg: gpmi-status-cfg { | |
f14da767 | 268 | fsl,pinmux-ids = < |
bc3875f1 LW |
269 | MX28_PAD_GPMI_RDN__GPMI_RDN |
270 | MX28_PAD_GPMI_WRN__GPMI_WRN | |
271 | MX28_PAD_GPMI_RESETN__GPMI_RESETN | |
f14da767 | 272 | >; |
4191c340 | 273 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
7a8e5149 HS |
274 | }; |
275 | ||
80d969e4 FE |
276 | auart0_pins_a: auart0@0 { |
277 | reg = <0>; | |
f14da767 | 278 | fsl,pinmux-ids = < |
bc3875f1 LW |
279 | MX28_PAD_AUART0_RX__AUART0_RX |
280 | MX28_PAD_AUART0_TX__AUART0_TX | |
281 | MX28_PAD_AUART0_CTS__AUART0_CTS | |
282 | MX28_PAD_AUART0_RTS__AUART0_RTS | |
f14da767 | 283 | >; |
4191c340 LW |
284 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
285 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
286 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
8fa62e11 MV |
287 | }; |
288 | ||
289 | auart0_2pins_a: auart0-2pins@0 { | |
290 | reg = <0>; | |
291 | fsl,pinmux-ids = < | |
bc3875f1 LW |
292 | MX28_PAD_AUART0_RX__AUART0_RX |
293 | MX28_PAD_AUART0_TX__AUART0_TX | |
8fa62e11 | 294 | >; |
4191c340 LW |
295 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
296 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
297 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
80d969e4 FE |
298 | }; |
299 | ||
e1a4d18f SG |
300 | auart1_pins_a: auart1@0 { |
301 | reg = <0>; | |
302 | fsl,pinmux-ids = < | |
bc3875f1 LW |
303 | MX28_PAD_AUART1_RX__AUART1_RX |
304 | MX28_PAD_AUART1_TX__AUART1_TX | |
305 | MX28_PAD_AUART1_CTS__AUART1_CTS | |
306 | MX28_PAD_AUART1_RTS__AUART1_RTS | |
e1a4d18f | 307 | >; |
4191c340 LW |
308 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
309 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
310 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
e1a4d18f SG |
311 | }; |
312 | ||
3143bbb4 SG |
313 | auart1_2pins_a: auart1-2pins@0 { |
314 | reg = <0>; | |
315 | fsl,pinmux-ids = < | |
bc3875f1 LW |
316 | MX28_PAD_AUART1_RX__AUART1_RX |
317 | MX28_PAD_AUART1_TX__AUART1_TX | |
3143bbb4 | 318 | >; |
4191c340 LW |
319 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
320 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
321 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
3143bbb4 SG |
322 | }; |
323 | ||
324 | auart2_2pins_a: auart2-2pins@0 { | |
325 | reg = <0>; | |
326 | fsl,pinmux-ids = < | |
bc3875f1 LW |
327 | MX28_PAD_SSP2_SCK__AUART2_RX |
328 | MX28_PAD_SSP2_MOSI__AUART2_TX | |
3143bbb4 | 329 | >; |
4191c340 LW |
330 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
331 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
332 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
3143bbb4 SG |
333 | }; |
334 | ||
f8040cf5 EB |
335 | auart2_2pins_b: auart2-2pins@1 { |
336 | reg = <1>; | |
337 | fsl,pinmux-ids = < | |
bc3875f1 LW |
338 | MX28_PAD_AUART2_RX__AUART2_RX |
339 | MX28_PAD_AUART2_TX__AUART2_TX | |
f8040cf5 | 340 | >; |
4191c340 LW |
341 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
342 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
343 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
f8040cf5 EB |
344 | }; |
345 | ||
80d969e4 FE |
346 | auart3_pins_a: auart3@0 { |
347 | reg = <0>; | |
f14da767 | 348 | fsl,pinmux-ids = < |
bc3875f1 LW |
349 | MX28_PAD_AUART3_RX__AUART3_RX |
350 | MX28_PAD_AUART3_TX__AUART3_TX | |
351 | MX28_PAD_AUART3_CTS__AUART3_CTS | |
352 | MX28_PAD_AUART3_RTS__AUART3_RTS | |
f14da767 | 353 | >; |
4191c340 LW |
354 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
355 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
356 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
80d969e4 FE |
357 | }; |
358 | ||
3143bbb4 SG |
359 | auart3_2pins_a: auart3-2pins@0 { |
360 | reg = <0>; | |
361 | fsl,pinmux-ids = < | |
bc3875f1 LW |
362 | MX28_PAD_SSP2_MISO__AUART3_RX |
363 | MX28_PAD_SSP2_SS0__AUART3_TX | |
3143bbb4 | 364 | >; |
4191c340 LW |
365 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
366 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
367 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
3143bbb4 SG |
368 | }; |
369 | ||
4812e746 EB |
370 | auart3_2pins_b: auart3-2pins@1 { |
371 | reg = <1>; | |
372 | fsl,pinmux-ids = < | |
bc3875f1 LW |
373 | MX28_PAD_AUART3_RX__AUART3_RX |
374 | MX28_PAD_AUART3_TX__AUART3_TX | |
4812e746 | 375 | >; |
4191c340 LW |
376 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
377 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
378 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
4812e746 EB |
379 | }; |
380 | ||
33678d12 EB |
381 | auart4_2pins_a: auart4@0 { |
382 | reg = <0>; | |
383 | fsl,pinmux-ids = < | |
bc3875f1 LW |
384 | MX28_PAD_SSP3_SCK__AUART4_TX |
385 | MX28_PAD_SSP3_MOSI__AUART4_RX | |
33678d12 | 386 | >; |
4191c340 LW |
387 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
388 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
389 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
33678d12 EB |
390 | }; |
391 | ||
bc3a59c1 DA |
392 | mac0_pins_a: mac0@0 { |
393 | reg = <0>; | |
f14da767 | 394 | fsl,pinmux-ids = < |
bc3875f1 LW |
395 | MX28_PAD_ENET0_MDC__ENET0_MDC |
396 | MX28_PAD_ENET0_MDIO__ENET0_MDIO | |
397 | MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | |
398 | MX28_PAD_ENET0_RXD0__ENET0_RXD0 | |
399 | MX28_PAD_ENET0_RXD1__ENET0_RXD1 | |
400 | MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | |
401 | MX28_PAD_ENET0_TXD0__ENET0_TXD0 | |
402 | MX28_PAD_ENET0_TXD1__ENET0_TXD1 | |
403 | MX28_PAD_ENET_CLK__CLKCTRL_ENET | |
f14da767 | 404 | >; |
4191c340 LW |
405 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
406 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
407 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
bc3a59c1 DA |
408 | }; |
409 | ||
410 | mac1_pins_a: mac1@0 { | |
411 | reg = <0>; | |
f14da767 | 412 | fsl,pinmux-ids = < |
bc3875f1 LW |
413 | MX28_PAD_ENET0_CRS__ENET1_RX_EN |
414 | MX28_PAD_ENET0_RXD2__ENET1_RXD0 | |
415 | MX28_PAD_ENET0_RXD3__ENET1_RXD1 | |
416 | MX28_PAD_ENET0_COL__ENET1_TX_EN | |
417 | MX28_PAD_ENET0_TXD2__ENET1_TXD0 | |
418 | MX28_PAD_ENET0_TXD3__ENET1_TXD1 | |
f14da767 | 419 | >; |
4191c340 LW |
420 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
421 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
422 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
bc3a59c1 | 423 | }; |
35d23047 SG |
424 | |
425 | mmc0_8bit_pins_a: mmc0-8bit@0 { | |
426 | reg = <0>; | |
f14da767 | 427 | fsl,pinmux-ids = < |
bc3875f1 LW |
428 | MX28_PAD_SSP0_DATA0__SSP0_D0 |
429 | MX28_PAD_SSP0_DATA1__SSP0_D1 | |
430 | MX28_PAD_SSP0_DATA2__SSP0_D2 | |
431 | MX28_PAD_SSP0_DATA3__SSP0_D3 | |
432 | MX28_PAD_SSP0_DATA4__SSP0_D4 | |
433 | MX28_PAD_SSP0_DATA5__SSP0_D5 | |
434 | MX28_PAD_SSP0_DATA6__SSP0_D6 | |
435 | MX28_PAD_SSP0_DATA7__SSP0_D7 | |
436 | MX28_PAD_SSP0_CMD__SSP0_CMD | |
437 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | |
438 | MX28_PAD_SSP0_SCK__SSP0_SCK | |
f14da767 | 439 | >; |
4191c340 LW |
440 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
441 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
442 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
35d23047 SG |
443 | }; |
444 | ||
8385e7c1 MR |
445 | mmc0_4bit_pins_a: mmc0-4bit@0 { |
446 | reg = <0>; | |
f14da767 | 447 | fsl,pinmux-ids = < |
bc3875f1 LW |
448 | MX28_PAD_SSP0_DATA0__SSP0_D0 |
449 | MX28_PAD_SSP0_DATA1__SSP0_D1 | |
450 | MX28_PAD_SSP0_DATA2__SSP0_D2 | |
451 | MX28_PAD_SSP0_DATA3__SSP0_D3 | |
452 | MX28_PAD_SSP0_CMD__SSP0_CMD | |
453 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | |
454 | MX28_PAD_SSP0_SCK__SSP0_SCK | |
f14da767 | 455 | >; |
4191c340 LW |
456 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
457 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
458 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
8385e7c1 MR |
459 | }; |
460 | ||
35d23047 | 461 | mmc0_cd_cfg: mmc0-cd-cfg { |
f14da767 | 462 | fsl,pinmux-ids = < |
bc3875f1 | 463 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
f14da767 | 464 | >; |
4191c340 | 465 | fsl,pull-up = <MXS_PULL_DISABLE>; |
35d23047 SG |
466 | }; |
467 | ||
468 | mmc0_sck_cfg: mmc0-sck-cfg { | |
f14da767 | 469 | fsl,pinmux-ids = < |
bc3875f1 | 470 | MX28_PAD_SSP0_SCK__SSP0_SCK |
f14da767 | 471 | >; |
4191c340 LW |
472 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
473 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
35d23047 | 474 | }; |
2a96e391 SG |
475 | |
476 | i2c0_pins_a: i2c0@0 { | |
477 | reg = <0>; | |
f14da767 | 478 | fsl,pinmux-ids = < |
bc3875f1 LW |
479 | MX28_PAD_I2C0_SCL__I2C0_SCL |
480 | MX28_PAD_I2C0_SDA__I2C0_SDA | |
f14da767 | 481 | >; |
4191c340 LW |
482 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
483 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
484 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
2a96e391 | 485 | }; |
530f1d41 | 486 | |
5c697ea2 MR |
487 | i2c0_pins_b: i2c0@1 { |
488 | reg = <1>; | |
489 | fsl,pinmux-ids = < | |
bc3875f1 LW |
490 | MX28_PAD_AUART0_RX__I2C0_SCL |
491 | MX28_PAD_AUART0_TX__I2C0_SDA | |
5c697ea2 | 492 | >; |
4191c340 LW |
493 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
494 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
495 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
5c697ea2 MR |
496 | }; |
497 | ||
de7e934f MR |
498 | i2c1_pins_a: i2c1@0 { |
499 | reg = <0>; | |
500 | fsl,pinmux-ids = < | |
bc3875f1 LW |
501 | MX28_PAD_PWM0__I2C1_SCL |
502 | MX28_PAD_PWM1__I2C1_SDA | |
de7e934f | 503 | >; |
4191c340 LW |
504 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
505 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
506 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
de7e934f MR |
507 | }; |
508 | ||
530f1d41 SG |
509 | saif0_pins_a: saif0@0 { |
510 | reg = <0>; | |
f14da767 | 511 | fsl,pinmux-ids = < |
bc3875f1 LW |
512 | MX28_PAD_SAIF0_MCLK__SAIF0_MCLK |
513 | MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK | |
514 | MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK | |
515 | MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 | |
f14da767 | 516 | >; |
4191c340 LW |
517 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
518 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
519 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
530f1d41 SG |
520 | }; |
521 | ||
2e1dd9fc LW |
522 | saif0_pins_b: saif0@1 { |
523 | reg = <1>; | |
524 | fsl,pinmux-ids = < | |
bc3875f1 LW |
525 | MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK |
526 | MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK | |
527 | MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 | |
2e1dd9fc | 528 | >; |
4191c340 LW |
529 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
530 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
531 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
2e1dd9fc LW |
532 | }; |
533 | ||
530f1d41 SG |
534 | saif1_pins_a: saif1@0 { |
535 | reg = <0>; | |
f14da767 | 536 | fsl,pinmux-ids = < |
bc3875f1 | 537 | MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
f14da767 | 538 | >; |
4191c340 LW |
539 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
540 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
541 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
530f1d41 | 542 | }; |
52f7176b | 543 | |
e1a4d18f SG |
544 | pwm0_pins_a: pwm0@0 { |
545 | reg = <0>; | |
546 | fsl,pinmux-ids = < | |
bc3875f1 | 547 | MX28_PAD_PWM0__PWM_0 |
e1a4d18f | 548 | >; |
4191c340 LW |
549 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
550 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
551 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
e1a4d18f SG |
552 | }; |
553 | ||
52f7176b SG |
554 | pwm2_pins_a: pwm2@0 { |
555 | reg = <0>; | |
556 | fsl,pinmux-ids = < | |
bc3875f1 | 557 | MX28_PAD_PWM2__PWM_2 |
52f7176b | 558 | >; |
4191c340 LW |
559 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
560 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
561 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
52f7176b | 562 | }; |
a915ee42 | 563 | |
2bde51cb JB |
564 | pwm3_pins_a: pwm3@0 { |
565 | reg = <0>; | |
566 | fsl,pinmux-ids = < | |
bc3875f1 | 567 | MX28_PAD_PWM3__PWM_3 |
2bde51cb | 568 | >; |
4191c340 LW |
569 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
570 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
571 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
2bde51cb JB |
572 | }; |
573 | ||
d248620c MR |
574 | pwm3_pins_b: pwm3@1 { |
575 | reg = <1>; | |
576 | fsl,pinmux-ids = < | |
bc3875f1 | 577 | MX28_PAD_SAIF0_MCLK__PWM_3 |
d248620c | 578 | >; |
4191c340 LW |
579 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
580 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
581 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
d248620c MR |
582 | }; |
583 | ||
2f44211f MR |
584 | pwm4_pins_a: pwm4@0 { |
585 | reg = <0>; | |
586 | fsl,pinmux-ids = < | |
bc3875f1 | 587 | MX28_PAD_PWM4__PWM_4 |
2f44211f | 588 | >; |
4191c340 LW |
589 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
590 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
591 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
2f44211f MR |
592 | }; |
593 | ||
a915ee42 SG |
594 | lcdif_24bit_pins_a: lcdif-24bit@0 { |
595 | reg = <0>; | |
596 | fsl,pinmux-ids = < | |
bc3875f1 LW |
597 | MX28_PAD_LCD_D00__LCD_D0 |
598 | MX28_PAD_LCD_D01__LCD_D1 | |
599 | MX28_PAD_LCD_D02__LCD_D2 | |
600 | MX28_PAD_LCD_D03__LCD_D3 | |
601 | MX28_PAD_LCD_D04__LCD_D4 | |
602 | MX28_PAD_LCD_D05__LCD_D5 | |
603 | MX28_PAD_LCD_D06__LCD_D6 | |
604 | MX28_PAD_LCD_D07__LCD_D7 | |
605 | MX28_PAD_LCD_D08__LCD_D8 | |
606 | MX28_PAD_LCD_D09__LCD_D9 | |
607 | MX28_PAD_LCD_D10__LCD_D10 | |
608 | MX28_PAD_LCD_D11__LCD_D11 | |
609 | MX28_PAD_LCD_D12__LCD_D12 | |
610 | MX28_PAD_LCD_D13__LCD_D13 | |
611 | MX28_PAD_LCD_D14__LCD_D14 | |
612 | MX28_PAD_LCD_D15__LCD_D15 | |
613 | MX28_PAD_LCD_D16__LCD_D16 | |
614 | MX28_PAD_LCD_D17__LCD_D17 | |
615 | MX28_PAD_LCD_D18__LCD_D18 | |
616 | MX28_PAD_LCD_D19__LCD_D19 | |
617 | MX28_PAD_LCD_D20__LCD_D20 | |
618 | MX28_PAD_LCD_D21__LCD_D21 | |
619 | MX28_PAD_LCD_D22__LCD_D22 | |
620 | MX28_PAD_LCD_D23__LCD_D23 | |
a915ee42 | 621 | >; |
4191c340 LW |
622 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
623 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
624 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
a915ee42 | 625 | }; |
6ca44acf | 626 | |
4ced2a40 GGM |
627 | lcdif_16bit_pins_a: lcdif-16bit@0 { |
628 | reg = <0>; | |
629 | fsl,pinmux-ids = < | |
bc3875f1 LW |
630 | MX28_PAD_LCD_D00__LCD_D0 |
631 | MX28_PAD_LCD_D01__LCD_D1 | |
632 | MX28_PAD_LCD_D02__LCD_D2 | |
633 | MX28_PAD_LCD_D03__LCD_D3 | |
634 | MX28_PAD_LCD_D04__LCD_D4 | |
635 | MX28_PAD_LCD_D05__LCD_D5 | |
636 | MX28_PAD_LCD_D06__LCD_D6 | |
637 | MX28_PAD_LCD_D07__LCD_D7 | |
638 | MX28_PAD_LCD_D08__LCD_D8 | |
639 | MX28_PAD_LCD_D09__LCD_D9 | |
640 | MX28_PAD_LCD_D10__LCD_D10 | |
641 | MX28_PAD_LCD_D11__LCD_D11 | |
642 | MX28_PAD_LCD_D12__LCD_D12 | |
643 | MX28_PAD_LCD_D13__LCD_D13 | |
644 | MX28_PAD_LCD_D14__LCD_D14 | |
645 | MX28_PAD_LCD_D15__LCD_D15 | |
4ced2a40 | 646 | >; |
4191c340 LW |
647 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
648 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
649 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
4ced2a40 GGM |
650 | }; |
651 | ||
23ad6f65 LW |
652 | lcdif_sync_pins_a: lcdif-sync@0 { |
653 | reg = <0>; | |
654 | fsl,pinmux-ids = < | |
bc3875f1 LW |
655 | MX28_PAD_LCD_RS__LCD_DOTCLK |
656 | MX28_PAD_LCD_CS__LCD_ENABLE | |
657 | MX28_PAD_LCD_RD_E__LCD_VSYNC | |
658 | MX28_PAD_LCD_WR_RWN__LCD_HSYNC | |
23ad6f65 | 659 | >; |
4191c340 LW |
660 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
661 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
662 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
23ad6f65 LW |
663 | }; |
664 | ||
6ca44acf SG |
665 | can0_pins_a: can0@0 { |
666 | reg = <0>; | |
667 | fsl,pinmux-ids = < | |
bc3875f1 LW |
668 | MX28_PAD_GPMI_RDY2__CAN0_TX |
669 | MX28_PAD_GPMI_RDY3__CAN0_RX | |
6ca44acf | 670 | >; |
4191c340 LW |
671 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
672 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
673 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
6ca44acf SG |
674 | }; |
675 | ||
676 | can1_pins_a: can1@0 { | |
677 | reg = <0>; | |
678 | fsl,pinmux-ids = < | |
bc3875f1 LW |
679 | MX28_PAD_GPMI_CE2N__CAN1_TX |
680 | MX28_PAD_GPMI_CE3N__CAN1_RX | |
6ca44acf | 681 | >; |
4191c340 LW |
682 | fsl,drive-strength = <MXS_DRIVE_4mA>; |
683 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
684 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
6ca44acf | 685 | }; |
7f122213 MV |
686 | |
687 | spi2_pins_a: spi2@0 { | |
688 | reg = <0>; | |
689 | fsl,pinmux-ids = < | |
bc3875f1 LW |
690 | MX28_PAD_SSP2_SCK__SSP2_SCK |
691 | MX28_PAD_SSP2_MOSI__SSP2_CMD | |
692 | MX28_PAD_SSP2_MISO__SSP2_D0 | |
693 | MX28_PAD_SSP2_SS0__SSP2_D3 | |
7f122213 | 694 | >; |
4191c340 LW |
695 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
696 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
697 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
7f122213 | 698 | }; |
bb2f1261 | 699 | |
3314d2be LW |
700 | spi3_pins_a: spi3@0 { |
701 | reg = <0>; | |
702 | fsl,pinmux-ids = < | |
bc3875f1 LW |
703 | MX28_PAD_AUART2_RX__SSP3_D4 |
704 | MX28_PAD_AUART2_TX__SSP3_D5 | |
705 | MX28_PAD_SSP3_SCK__SSP3_SCK | |
706 | MX28_PAD_SSP3_MOSI__SSP3_CMD | |
707 | MX28_PAD_SSP3_MISO__SSP3_D0 | |
708 | MX28_PAD_SSP3_SS0__SSP3_D3 | |
3314d2be | 709 | >; |
4191c340 LW |
710 | fsl,drive-strength = <MXS_DRIVE_8mA>; |
711 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
712 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
3314d2be LW |
713 | }; |
714 | ||
bb2f1261 MV |
715 | usbphy0_pins_a: usbphy0@0 { |
716 | reg = <0>; | |
717 | fsl,pinmux-ids = < | |
bc3875f1 | 718 | MX28_PAD_SSP2_SS2__USB0_OVERCURRENT |
bb2f1261 | 719 | >; |
4191c340 LW |
720 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
721 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
722 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
bb2f1261 MV |
723 | }; |
724 | ||
725 | usbphy0_pins_b: usbphy0@1 { | |
726 | reg = <1>; | |
727 | fsl,pinmux-ids = < | |
bc3875f1 | 728 | MX28_PAD_AUART1_CTS__USB0_OVERCURRENT |
bb2f1261 | 729 | >; |
4191c340 LW |
730 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
731 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
732 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
bb2f1261 MV |
733 | }; |
734 | ||
735 | usbphy1_pins_a: usbphy1@0 { | |
736 | reg = <0>; | |
737 | fsl,pinmux-ids = < | |
bc3875f1 | 738 | MX28_PAD_SSP2_SS1__USB1_OVERCURRENT |
bb2f1261 | 739 | >; |
4191c340 LW |
740 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
741 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
742 | fsl,pull-up = <MXS_PULL_DISABLE>; | |
bb2f1261 | 743 | }; |
69c02f95 FE |
744 | |
745 | usb0_id_pins_a: usb0id@0 { | |
746 | reg = <0>; | |
747 | fsl,pinmux-ids = < | |
e96e1782 | 748 | MX28_PAD_AUART1_RTS__USB0_ID |
69c02f95 | 749 | >; |
e96e1782 LW |
750 | fsl,drive-strength = <MXS_DRIVE_12mA>; |
751 | fsl,voltage = <MXS_VOLTAGE_HIGH>; | |
752 | fsl,pull-up = <MXS_PULL_ENABLE>; | |
69c02f95 | 753 | }; |
bc3a59c1 DA |
754 | }; |
755 | ||
296f8cd3 | 756 | digctl: digctl@8001c000 { |
115581cf | 757 | compatible = "fsl,imx28-digctl", "fsl,imx23-digctl"; |
0f06cde7 | 758 | reg = <0x8001c000 0x2000>; |
bc3a59c1 DA |
759 | interrupts = <89>; |
760 | status = "disabled"; | |
761 | }; | |
762 | ||
296f8cd3 | 763 | etm: etm@80022000 { |
0f06cde7 | 764 | reg = <0x80022000 0x2000>; |
bc3a59c1 DA |
765 | status = "disabled"; |
766 | }; | |
767 | ||
f30fb03d | 768 | dma_apbx: dma-apbx@80024000 { |
84f3570a | 769 | compatible = "fsl,imx28-dma-apbx"; |
0f06cde7 | 770 | reg = <0x80024000 0x2000>; |
f30fb03d SG |
771 | interrupts = <78 79 66 0 |
772 | 80 81 68 69 | |
773 | 70 71 72 73 | |
774 | 74 75 76 77>; | |
775 | interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty", | |
776 | "saif0", "saif1", "i2c0", "i2c1", | |
777 | "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", | |
778 | "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; | |
779 | #dma-cells = <1>; | |
780 | dma-channels = <16>; | |
b598b9f3 | 781 | clocks = <&clks 26>; |
bc3a59c1 DA |
782 | }; |
783 | ||
296f8cd3 | 784 | dcp: dcp@80028000 { |
0f06cde7 | 785 | reg = <0x80028000 0x2000>; |
bc3a59c1 | 786 | interrupts = <52 53 54>; |
519d8b1a | 787 | compatible = "fsl-dcp"; |
bc3a59c1 DA |
788 | }; |
789 | ||
296f8cd3 | 790 | pxp: pxp@8002a000 { |
0f06cde7 | 791 | reg = <0x8002a000 0x2000>; |
bc3a59c1 DA |
792 | interrupts = <39>; |
793 | status = "disabled"; | |
794 | }; | |
795 | ||
296f8cd3 | 796 | ocotp: ocotp@8002c000 { |
69d75a02 | 797 | compatible = "fsl,ocotp"; |
0f06cde7 | 798 | reg = <0x8002c000 0x2000>; |
bc3a59c1 DA |
799 | status = "disabled"; |
800 | }; | |
801 | ||
802 | axi-ahb@8002e000 { | |
0f06cde7 | 803 | reg = <0x8002e000 0x2000>; |
bc3a59c1 DA |
804 | status = "disabled"; |
805 | }; | |
806 | ||
296f8cd3 | 807 | lcdif: lcdif@80030000 { |
a915ee42 | 808 | compatible = "fsl,imx28-lcdif"; |
0f06cde7 | 809 | reg = <0x80030000 0x2000>; |
7f2b9288 | 810 | interrupts = <38>; |
b598b9f3 | 811 | clocks = <&clks 55>; |
f30fb03d SG |
812 | dmas = <&dma_apbh 13>; |
813 | dma-names = "rx"; | |
bc3a59c1 DA |
814 | status = "disabled"; |
815 | }; | |
816 | ||
817 | can0: can@80032000 { | |
6ca44acf | 818 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; |
0f06cde7 | 819 | reg = <0x80032000 0x2000>; |
bc3a59c1 | 820 | interrupts = <8>; |
b598b9f3 SG |
821 | clocks = <&clks 58>, <&clks 58>; |
822 | clock-names = "ipg", "per"; | |
bc3a59c1 DA |
823 | status = "disabled"; |
824 | }; | |
825 | ||
826 | can1: can@80034000 { | |
6ca44acf | 827 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; |
0f06cde7 | 828 | reg = <0x80034000 0x2000>; |
bc3a59c1 | 829 | interrupts = <9>; |
b598b9f3 SG |
830 | clocks = <&clks 59>, <&clks 59>; |
831 | clock-names = "ipg", "per"; | |
bc3a59c1 DA |
832 | status = "disabled"; |
833 | }; | |
834 | ||
296f8cd3 | 835 | simdbg: simdbg@8003c000 { |
0f06cde7 | 836 | reg = <0x8003c000 0x200>; |
bc3a59c1 DA |
837 | status = "disabled"; |
838 | }; | |
839 | ||
296f8cd3 | 840 | simgpmisel: simgpmisel@8003c200 { |
0f06cde7 | 841 | reg = <0x8003c200 0x100>; |
bc3a59c1 DA |
842 | status = "disabled"; |
843 | }; | |
844 | ||
296f8cd3 | 845 | simsspsel: simsspsel@8003c300 { |
0f06cde7 | 846 | reg = <0x8003c300 0x100>; |
bc3a59c1 DA |
847 | status = "disabled"; |
848 | }; | |
849 | ||
296f8cd3 | 850 | simmemsel: simmemsel@8003c400 { |
0f06cde7 | 851 | reg = <0x8003c400 0x100>; |
bc3a59c1 DA |
852 | status = "disabled"; |
853 | }; | |
854 | ||
296f8cd3 | 855 | gpiomon: gpiomon@8003c500 { |
0f06cde7 | 856 | reg = <0x8003c500 0x100>; |
bc3a59c1 DA |
857 | status = "disabled"; |
858 | }; | |
859 | ||
296f8cd3 | 860 | simenet: simenet@8003c700 { |
0f06cde7 | 861 | reg = <0x8003c700 0x100>; |
bc3a59c1 DA |
862 | status = "disabled"; |
863 | }; | |
864 | ||
296f8cd3 | 865 | armjtag: armjtag@8003c800 { |
0f06cde7 | 866 | reg = <0x8003c800 0x100>; |
bc3a59c1 DA |
867 | status = "disabled"; |
868 | }; | |
07a3ce7f | 869 | }; |
bc3a59c1 DA |
870 | |
871 | apbx@80040000 { | |
872 | compatible = "simple-bus"; | |
873 | #address-cells = <1>; | |
874 | #size-cells = <1>; | |
875 | reg = <0x80040000 0x40000>; | |
876 | ranges; | |
877 | ||
b598b9f3 | 878 | clks: clkctrl@80040000 { |
8f7cf881 | 879 | compatible = "fsl,imx28-clkctrl", "fsl,clkctrl"; |
0f06cde7 | 880 | reg = <0x80040000 0x2000>; |
b598b9f3 | 881 | #clock-cells = <1>; |
bc3a59c1 DA |
882 | }; |
883 | ||
884 | saif0: saif@80042000 { | |
530f1d41 | 885 | compatible = "fsl,imx28-saif"; |
0f06cde7 | 886 | reg = <0x80042000 0x2000>; |
7f2b9288 | 887 | interrupts = <59>; |
66acaf3f | 888 | #clock-cells = <0>; |
b598b9f3 | 889 | clocks = <&clks 53>; |
f30fb03d SG |
890 | dmas = <&dma_apbx 4>; |
891 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
892 | status = "disabled"; |
893 | }; | |
894 | ||
296f8cd3 | 895 | power: power@80044000 { |
0f06cde7 | 896 | reg = <0x80044000 0x2000>; |
bc3a59c1 DA |
897 | status = "disabled"; |
898 | }; | |
899 | ||
900 | saif1: saif@80046000 { | |
530f1d41 | 901 | compatible = "fsl,imx28-saif"; |
0f06cde7 | 902 | reg = <0x80046000 0x2000>; |
7f2b9288 | 903 | interrupts = <58>; |
b598b9f3 | 904 | clocks = <&clks 54>; |
f30fb03d SG |
905 | dmas = <&dma_apbx 5>; |
906 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
907 | status = "disabled"; |
908 | }; | |
909 | ||
296f8cd3 | 910 | lradc: lradc@80050000 { |
aef35104 | 911 | compatible = "fsl,imx28-lradc"; |
0f06cde7 | 912 | reg = <0x80050000 0x2000>; |
aef35104 MV |
913 | interrupts = <10 14 15 16 17 18 19 |
914 | 20 21 22 23 24 25>; | |
bc3a59c1 DA |
915 | status = "disabled"; |
916 | }; | |
917 | ||
296f8cd3 | 918 | spdif: spdif@80054000 { |
0f06cde7 | 919 | reg = <0x80054000 0x2000>; |
7f2b9288 | 920 | interrupts = <45>; |
f30fb03d SG |
921 | dmas = <&dma_apbx 2>; |
922 | dma-names = "tx"; | |
bc3a59c1 DA |
923 | status = "disabled"; |
924 | }; | |
925 | ||
296f8cd3 | 926 | mxs_rtc: rtc@80056000 { |
f98c990c | 927 | compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; |
0f06cde7 | 928 | reg = <0x80056000 0x2000>; |
f98c990c | 929 | interrupts = <29>; |
bc3a59c1 DA |
930 | }; |
931 | ||
932 | i2c0: i2c@80058000 { | |
2a96e391 SG |
933 | #address-cells = <1>; |
934 | #size-cells = <0>; | |
935 | compatible = "fsl,imx28-i2c"; | |
0f06cde7 | 936 | reg = <0x80058000 0x2000>; |
7f2b9288 | 937 | interrupts = <111>; |
cd4f2d4a | 938 | clock-frequency = <100000>; |
f30fb03d SG |
939 | dmas = <&dma_apbx 6>; |
940 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
941 | status = "disabled"; |
942 | }; | |
943 | ||
944 | i2c1: i2c@8005a000 { | |
2a96e391 SG |
945 | #address-cells = <1>; |
946 | #size-cells = <0>; | |
947 | compatible = "fsl,imx28-i2c"; | |
0f06cde7 | 948 | reg = <0x8005a000 0x2000>; |
7f2b9288 | 949 | interrupts = <110>; |
cd4f2d4a | 950 | clock-frequency = <100000>; |
f30fb03d SG |
951 | dmas = <&dma_apbx 7>; |
952 | dma-names = "rx-tx"; | |
bc3a59c1 DA |
953 | status = "disabled"; |
954 | }; | |
955 | ||
52f7176b SG |
956 | pwm: pwm@80064000 { |
957 | compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; | |
0f06cde7 | 958 | reg = <0x80064000 0x2000>; |
b598b9f3 | 959 | clocks = <&clks 44>; |
52f7176b SG |
960 | #pwm-cells = <2>; |
961 | fsl,pwm-number = <8>; | |
bc3a59c1 DA |
962 | status = "disabled"; |
963 | }; | |
964 | ||
296f8cd3 | 965 | timer: timrot@80068000 { |
eeca6e60 | 966 | compatible = "fsl,imx28-timrot", "fsl,timrot"; |
0f06cde7 | 967 | reg = <0x80068000 0x2000>; |
eeca6e60 | 968 | interrupts = <48 49 50 51>; |
2efb9504 | 969 | clocks = <&clks 26>; |
bc3a59c1 DA |
970 | }; |
971 | ||
972 | auart0: serial@8006a000 { | |
80d969e4 | 973 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 | 974 | reg = <0x8006a000 0x2000>; |
7f2b9288 | 975 | interrupts = <112>; |
f30fb03d SG |
976 | dmas = <&dma_apbx 8>, <&dma_apbx 9>; |
977 | dma-names = "rx", "tx"; | |
b598b9f3 | 978 | clocks = <&clks 45>; |
bc3a59c1 DA |
979 | status = "disabled"; |
980 | }; | |
981 | ||
982 | auart1: serial@8006c000 { | |
80d969e4 | 983 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 | 984 | reg = <0x8006c000 0x2000>; |
7f2b9288 | 985 | interrupts = <113>; |
f30fb03d SG |
986 | dmas = <&dma_apbx 10>, <&dma_apbx 11>; |
987 | dma-names = "rx", "tx"; | |
b598b9f3 | 988 | clocks = <&clks 45>; |
bc3a59c1 DA |
989 | status = "disabled"; |
990 | }; | |
991 | ||
992 | auart2: serial@8006e000 { | |
80d969e4 | 993 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 | 994 | reg = <0x8006e000 0x2000>; |
7f2b9288 | 995 | interrupts = <114>; |
f30fb03d SG |
996 | dmas = <&dma_apbx 12>, <&dma_apbx 13>; |
997 | dma-names = "rx", "tx"; | |
b598b9f3 | 998 | clocks = <&clks 45>; |
bc3a59c1 DA |
999 | status = "disabled"; |
1000 | }; | |
1001 | ||
1002 | auart3: serial@80070000 { | |
80d969e4 | 1003 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 | 1004 | reg = <0x80070000 0x2000>; |
7f2b9288 | 1005 | interrupts = <115>; |
f30fb03d SG |
1006 | dmas = <&dma_apbx 14>, <&dma_apbx 15>; |
1007 | dma-names = "rx", "tx"; | |
b598b9f3 | 1008 | clocks = <&clks 45>; |
bc3a59c1 DA |
1009 | status = "disabled"; |
1010 | }; | |
1011 | ||
1012 | auart4: serial@80072000 { | |
80d969e4 | 1013 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
bc3a59c1 | 1014 | reg = <0x80072000 0x2000>; |
7f2b9288 | 1015 | interrupts = <116>; |
f30fb03d SG |
1016 | dmas = <&dma_apbx 0>, <&dma_apbx 1>; |
1017 | dma-names = "rx", "tx"; | |
b598b9f3 | 1018 | clocks = <&clks 45>; |
bc3a59c1 DA |
1019 | status = "disabled"; |
1020 | }; | |
1021 | ||
1022 | duart: serial@80074000 { | |
1023 | compatible = "arm,pl011", "arm,primecell"; | |
1024 | reg = <0x80074000 0x1000>; | |
1025 | interrupts = <47>; | |
b598b9f3 SG |
1026 | clocks = <&clks 45>, <&clks 26>; |
1027 | clock-names = "uart", "apb_pclk"; | |
bc3a59c1 DA |
1028 | status = "disabled"; |
1029 | }; | |
1030 | ||
1031 | usbphy0: usbphy@8007c000 { | |
5da01270 | 1032 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; |
bc3a59c1 | 1033 | reg = <0x8007c000 0x2000>; |
b598b9f3 | 1034 | clocks = <&clks 62>; |
bc3a59c1 DA |
1035 | status = "disabled"; |
1036 | }; | |
1037 | ||
1038 | usbphy1: usbphy@8007e000 { | |
5da01270 | 1039 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; |
bc3a59c1 | 1040 | reg = <0x8007e000 0x2000>; |
b598b9f3 | 1041 | clocks = <&clks 63>; |
bc3a59c1 DA |
1042 | status = "disabled"; |
1043 | }; | |
1044 | }; | |
1045 | }; | |
1046 | ||
1047 | ahb@80080000 { | |
1048 | compatible = "simple-bus"; | |
1049 | #address-cells = <1>; | |
1050 | #size-cells = <1>; | |
1051 | reg = <0x80080000 0x80000>; | |
1052 | ranges; | |
1053 | ||
5da01270 RZ |
1054 | usb0: usb@80080000 { |
1055 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; | |
bc3a59c1 | 1056 | reg = <0x80080000 0x10000>; |
5da01270 | 1057 | interrupts = <93>; |
b598b9f3 | 1058 | clocks = <&clks 60>; |
5da01270 | 1059 | fsl,usbphy = <&usbphy0>; |
bc3a59c1 DA |
1060 | status = "disabled"; |
1061 | }; | |
1062 | ||
5da01270 RZ |
1063 | usb1: usb@80090000 { |
1064 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; | |
bc3a59c1 | 1065 | reg = <0x80090000 0x10000>; |
5da01270 | 1066 | interrupts = <92>; |
b598b9f3 | 1067 | clocks = <&clks 61>; |
5da01270 | 1068 | fsl,usbphy = <&usbphy1>; |
bc3a59c1 DA |
1069 | status = "disabled"; |
1070 | }; | |
1071 | ||
296f8cd3 | 1072 | dflpt: dflpt@800c0000 { |
bc3a59c1 DA |
1073 | reg = <0x800c0000 0x10000>; |
1074 | status = "disabled"; | |
1075 | }; | |
1076 | ||
1077 | mac0: ethernet@800f0000 { | |
1078 | compatible = "fsl,imx28-fec"; | |
1079 | reg = <0x800f0000 0x4000>; | |
1080 | interrupts = <101>; | |
f231a9fe WS |
1081 | clocks = <&clks 57>, <&clks 57>, <&clks 64>; |
1082 | clock-names = "ipg", "ahb", "enet_out"; | |
bc3a59c1 DA |
1083 | status = "disabled"; |
1084 | }; | |
1085 | ||
1086 | mac1: ethernet@800f4000 { | |
1087 | compatible = "fsl,imx28-fec"; | |
1088 | reg = <0x800f4000 0x4000>; | |
1089 | interrupts = <102>; | |
b598b9f3 SG |
1090 | clocks = <&clks 57>, <&clks 57>; |
1091 | clock-names = "ipg", "ahb"; | |
bc3a59c1 DA |
1092 | status = "disabled"; |
1093 | }; | |
1094 | ||
296f8cd3 | 1095 | etn_switch: switch@800f8000 { |
bc3a59c1 DA |
1096 | reg = <0x800f8000 0x8000>; |
1097 | status = "disabled"; | |
1098 | }; | |
bc3a59c1 DA |
1099 | }; |
1100 | }; |