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pinctrl: pinctrl-mxs: document the missing pull-ups
[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / imx28.dtsi
CommitLineData
bc3a59c1
DA		 1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
ce4c6f9b
SG		 17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 gpio3 = &gpio3;
22 gpio4 = &gpio4;
530f1d41
SG		 23 saif0 = &saif0;
24 saif1 = &saif1;
80d969e4
FE		 25 serial0 = &auart0;
26 serial1 = &auart1;
27 serial2 = &auart2;
28 serial3 = &auart3;
29 serial4 = &auart4;
8c41d573
MV		 30 ethernet0 = &mac0;
31 ethernet1 = &mac1;
ce4c6f9b
SG		 32 };
33
bc3a59c1
DA		 34 cpus {
35 cpu@0 {
36 compatible = "arm,arm926ejs";
37 };
38 };
39
40 apb@80000000 {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
44 reg = <0x80000000 0x80000>;
45 ranges;
46
47 apbh@80000000 {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 reg = <0x80000000 0x3c900>;
52 ranges;
53
54 icoll: interrupt-controller@80000000 {
83a84efc 55 compatible = "fsl,imx28-icoll", "fsl,icoll";
bc3a59c1
DA		 56 interrupt-controller;
57 #interrupt-cells = <1>;
58 reg = <0x80000000 0x2000>;
59 };
60
61 hsadc@80002000 {
0f06cde7 62 reg = <0x80002000 0x2000>;
bc3a59c1
DA		 63 interrupts = <13 87>;
64 status = "disabled";
65 };
66
67 dma-apbh@80004000 {
84f3570a 68 compatible = "fsl,imx28-dma-apbh";
0f06cde7 69 reg = <0x80004000 0x2000>;
b598b9f3 70 clocks = <&clks 25>;
bc3a59c1
DA		 71 };
72
73 perfmon@80006000 {
0f06cde7 74 reg = <0x80006000 0x800>;
bc3a59c1
DA		 75 interrupts = <27>;
76 status = "disabled";
77 };
78
7a8e5149
HS		 79 gpmi-nand@8000c000 {
80 compatible = "fsl,imx28-gpmi-nand";
81 #address-cells = <1>;
82 #size-cells = <1>;
0f06cde7 83 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
7a8e5149
HS		 84 reg-names = "gpmi-nand", "bch";
85 interrupts = <88>, <41>;
86 interrupt-names = "gpmi-dma", "bch";
b598b9f3 87 clocks = <&clks 50>;
b6442559 88 clock-names = "gpmi_io";
7a8e5149 89 fsl,gpmi-dma-channel = <4>;
bc3a59c1
DA		 90 status = "disabled";
91 };
92
93 ssp0: ssp@80010000 {
41bf5706
MR		 94 #address-cells = <1>;
95 #size-cells = <0>;
0f06cde7 96 reg = <0x80010000 0x2000>;
bc3a59c1 97 interrupts = <96 82>;
b598b9f3 98 clocks = <&clks 46>;
35d23047 99 fsl,ssp-dma-channel = <0>;
bc3a59c1
DA		 100 status = "disabled";
101 };
102
103 ssp1: ssp@80012000 {
41bf5706
MR		 104 #address-cells = <1>;
105 #size-cells = <0>;
0f06cde7 106 reg = <0x80012000 0x2000>;
bc3a59c1 107 interrupts = <97 83>;
b598b9f3 108 clocks = <&clks 47>;
35d23047 109 fsl,ssp-dma-channel = <1>;
bc3a59c1
DA		 110 status = "disabled";
111 };
112
113 ssp2: ssp@80014000 {
41bf5706
MR		 114 #address-cells = <1>;
115 #size-cells = <0>;
0f06cde7 116 reg = <0x80014000 0x2000>;
bc3a59c1 117 interrupts = <98 84>;
b598b9f3 118 clocks = <&clks 48>;
35d23047 119 fsl,ssp-dma-channel = <2>;
bc3a59c1
DA		 120 status = "disabled";
121 };
122
123 ssp3: ssp@80016000 {
41bf5706
MR		 124 #address-cells = <1>;
125 #size-cells = <0>;
0f06cde7 126 reg = <0x80016000 0x2000>;
bc3a59c1 127 interrupts = <99 85>;
b598b9f3 128 clocks = <&clks 49>;
35d23047 129 fsl,ssp-dma-channel = <3>;
bc3a59c1
DA		 130 status = "disabled";
131 };
132
133 pinctrl@80018000 {
134 #address-cells = <1>;
135 #size-cells = <0>;
ce4c6f9b 136 compatible = "fsl,imx28-pinctrl", "simple-bus";
0f06cde7 137 reg = <0x80018000 0x2000>;
bc3a59c1 138
ce4c6f9b
SG		 139 gpio0: gpio@0 {
140 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
141 interrupts = <127>;
142 gpio-controller;
143 #gpio-cells = <2>;
144 interrupt-controller;
145 #interrupt-cells = <2>;
146 };
147
148 gpio1: gpio@1 {
149 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
150 interrupts = <126>;
151 gpio-controller;
152 #gpio-cells = <2>;
153 interrupt-controller;
154 #interrupt-cells = <2>;
155 };
156
157 gpio2: gpio@2 {
158 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
159 interrupts = <125>;
160 gpio-controller;
161 #gpio-cells = <2>;
162 interrupt-controller;
163 #interrupt-cells = <2>;
164 };
165
166 gpio3: gpio@3 {
167 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
168 interrupts = <124>;
169 gpio-controller;
170 #gpio-cells = <2>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 };
174
175 gpio4: gpio@4 {
176 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
177 interrupts = <123>;
178 gpio-controller;
179 #gpio-cells = <2>;
180 interrupt-controller;
181 #interrupt-cells = <2>;
182 };
183
bc3a59c1
DA		 184 duart_pins_a: duart@0 {
185 reg = <0>;
f14da767
SG		 186 fsl,pinmux-ids = <
187 0x3102 /* MX28_PAD_PWM0__DUART_RX */
188 0x3112 /* MX28_PAD_PWM1__DUART_TX */
189 >;
bc3a59c1
DA		 190 fsl,drive-strength = <0>;
191 fsl,voltage = <1>;
192 fsl,pull-up = <0>;
193 };
194
8385e7c1
MR		 195 duart_pins_b: duart@1 {
196 reg = <1>;
f14da767
SG		 197 fsl,pinmux-ids = <
198 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
199 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
200 >;
8385e7c1
MR		 201 fsl,drive-strength = <0>;
202 fsl,voltage = <1>;
203 fsl,pull-up = <0>;
204 };
205
e1a4d18f
SG		 206 duart_4pins_a: duart-4pins@0 {
207 reg = <0>;
208 fsl,pinmux-ids = <
209 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
210 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
211 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
212 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
213 >;
214 fsl,drive-strength = <0>;
215 fsl,voltage = <1>;
216 fsl,pull-up = <0>;
217 };
218
7a8e5149
HS		 219 gpmi_pins_a: gpmi-nand@0 {
220 reg = <0>;
f14da767
SG		 221 fsl,pinmux-ids = <
222 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
223 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
224 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
225 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
226 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
227 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
228 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
229 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
230 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
f14da767 231 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
f14da767
SG		 232 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
233 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
234 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
235 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
236 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
237 >;
7a8e5149
HS		 238 fsl,drive-strength = <0>;
239 fsl,voltage = <1>;
240 fsl,pull-up = <0>;
241 };
242
243 gpmi_status_cfg: gpmi-status-cfg {
f14da767
SG		 244 fsl,pinmux-ids = <
245 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
246 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
247 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
248 >;
7a8e5149
HS		 249 fsl,drive-strength = <2>;
250 };
251
80d969e4
FE		 252 auart0_pins_a: auart0@0 {
253 reg = <0>;
f14da767
SG		 254 fsl,pinmux-ids = <
255 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
256 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
257 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
258 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
259 >;
80d969e4 260 fsl,drive-strength = <0>;
8fa62e11
MV		 261 fsl,voltage = <1>;
262 fsl,pull-up = <0>;
263 };
264
265 auart0_2pins_a: auart0-2pins@0 {
266 reg = <0>;
267 fsl,pinmux-ids = <
268 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
269 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
270 >;
271 fsl,drive-strength = <0>;
80d969e4
FE		 272 fsl,voltage = <1>;
273 fsl,pull-up = <0>;
274 };
275
e1a4d18f
SG		 276 auart1_pins_a: auart1@0 {
277 reg = <0>;
278 fsl,pinmux-ids = <
279 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
280 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
281 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
282 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
283 >;
284 fsl,drive-strength = <0>;
285 fsl,voltage = <1>;
286 fsl,pull-up = <0>;
287 };
288
3143bbb4
SG		 289 auart1_2pins_a: auart1-2pins@0 {
290 reg = <0>;
291 fsl,pinmux-ids = <
292 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
293 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
294 >;
295 fsl,drive-strength = <0>;
296 fsl,voltage = <1>;
297 fsl,pull-up = <0>;
298 };
299
300 auart2_2pins_a: auart2-2pins@0 {
301 reg = <0>;
302 fsl,pinmux-ids = <
303 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
304 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
305 >;
306 fsl,drive-strength = <0>;
307 fsl,voltage = <1>;
308 fsl,pull-up = <0>;
309 };
310
80d969e4
FE		 311 auart3_pins_a: auart3@0 {
312 reg = <0>;
f14da767
SG		 313 fsl,pinmux-ids = <
314 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
315 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
316 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
317 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
318 >;
80d969e4
FE		 319 fsl,drive-strength = <0>;
320 fsl,voltage = <1>;
321 fsl,pull-up = <0>;
322 };
323
3143bbb4
SG		 324 auart3_2pins_a: auart3-2pins@0 {
325 reg = <0>;
326 fsl,pinmux-ids = <
327 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
328 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
329 >;
330 fsl,drive-strength = <0>;
331 fsl,voltage = <1>;
332 fsl,pull-up = <0>;
333 };
334
bc3a59c1
DA		 335 mac0_pins_a: mac0@0 {
336 reg = <0>;
f14da767
SG		 337 fsl,pinmux-ids = <
338 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
339 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
340 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
341 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
342 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
343 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
344 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
345 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
346 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
347 >;
bc3a59c1
DA		 348 fsl,drive-strength = <1>;
349 fsl,voltage = <1>;
350 fsl,pull-up = <1>;
351 };
352
353 mac1_pins_a: mac1@0 {
354 reg = <0>;
f14da767
SG		 355 fsl,pinmux-ids = <
356 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
357 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
358 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
359 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
360 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
361 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
362 >;
bc3a59c1
DA		 363 fsl,drive-strength = <1>;
364 fsl,voltage = <1>;
365 fsl,pull-up = <1>;
366 };
35d23047
SG		 367
368 mmc0_8bit_pins_a: mmc0-8bit@0 {
369 reg = <0>;
f14da767
SG		 370 fsl,pinmux-ids = <
371 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
372 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
373 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
374 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
375 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
376 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
377 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
378 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
379 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
380 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
381 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
382 >;
35d23047
SG		 383 fsl,drive-strength = <1>;
384 fsl,voltage = <1>;
385 fsl,pull-up = <1>;
386 };
387
8385e7c1
MR		 388 mmc0_4bit_pins_a: mmc0-4bit@0 {
389 reg = <0>;
f14da767
SG		 390 fsl,pinmux-ids = <
391 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
392 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
393 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
394 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
395 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
396 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
397 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
398 >;
8385e7c1
MR		 399 fsl,drive-strength = <1>;
400 fsl,voltage = <1>;
401 fsl,pull-up = <1>;
402 };
403
35d23047 404 mmc0_cd_cfg: mmc0-cd-cfg {
f14da767
SG		 405 fsl,pinmux-ids = <
406 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
407 >;
35d23047
SG		 408 fsl,pull-up = <0>;
409 };
410
411 mmc0_sck_cfg: mmc0-sck-cfg {
f14da767
SG		 412 fsl,pinmux-ids = <
413 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
414 >;
35d23047
SG		 415 fsl,drive-strength = <2>;
416 fsl,pull-up = <0>;
417 };
2a96e391
SG		 418
419 i2c0_pins_a: i2c0@0 {
420 reg = <0>;
f14da767
SG		 421 fsl,pinmux-ids = <
422 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
423 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
424 >;
2a96e391
SG		 425 fsl,drive-strength = <1>;
426 fsl,voltage = <1>;
427 fsl,pull-up = <1>;
428 };
530f1d41 429
5c697ea2
MR		 430 i2c0_pins_b: i2c0@1 {
431 reg = <1>;
432 fsl,pinmux-ids = <
433 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
434 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
435 >;
436 fsl,drive-strength = <1>;
437 fsl,voltage = <1>;
438 fsl,pull-up = <1>;
439 };
440
de7e934f
MR		 441 i2c1_pins_a: i2c1@0 {
442 reg = <0>;
443 fsl,pinmux-ids = <
444 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
445 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
446 >;
447 fsl,drive-strength = <1>;
448 fsl,voltage = <1>;
449 fsl,pull-up = <1>;
450 };
451
530f1d41
SG		 452 saif0_pins_a: saif0@0 {
453 reg = <0>;
f14da767
SG		 454 fsl,pinmux-ids = <
455 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
456 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
457 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
458 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
459 >;
530f1d41
SG		 460 fsl,drive-strength = <2>;
461 fsl,voltage = <1>;
462 fsl,pull-up = <1>;
463 };
464
465 saif1_pins_a: saif1@0 {
466 reg = <0>;
f14da767
SG		 467 fsl,pinmux-ids = <
468 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
469 >;
530f1d41
SG		 470 fsl,drive-strength = <2>;
471 fsl,voltage = <1>;
472 fsl,pull-up = <1>;
473 };
52f7176b 474
e1a4d18f
SG		 475 pwm0_pins_a: pwm0@0 {
476 reg = <0>;
477 fsl,pinmux-ids = <
478 0x3100 /* MX28_PAD_PWM0__PWM_0 */
479 >;
480 fsl,drive-strength = <0>;
481 fsl,voltage = <1>;
482 fsl,pull-up = <0>;
483 };
484
52f7176b
SG		 485 pwm2_pins_a: pwm2@0 {
486 reg = <0>;
487 fsl,pinmux-ids = <
488 0x3120 /* MX28_PAD_PWM2__PWM_2 */
489 >;
490 fsl,drive-strength = <0>;
491 fsl,voltage = <1>;
492 fsl,pull-up = <0>;
493 };
a915ee42 494
2bde51cb
JB		 495 pwm3_pins_a: pwm3@0 {
496 reg = <0>;
497 fsl,pinmux-ids = <
498 0x31c0 /* MX28_PAD_PWM3__PWM_3 */
499 >;
500 fsl,drive-strength = <0>;
501 fsl,voltage = <1>;
502 fsl,pull-up = <0>;
503 };
504
d248620c
MR		 505 pwm3_pins_b: pwm3@1 {
506 reg = <1>;
507 fsl,pinmux-ids = <
508 0x3141 /* MX28_PAD_SAIF0_MCLK__PWM3 */
509 >;
510 fsl,drive-strength = <0>;
511 fsl,voltage = <1>;
512 fsl,pull-up = <0>;
513 };
514
2f44211f
MR		 515 pwm4_pins_a: pwm4@0 {
516 reg = <0>;
517 fsl,pinmux-ids = <
518 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
519 >;
520 fsl,drive-strength = <0>;
521 fsl,voltage = <1>;
522 fsl,pull-up = <0>;
523 };
524
a915ee42
SG		 525 lcdif_24bit_pins_a: lcdif-24bit@0 {
526 reg = <0>;
527 fsl,pinmux-ids = <
528 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
529 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
530 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
531 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
532 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
533 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
534 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
535 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
536 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
537 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
538 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
539 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
540 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
541 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
542 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
543 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
544 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
545 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
546 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
547 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
548 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
549 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
550 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
551 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
a915ee42
SG		 552 >;
553 fsl,drive-strength = <0>;
554 fsl,voltage = <1>;
555 fsl,pull-up = <0>;
556 };
6ca44acf 557
4ced2a40
GGM		 558 lcdif_16bit_pins_a: lcdif-16bit@0 {
559 reg = <0>;
560 fsl,pinmux-ids = <
561 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
562 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
563 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
564 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
565 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
566 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
567 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
568 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
569 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
570 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
571 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
572 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
573 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
574 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
575 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
576 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
577 >;
578 fsl,drive-strength = <0>;
579 fsl,voltage = <1>;
580 fsl,pull-up = <0>;
581 };
582
6ca44acf
SG		 583 can0_pins_a: can0@0 {
584 reg = <0>;
585 fsl,pinmux-ids = <
586 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
587 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
588 >;
589 fsl,drive-strength = <0>;
590 fsl,voltage = <1>;
591 fsl,pull-up = <0>;
592 };
593
594 can1_pins_a: can1@0 {
595 reg = <0>;
596 fsl,pinmux-ids = <
597 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
598 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
599 >;
600 fsl,drive-strength = <0>;
601 fsl,voltage = <1>;
602 fsl,pull-up = <0>;
603 };
7f122213
MV		 604
605 spi2_pins_a: spi2@0 {
606 reg = <0>;
607 fsl,pinmux-ids = <
608 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
609 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
610 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
611 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
612 >;
613 fsl,drive-strength = <1>;
614 fsl,voltage = <1>;
615 fsl,pull-up = <1>;
616 };
bb2f1261
MV		 617
618 usbphy0_pins_a: usbphy0@0 {
619 reg = <0>;
620 fsl,pinmux-ids = <
621 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
622 >;
623 fsl,drive-strength = <2>;
624 fsl,voltage = <1>;
625 fsl,pull-up = <0>;
626 };
627
628 usbphy0_pins_b: usbphy0@1 {
629 reg = <1>;
630 fsl,pinmux-ids = <
631 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
632 >;
633 fsl,drive-strength = <2>;
634 fsl,voltage = <1>;
635 fsl,pull-up = <0>;
636 };
637
638 usbphy1_pins_a: usbphy1@0 {
639 reg = <0>;
640 fsl,pinmux-ids = <
641 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
642 >;
643 fsl,drive-strength = <2>;
644 fsl,voltage = <1>;
645 fsl,pull-up = <0>;
646 };
bc3a59c1
DA		 647 };
648
649 digctl@8001c000 {
38d6590f 650 compatible = "fsl,imx28-digctl";
0f06cde7 651 reg = <0x8001c000 0x2000>;
bc3a59c1
DA		 652 interrupts = <89>;
653 status = "disabled";
654 };
655
656 etm@80022000 {
0f06cde7 657 reg = <0x80022000 0x2000>;
bc3a59c1
DA		 658 status = "disabled";
659 };
660
661 dma-apbx@80024000 {
84f3570a 662 compatible = "fsl,imx28-dma-apbx";
0f06cde7 663 reg = <0x80024000 0x2000>;
b598b9f3 664 clocks = <&clks 26>;
bc3a59c1
DA		 665 };
666
667 dcp@80028000 {
0f06cde7 668 reg = <0x80028000 0x2000>;
bc3a59c1
DA		 669 interrupts = <52 53 54>;
670 status = "disabled";
671 };
672
673 pxp@8002a000 {
0f06cde7 674 reg = <0x8002a000 0x2000>;
bc3a59c1
DA		 675 interrupts = <39>;
676 status = "disabled";
677 };
678
679 ocotp@8002c000 {
69d75a02 680 compatible = "fsl,ocotp";
0f06cde7 681 reg = <0x8002c000 0x2000>;
bc3a59c1
DA		 682 status = "disabled";
683 };
684
685 axi-ahb@8002e000 {
0f06cde7 686 reg = <0x8002e000 0x2000>;
bc3a59c1
DA		 687 status = "disabled";
688 };
689
690 lcdif@80030000 {
a915ee42 691 compatible = "fsl,imx28-lcdif";
0f06cde7 692 reg = <0x80030000 0x2000>;
bc3a59c1 693 interrupts = <38 86>;
b598b9f3 694 clocks = <&clks 55>;
bc3a59c1
DA		 695 status = "disabled";
696 };
697
698 can0: can@80032000 {
6ca44acf 699 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 700 reg = <0x80032000 0x2000>;
bc3a59c1 701 interrupts = <8>;
b598b9f3
SG		 702 clocks = <&clks 58>, <&clks 58>;
703 clock-names = "ipg", "per";
bc3a59c1
DA		 704 status = "disabled";
705 };
706
707 can1: can@80034000 {
6ca44acf 708 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 709 reg = <0x80034000 0x2000>;
bc3a59c1 710 interrupts = <9>;
b598b9f3
SG		 711 clocks = <&clks 59>, <&clks 59>;
712 clock-names = "ipg", "per";
bc3a59c1
DA		 713 status = "disabled";
714 };
715
716 simdbg@8003c000 {
0f06cde7 717 reg = <0x8003c000 0x200>;
bc3a59c1
DA		 718 status = "disabled";
719 };
720
721 simgpmisel@8003c200 {
0f06cde7 722 reg = <0x8003c200 0x100>;
bc3a59c1
DA		 723 status = "disabled";
724 };
725
726 simsspsel@8003c300 {
0f06cde7 727 reg = <0x8003c300 0x100>;
bc3a59c1
DA		 728 status = "disabled";
729 };
730
731 simmemsel@8003c400 {
0f06cde7 732 reg = <0x8003c400 0x100>;
bc3a59c1
DA		 733 status = "disabled";
734 };
735
736 gpiomon@8003c500 {
0f06cde7 737 reg = <0x8003c500 0x100>;
bc3a59c1
DA		 738 status = "disabled";
739 };
740
741 simenet@8003c700 {
0f06cde7 742 reg = <0x8003c700 0x100>;
bc3a59c1
DA		 743 status = "disabled";
744 };
745
746 armjtag@8003c800 {
0f06cde7 747 reg = <0x8003c800 0x100>;
bc3a59c1
DA		 748 status = "disabled";
749 };
750 };
751
752 apbx@80040000 {
753 compatible = "simple-bus";
754 #address-cells = <1>;
755 #size-cells = <1>;
756 reg = <0x80040000 0x40000>;
757 ranges;
758
b598b9f3 759 clks: clkctrl@80040000 {
8f7cf881 760 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
0f06cde7 761 reg = <0x80040000 0x2000>;
b598b9f3 762 #clock-cells = <1>;
bc3a59c1
DA		 763 };
764
765 saif0: saif@80042000 {
530f1d41 766 compatible = "fsl,imx28-saif";
0f06cde7 767 reg = <0x80042000 0x2000>;
bc3a59c1 768 interrupts = <59 80>;
b598b9f3 769 clocks = <&clks 53>;
530f1d41 770 fsl,saif-dma-channel = <4>;
bc3a59c1
DA		 771 status = "disabled";
772 };
773
774 power@80044000 {
0f06cde7 775 reg = <0x80044000 0x2000>;
bc3a59c1
DA		 776 status = "disabled";
777 };
778
779 saif1: saif@80046000 {
530f1d41 780 compatible = "fsl,imx28-saif";
0f06cde7 781 reg = <0x80046000 0x2000>;
bc3a59c1 782 interrupts = <58 81>;
b598b9f3 783 clocks = <&clks 54>;
530f1d41 784 fsl,saif-dma-channel = <5>;
bc3a59c1
DA		 785 status = "disabled";
786 };
787
788 lradc@80050000 {
aef35104 789 compatible = "fsl,imx28-lradc";
0f06cde7 790 reg = <0x80050000 0x2000>;
aef35104
MV		 791 interrupts = <10 14 15 16 17 18 19
792 20 21 22 23 24 25>;
bc3a59c1
DA		 793 status = "disabled";
794 };
795
796 spdif@80054000 {
0f06cde7 797 reg = <0x80054000 0x2000>;
bc3a59c1
DA		 798 interrupts = <45 66>;
799 status = "disabled";
800 };
801
802 rtc@80056000 {
f98c990c 803 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
0f06cde7 804 reg = <0x80056000 0x2000>;
f98c990c 805 interrupts = <29>;
bc3a59c1
DA		 806 };
807
808 i2c0: i2c@80058000 {
2a96e391
SG		 809 #address-cells = <1>;
810 #size-cells = <0>;
811 compatible = "fsl,imx28-i2c";
0f06cde7 812 reg = <0x80058000 0x2000>;
bc3a59c1 813 interrupts = <111 68>;
cd4f2d4a 814 clock-frequency = <100000>;
62885f59 815 fsl,i2c-dma-channel = <6>;
bc3a59c1
DA		 816 status = "disabled";
817 };
818
819 i2c1: i2c@8005a000 {
2a96e391
SG		 820 #address-cells = <1>;
821 #size-cells = <0>;
822 compatible = "fsl,imx28-i2c";
0f06cde7 823 reg = <0x8005a000 0x2000>;
bc3a59c1 824 interrupts = <110 69>;
cd4f2d4a 825 clock-frequency = <100000>;
62885f59 826 fsl,i2c-dma-channel = <7>;
bc3a59c1
DA		 827 status = "disabled";
828 };
829
52f7176b
SG		 830 pwm: pwm@80064000 {
831 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
0f06cde7 832 reg = <0x80064000 0x2000>;
b598b9f3 833 clocks = <&clks 44>;
52f7176b
SG		 834 #pwm-cells = <2>;
835 fsl,pwm-number = <8>;
bc3a59c1
DA		 836 status = "disabled";
837 };
838
839 timrot@80068000 {
eeca6e60 840 compatible = "fsl,imx28-timrot", "fsl,timrot";
0f06cde7 841 reg = <0x80068000 0x2000>;
eeca6e60 842 interrupts = <48 49 50 51>;
2efb9504 843 clocks = <&clks 26>;
bc3a59c1
DA		 844 };
845
846 auart0: serial@8006a000 {
80d969e4 847 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 848 reg = <0x8006a000 0x2000>;
849 interrupts = <112 70 71>;
77a807dc 850 fsl,auart-dma-channel = <8 9>;
b598b9f3 851 clocks = <&clks 45>;
bc3a59c1
DA		 852 status = "disabled";
853 };
854
855 auart1: serial@8006c000 {
80d969e4 856 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 857 reg = <0x8006c000 0x2000>;
858 interrupts = <113 72 73>;
b598b9f3 859 clocks = <&clks 45>;
bc3a59c1
DA		 860 status = "disabled";
861 };
862
863 auart2: serial@8006e000 {
80d969e4 864 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 865 reg = <0x8006e000 0x2000>;
866 interrupts = <114 74 75>;
b598b9f3 867 clocks = <&clks 45>;
bc3a59c1
DA		 868 status = "disabled";
869 };
870
871 auart3: serial@80070000 {
80d969e4 872 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 873 reg = <0x80070000 0x2000>;
874 interrupts = <115 76 77>;
b598b9f3 875 clocks = <&clks 45>;
bc3a59c1
DA		 876 status = "disabled";
877 };
878
879 auart4: serial@80072000 {
80d969e4 880 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 881 reg = <0x80072000 0x2000>;
882 interrupts = <116 78 79>;
b598b9f3 883 clocks = <&clks 45>;
bc3a59c1
DA		 884 status = "disabled";
885 };
886
887 duart: serial@80074000 {
888 compatible = "arm,pl011", "arm,primecell";
889 reg = <0x80074000 0x1000>;
890 interrupts = <47>;
b598b9f3
SG		 891 clocks = <&clks 45>, <&clks 26>;
892 clock-names = "uart", "apb_pclk";
bc3a59c1
DA		 893 status = "disabled";
894 };
895
896 usbphy0: usbphy@8007c000 {
5da01270 897 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 898 reg = <0x8007c000 0x2000>;
b598b9f3 899 clocks = <&clks 62>;
bc3a59c1
DA		 900 status = "disabled";
901 };
902
903 usbphy1: usbphy@8007e000 {
5da01270 904 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 905 reg = <0x8007e000 0x2000>;
b598b9f3 906 clocks = <&clks 63>;
bc3a59c1
DA		 907 status = "disabled";
908 };
909 };
910 };
911
912 ahb@80080000 {
913 compatible = "simple-bus";
914 #address-cells = <1>;
915 #size-cells = <1>;
916 reg = <0x80080000 0x80000>;
917 ranges;
918
5da01270
RZ		 919 usb0: usb@80080000 {
920 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 921 reg = <0x80080000 0x10000>;
5da01270 922 interrupts = <93>;
b598b9f3 923 clocks = <&clks 60>;
5da01270 924 fsl,usbphy = <&usbphy0>;
bc3a59c1
DA		 925 status = "disabled";
926 };
927
5da01270
RZ		 928 usb1: usb@80090000 {
929 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 930 reg = <0x80090000 0x10000>;
5da01270 931 interrupts = <92>;
b598b9f3 932 clocks = <&clks 61>;
5da01270 933 fsl,usbphy = <&usbphy1>;
bc3a59c1
DA		 934 status = "disabled";
935 };
936
937 dflpt@800c0000 {
938 reg = <0x800c0000 0x10000>;
939 status = "disabled";
940 };
941
942 mac0: ethernet@800f0000 {
943 compatible = "fsl,imx28-fec";
944 reg = <0x800f0000 0x4000>;
945 interrupts = <101>;
f231a9fe
WS		 946 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
947 clock-names = "ipg", "ahb", "enet_out";
bc3a59c1
DA		 948 status = "disabled";
949 };
950
951 mac1: ethernet@800f4000 {
952 compatible = "fsl,imx28-fec";
953 reg = <0x800f4000 0x4000>;
954 interrupts = <102>;
b598b9f3
SG		 955 clocks = <&clks 57>, <&clks 57>;
956 clock-names = "ipg", "ahb";
bc3a59c1
DA		 957 status = "disabled";
958 };
959
960 switch@800f8000 {
961 reg = <0x800f8000 0x8000>;
962 status = "disabled";
963 };
964
965 };
966};
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