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ARM: mx28: add auart2 2 pins pinmux to imx28.dtsi
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx28.dtsi
CommitLineData
bc3a59c1
DA		 1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
ce4c6f9b
SG		 17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 gpio3 = &gpio3;
22 gpio4 = &gpio4;
530f1d41
SG		 23 saif0 = &saif0;
24 saif1 = &saif1;
80d969e4
FE		 25 serial0 = &auart0;
26 serial1 = &auart1;
27 serial2 = &auart2;
28 serial3 = &auart3;
29 serial4 = &auart4;
8c41d573
MV		 30 ethernet0 = &mac0;
31 ethernet1 = &mac1;
ce4c6f9b
SG		 32 };
33
bc3a59c1
DA		 34 cpus {
35 cpu@0 {
36 compatible = "arm,arm926ejs";
37 };
38 };
39
40 apb@80000000 {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
44 reg = <0x80000000 0x80000>;
45 ranges;
46
47 apbh@80000000 {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 reg = <0x80000000 0x3c900>;
52 ranges;
53
54 icoll: interrupt-controller@80000000 {
83a84efc 55 compatible = "fsl,imx28-icoll", "fsl,icoll";
bc3a59c1
DA		 56 interrupt-controller;
57 #interrupt-cells = <1>;
58 reg = <0x80000000 0x2000>;
59 };
60
61 hsadc@80002000 {
0f06cde7 62 reg = <0x80002000 0x2000>;
bc3a59c1 63 interrupts = <13 87>;
f30fb03d
SG		 64 dmas = <&dma_apbh 12>;
65 dma-names = "rx";
bc3a59c1
DA		 66 status = "disabled";
67 };
68
f30fb03d 69 dma_apbh: dma-apbh@80004000 {
84f3570a 70 compatible = "fsl,imx28-dma-apbh";
0f06cde7 71 reg = <0x80004000 0x2000>;
f30fb03d
SG		 72 interrupts = <82 83 84 85
73 88 88 88 88
74 88 88 88 88
75 87 86 0 0>;
76 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
77 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
78 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
79 "hsadc", "lcdif", "empty", "empty";
80 #dma-cells = <1>;
81 dma-channels = <16>;
b598b9f3 82 clocks = <&clks 25>;
bc3a59c1
DA		 83 };
84
85 perfmon@80006000 {
0f06cde7 86 reg = <0x80006000 0x800>;
bc3a59c1
DA		 87 interrupts = <27>;
88 status = "disabled";
89 };
90
7a8e5149
HS		 91 gpmi-nand@8000c000 {
92 compatible = "fsl,imx28-gpmi-nand";
93 #address-cells = <1>;
94 #size-cells = <1>;
0f06cde7 95 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
7a8e5149
HS		 96 reg-names = "gpmi-nand", "bch";
97 interrupts = <88>, <41>;
98 interrupt-names = "gpmi-dma", "bch";
b598b9f3 99 clocks = <&clks 50>;
b6442559 100 clock-names = "gpmi_io";
f30fb03d
SG		 101 dmas = <&dma_apbh 4>;
102 dma-names = "rx-tx";
7a8e5149 103 fsl,gpmi-dma-channel = <4>;
bc3a59c1
DA		 104 status = "disabled";
105 };
106
107 ssp0: ssp@80010000 {
41bf5706
MR		 108 #address-cells = <1>;
109 #size-cells = <0>;
0f06cde7 110 reg = <0x80010000 0x2000>;
bc3a59c1 111 interrupts = <96 82>;
b598b9f3 112 clocks = <&clks 46>;
f30fb03d
SG		 113 dmas = <&dma_apbh 0>;
114 dma-names = "rx-tx";
35d23047 115 fsl,ssp-dma-channel = <0>;
bc3a59c1
DA		 116 status = "disabled";
117 };
118
119 ssp1: ssp@80012000 {
41bf5706
MR		 120 #address-cells = <1>;
121 #size-cells = <0>;
0f06cde7 122 reg = <0x80012000 0x2000>;
bc3a59c1 123 interrupts = <97 83>;
b598b9f3 124 clocks = <&clks 47>;
f30fb03d
SG		 125 dmas = <&dma_apbh 1>;
126 dma-names = "rx-tx";
35d23047 127 fsl,ssp-dma-channel = <1>;
bc3a59c1
DA		 128 status = "disabled";
129 };
130
131 ssp2: ssp@80014000 {
41bf5706
MR		 132 #address-cells = <1>;
133 #size-cells = <0>;
0f06cde7 134 reg = <0x80014000 0x2000>;
bc3a59c1 135 interrupts = <98 84>;
b598b9f3 136 clocks = <&clks 48>;
f30fb03d
SG		 137 dmas = <&dma_apbh 2>;
138 dma-names = "rx-tx";
35d23047 139 fsl,ssp-dma-channel = <2>;
bc3a59c1
DA		 140 status = "disabled";
141 };
142
143 ssp3: ssp@80016000 {
41bf5706
MR		 144 #address-cells = <1>;
145 #size-cells = <0>;
0f06cde7 146 reg = <0x80016000 0x2000>;
bc3a59c1 147 interrupts = <99 85>;
b598b9f3 148 clocks = <&clks 49>;
f30fb03d
SG		 149 dmas = <&dma_apbh 3>;
150 dma-names = "rx-tx";
35d23047 151 fsl,ssp-dma-channel = <3>;
bc3a59c1
DA		 152 status = "disabled";
153 };
154
155 pinctrl@80018000 {
156 #address-cells = <1>;
157 #size-cells = <0>;
ce4c6f9b 158 compatible = "fsl,imx28-pinctrl", "simple-bus";
0f06cde7 159 reg = <0x80018000 0x2000>;
bc3a59c1 160
ce4c6f9b
SG		 161 gpio0: gpio@0 {
162 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
163 interrupts = <127>;
164 gpio-controller;
165 #gpio-cells = <2>;
166 interrupt-controller;
167 #interrupt-cells = <2>;
168 };
169
170 gpio1: gpio@1 {
171 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
172 interrupts = <126>;
173 gpio-controller;
174 #gpio-cells = <2>;
175 interrupt-controller;
176 #interrupt-cells = <2>;
177 };
178
179 gpio2: gpio@2 {
180 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
181 interrupts = <125>;
182 gpio-controller;
183 #gpio-cells = <2>;
184 interrupt-controller;
185 #interrupt-cells = <2>;
186 };
187
188 gpio3: gpio@3 {
189 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
190 interrupts = <124>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 interrupt-controller;
194 #interrupt-cells = <2>;
195 };
196
197 gpio4: gpio@4 {
198 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
199 interrupts = <123>;
200 gpio-controller;
201 #gpio-cells = <2>;
202 interrupt-controller;
203 #interrupt-cells = <2>;
204 };
205
bc3a59c1
DA		 206 duart_pins_a: duart@0 {
207 reg = <0>;
f14da767
SG		 208 fsl,pinmux-ids = <
209 0x3102 /* MX28_PAD_PWM0__DUART_RX */
210 0x3112 /* MX28_PAD_PWM1__DUART_TX */
211 >;
bc3a59c1
DA		 212 fsl,drive-strength = <0>;
213 fsl,voltage = <1>;
214 fsl,pull-up = <0>;
215 };
216
8385e7c1
MR		 217 duart_pins_b: duart@1 {
218 reg = <1>;
f14da767
SG		 219 fsl,pinmux-ids = <
220 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
221 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
222 >;
8385e7c1
MR		 223 fsl,drive-strength = <0>;
224 fsl,voltage = <1>;
225 fsl,pull-up = <0>;
226 };
227
e1a4d18f
SG		 228 duart_4pins_a: duart-4pins@0 {
229 reg = <0>;
230 fsl,pinmux-ids = <
231 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
232 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
233 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
234 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
235 >;
236 fsl,drive-strength = <0>;
237 fsl,voltage = <1>;
238 fsl,pull-up = <0>;
239 };
240
7a8e5149
HS		 241 gpmi_pins_a: gpmi-nand@0 {
242 reg = <0>;
f14da767
SG		 243 fsl,pinmux-ids = <
244 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
245 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
246 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
247 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
248 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
249 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
250 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
251 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
252 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
f14da767 253 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
f14da767
SG		 254 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
255 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
256 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
257 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
258 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
259 >;
7a8e5149
HS		 260 fsl,drive-strength = <0>;
261 fsl,voltage = <1>;
262 fsl,pull-up = <0>;
263 };
264
265 gpmi_status_cfg: gpmi-status-cfg {
f14da767
SG		 266 fsl,pinmux-ids = <
267 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
268 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
269 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
270 >;
7a8e5149
HS		 271 fsl,drive-strength = <2>;
272 };
273
80d969e4
FE		 274 auart0_pins_a: auart0@0 {
275 reg = <0>;
f14da767
SG		 276 fsl,pinmux-ids = <
277 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
278 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
279 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
280 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
281 >;
80d969e4 282 fsl,drive-strength = <0>;
8fa62e11
MV		 283 fsl,voltage = <1>;
284 fsl,pull-up = <0>;
285 };
286
287 auart0_2pins_a: auart0-2pins@0 {
288 reg = <0>;
289 fsl,pinmux-ids = <
290 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
291 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
292 >;
293 fsl,drive-strength = <0>;
80d969e4
FE		 294 fsl,voltage = <1>;
295 fsl,pull-up = <0>;
296 };
297
e1a4d18f
SG		 298 auart1_pins_a: auart1@0 {
299 reg = <0>;
300 fsl,pinmux-ids = <
301 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
302 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
303 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
304 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
305 >;
306 fsl,drive-strength = <0>;
307 fsl,voltage = <1>;
308 fsl,pull-up = <0>;
309 };
310
3143bbb4
SG		 311 auart1_2pins_a: auart1-2pins@0 {
312 reg = <0>;
313 fsl,pinmux-ids = <
314 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
315 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
316 >;
317 fsl,drive-strength = <0>;
318 fsl,voltage = <1>;
319 fsl,pull-up = <0>;
320 };
321
322 auart2_2pins_a: auart2-2pins@0 {
323 reg = <0>;
324 fsl,pinmux-ids = <
325 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
326 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
327 >;
328 fsl,drive-strength = <0>;
329 fsl,voltage = <1>;
330 fsl,pull-up = <0>;
331 };
332
f8040cf5
EB		 333 auart2_2pins_b: auart2-2pins@1 {
334 reg = <1>;
335 fsl,pinmux-ids = <
336 0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */
337 0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */
338 >;
339 fsl,drive-strength = <0>;
340 fsl,voltage = <1>;
341 fsl,pull-up = <0>;
342 };
343
80d969e4
FE		 344 auart3_pins_a: auart3@0 {
345 reg = <0>;
f14da767
SG		 346 fsl,pinmux-ids = <
347 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
348 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
349 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
350 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
351 >;
80d969e4
FE		 352 fsl,drive-strength = <0>;
353 fsl,voltage = <1>;
354 fsl,pull-up = <0>;
355 };
356
3143bbb4
SG		 357 auart3_2pins_a: auart3-2pins@0 {
358 reg = <0>;
359 fsl,pinmux-ids = <
360 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
361 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
362 >;
363 fsl,drive-strength = <0>;
364 fsl,voltage = <1>;
365 fsl,pull-up = <0>;
366 };
367
bc3a59c1
DA		 368 mac0_pins_a: mac0@0 {
369 reg = <0>;
f14da767
SG		 370 fsl,pinmux-ids = <
371 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
372 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
373 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
374 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
375 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
376 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
377 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
378 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
379 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
380 >;
bc3a59c1
DA		 381 fsl,drive-strength = <1>;
382 fsl,voltage = <1>;
383 fsl,pull-up = <1>;
384 };
385
386 mac1_pins_a: mac1@0 {
387 reg = <0>;
f14da767
SG		 388 fsl,pinmux-ids = <
389 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
390 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
391 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
392 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
393 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
394 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
395 >;
bc3a59c1
DA		 396 fsl,drive-strength = <1>;
397 fsl,voltage = <1>;
398 fsl,pull-up = <1>;
399 };
35d23047
SG		 400
401 mmc0_8bit_pins_a: mmc0-8bit@0 {
402 reg = <0>;
f14da767
SG		 403 fsl,pinmux-ids = <
404 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
405 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
406 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
407 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
408 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
409 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
410 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
411 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
412 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
413 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
414 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
415 >;
35d23047
SG		 416 fsl,drive-strength = <1>;
417 fsl,voltage = <1>;
418 fsl,pull-up = <1>;
419 };
420
8385e7c1
MR		 421 mmc0_4bit_pins_a: mmc0-4bit@0 {
422 reg = <0>;
f14da767
SG		 423 fsl,pinmux-ids = <
424 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
425 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
426 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
427 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
428 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
429 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
430 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
431 >;
8385e7c1
MR		 432 fsl,drive-strength = <1>;
433 fsl,voltage = <1>;
434 fsl,pull-up = <1>;
435 };
436
35d23047 437 mmc0_cd_cfg: mmc0-cd-cfg {
f14da767
SG		 438 fsl,pinmux-ids = <
439 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
440 >;
35d23047
SG		 441 fsl,pull-up = <0>;
442 };
443
444 mmc0_sck_cfg: mmc0-sck-cfg {
f14da767
SG		 445 fsl,pinmux-ids = <
446 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
447 >;
35d23047
SG		 448 fsl,drive-strength = <2>;
449 fsl,pull-up = <0>;
450 };
2a96e391
SG		 451
452 i2c0_pins_a: i2c0@0 {
453 reg = <0>;
f14da767
SG		 454 fsl,pinmux-ids = <
455 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
456 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
457 >;
2a96e391
SG		 458 fsl,drive-strength = <1>;
459 fsl,voltage = <1>;
460 fsl,pull-up = <1>;
461 };
530f1d41 462
5c697ea2
MR		 463 i2c0_pins_b: i2c0@1 {
464 reg = <1>;
465 fsl,pinmux-ids = <
466 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
467 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
468 >;
469 fsl,drive-strength = <1>;
470 fsl,voltage = <1>;
471 fsl,pull-up = <1>;
472 };
473
de7e934f
MR		 474 i2c1_pins_a: i2c1@0 {
475 reg = <0>;
476 fsl,pinmux-ids = <
477 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
478 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
479 >;
480 fsl,drive-strength = <1>;
481 fsl,voltage = <1>;
482 fsl,pull-up = <1>;
483 };
484
530f1d41
SG		 485 saif0_pins_a: saif0@0 {
486 reg = <0>;
f14da767
SG		 487 fsl,pinmux-ids = <
488 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
489 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
490 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
491 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
492 >;
530f1d41
SG		 493 fsl,drive-strength = <2>;
494 fsl,voltage = <1>;
495 fsl,pull-up = <1>;
496 };
497
498 saif1_pins_a: saif1@0 {
499 reg = <0>;
f14da767
SG		 500 fsl,pinmux-ids = <
501 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
502 >;
530f1d41
SG		 503 fsl,drive-strength = <2>;
504 fsl,voltage = <1>;
505 fsl,pull-up = <1>;
506 };
52f7176b 507
e1a4d18f
SG		 508 pwm0_pins_a: pwm0@0 {
509 reg = <0>;
510 fsl,pinmux-ids = <
511 0x3100 /* MX28_PAD_PWM0__PWM_0 */
512 >;
513 fsl,drive-strength = <0>;
514 fsl,voltage = <1>;
515 fsl,pull-up = <0>;
516 };
517
52f7176b
SG		 518 pwm2_pins_a: pwm2@0 {
519 reg = <0>;
520 fsl,pinmux-ids = <
521 0x3120 /* MX28_PAD_PWM2__PWM_2 */
522 >;
523 fsl,drive-strength = <0>;
524 fsl,voltage = <1>;
525 fsl,pull-up = <0>;
526 };
a915ee42 527
2bde51cb
JB		 528 pwm3_pins_a: pwm3@0 {
529 reg = <0>;
530 fsl,pinmux-ids = <
531 0x31c0 /* MX28_PAD_PWM3__PWM_3 */
532 >;
533 fsl,drive-strength = <0>;
534 fsl,voltage = <1>;
535 fsl,pull-up = <0>;
536 };
537
d248620c
MR		 538 pwm3_pins_b: pwm3@1 {
539 reg = <1>;
540 fsl,pinmux-ids = <
541 0x3141 /* MX28_PAD_SAIF0_MCLK__PWM3 */
542 >;
543 fsl,drive-strength = <0>;
544 fsl,voltage = <1>;
545 fsl,pull-up = <0>;
546 };
547
2f44211f
MR		 548 pwm4_pins_a: pwm4@0 {
549 reg = <0>;
550 fsl,pinmux-ids = <
551 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
552 >;
553 fsl,drive-strength = <0>;
554 fsl,voltage = <1>;
555 fsl,pull-up = <0>;
556 };
557
a915ee42
SG		 558 lcdif_24bit_pins_a: lcdif-24bit@0 {
559 reg = <0>;
560 fsl,pinmux-ids = <
561 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
562 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
563 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
564 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
565 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
566 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
567 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
568 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
569 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
570 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
571 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
572 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
573 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
574 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
575 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
576 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
577 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
578 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
579 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
580 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
581 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
582 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
583 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
584 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
a915ee42
SG		 585 >;
586 fsl,drive-strength = <0>;
587 fsl,voltage = <1>;
588 fsl,pull-up = <0>;
589 };
6ca44acf 590
4ced2a40
GGM		 591 lcdif_16bit_pins_a: lcdif-16bit@0 {
592 reg = <0>;
593 fsl,pinmux-ids = <
594 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
595 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
596 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
597 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
598 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
599 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
600 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
601 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
602 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
603 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
604 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
605 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
606 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
607 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
608 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
609 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
610 >;
611 fsl,drive-strength = <0>;
612 fsl,voltage = <1>;
613 fsl,pull-up = <0>;
614 };
615
6ca44acf
SG		 616 can0_pins_a: can0@0 {
617 reg = <0>;
618 fsl,pinmux-ids = <
619 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
620 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
621 >;
622 fsl,drive-strength = <0>;
623 fsl,voltage = <1>;
624 fsl,pull-up = <0>;
625 };
626
627 can1_pins_a: can1@0 {
628 reg = <0>;
629 fsl,pinmux-ids = <
630 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
631 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
632 >;
633 fsl,drive-strength = <0>;
634 fsl,voltage = <1>;
635 fsl,pull-up = <0>;
636 };
7f122213
MV		 637
638 spi2_pins_a: spi2@0 {
639 reg = <0>;
640 fsl,pinmux-ids = <
641 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
642 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
643 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
644 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
645 >;
646 fsl,drive-strength = <1>;
647 fsl,voltage = <1>;
648 fsl,pull-up = <1>;
649 };
bb2f1261
MV		 650
651 usbphy0_pins_a: usbphy0@0 {
652 reg = <0>;
653 fsl,pinmux-ids = <
654 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
655 >;
656 fsl,drive-strength = <2>;
657 fsl,voltage = <1>;
658 fsl,pull-up = <0>;
659 };
660
661 usbphy0_pins_b: usbphy0@1 {
662 reg = <1>;
663 fsl,pinmux-ids = <
664 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
665 >;
666 fsl,drive-strength = <2>;
667 fsl,voltage = <1>;
668 fsl,pull-up = <0>;
669 };
670
671 usbphy1_pins_a: usbphy1@0 {
672 reg = <0>;
673 fsl,pinmux-ids = <
674 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
675 >;
676 fsl,drive-strength = <2>;
677 fsl,voltage = <1>;
678 fsl,pull-up = <0>;
679 };
bc3a59c1
DA		 680 };
681
682 digctl@8001c000 {
115581cf 683 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
0f06cde7 684 reg = <0x8001c000 0x2000>;
bc3a59c1
DA		 685 interrupts = <89>;
686 status = "disabled";
687 };
688
689 etm@80022000 {
0f06cde7 690 reg = <0x80022000 0x2000>;
bc3a59c1
DA		 691 status = "disabled";
692 };
693
f30fb03d 694 dma_apbx: dma-apbx@80024000 {
84f3570a 695 compatible = "fsl,imx28-dma-apbx";
0f06cde7 696 reg = <0x80024000 0x2000>;
f30fb03d
SG		 697 interrupts = <78 79 66 0
698 80 81 68 69
699 70 71 72 73
700 74 75 76 77>;
701 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
702 "saif0", "saif1", "i2c0", "i2c1",
703 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
704 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
705 #dma-cells = <1>;
706 dma-channels = <16>;
b598b9f3 707 clocks = <&clks 26>;
bc3a59c1
DA		 708 };
709
710 dcp@80028000 {
0f06cde7 711 reg = <0x80028000 0x2000>;
bc3a59c1
DA		 712 interrupts = <52 53 54>;
713 status = "disabled";
714 };
715
716 pxp@8002a000 {
0f06cde7 717 reg = <0x8002a000 0x2000>;
bc3a59c1
DA		 718 interrupts = <39>;
719 status = "disabled";
720 };
721
722 ocotp@8002c000 {
69d75a02 723 compatible = "fsl,ocotp";
0f06cde7 724 reg = <0x8002c000 0x2000>;
bc3a59c1
DA		 725 status = "disabled";
726 };
727
728 axi-ahb@8002e000 {
0f06cde7 729 reg = <0x8002e000 0x2000>;
bc3a59c1
DA		 730 status = "disabled";
731 };
732
733 lcdif@80030000 {
a915ee42 734 compatible = "fsl,imx28-lcdif";
0f06cde7 735 reg = <0x80030000 0x2000>;
bc3a59c1 736 interrupts = <38 86>;
b598b9f3 737 clocks = <&clks 55>;
f30fb03d
SG		 738 dmas = <&dma_apbh 13>;
739 dma-names = "rx";
bc3a59c1
DA		 740 status = "disabled";
741 };
742
743 can0: can@80032000 {
6ca44acf 744 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 745 reg = <0x80032000 0x2000>;
bc3a59c1 746 interrupts = <8>;
b598b9f3
SG		 747 clocks = <&clks 58>, <&clks 58>;
748 clock-names = "ipg", "per";
bc3a59c1
DA		 749 status = "disabled";
750 };
751
752 can1: can@80034000 {
6ca44acf 753 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 754 reg = <0x80034000 0x2000>;
bc3a59c1 755 interrupts = <9>;
b598b9f3
SG		 756 clocks = <&clks 59>, <&clks 59>;
757 clock-names = "ipg", "per";
bc3a59c1
DA		 758 status = "disabled";
759 };
760
761 simdbg@8003c000 {
0f06cde7 762 reg = <0x8003c000 0x200>;
bc3a59c1
DA		 763 status = "disabled";
764 };
765
766 simgpmisel@8003c200 {
0f06cde7 767 reg = <0x8003c200 0x100>;
bc3a59c1
DA		 768 status = "disabled";
769 };
770
771 simsspsel@8003c300 {
0f06cde7 772 reg = <0x8003c300 0x100>;
bc3a59c1
DA		 773 status = "disabled";
774 };
775
776 simmemsel@8003c400 {
0f06cde7 777 reg = <0x8003c400 0x100>;
bc3a59c1
DA		 778 status = "disabled";
779 };
780
781 gpiomon@8003c500 {
0f06cde7 782 reg = <0x8003c500 0x100>;
bc3a59c1
DA		 783 status = "disabled";
784 };
785
786 simenet@8003c700 {
0f06cde7 787 reg = <0x8003c700 0x100>;
bc3a59c1
DA		 788 status = "disabled";
789 };
790
791 armjtag@8003c800 {
0f06cde7 792 reg = <0x8003c800 0x100>;
bc3a59c1
DA		 793 status = "disabled";
794 };
795 };
796
797 apbx@80040000 {
798 compatible = "simple-bus";
799 #address-cells = <1>;
800 #size-cells = <1>;
801 reg = <0x80040000 0x40000>;
802 ranges;
803
b598b9f3 804 clks: clkctrl@80040000 {
8f7cf881 805 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
0f06cde7 806 reg = <0x80040000 0x2000>;
b598b9f3 807 #clock-cells = <1>;
bc3a59c1
DA		 808 };
809
810 saif0: saif@80042000 {
530f1d41 811 compatible = "fsl,imx28-saif";
0f06cde7 812 reg = <0x80042000 0x2000>;
bc3a59c1 813 interrupts = <59 80>;
b598b9f3 814 clocks = <&clks 53>;
f30fb03d
SG		 815 dmas = <&dma_apbx 4>;
816 dma-names = "rx-tx";
530f1d41 817 fsl,saif-dma-channel = <4>;
bc3a59c1
DA		 818 status = "disabled";
819 };
820
821 power@80044000 {
0f06cde7 822 reg = <0x80044000 0x2000>;
bc3a59c1
DA		 823 status = "disabled";
824 };
825
826 saif1: saif@80046000 {
530f1d41 827 compatible = "fsl,imx28-saif";
0f06cde7 828 reg = <0x80046000 0x2000>;
bc3a59c1 829 interrupts = <58 81>;
b598b9f3 830 clocks = <&clks 54>;
f30fb03d
SG		 831 dmas = <&dma_apbx 5>;
832 dma-names = "rx-tx";
530f1d41 833 fsl,saif-dma-channel = <5>;
bc3a59c1
DA		 834 status = "disabled";
835 };
836
837 lradc@80050000 {
aef35104 838 compatible = "fsl,imx28-lradc";
0f06cde7 839 reg = <0x80050000 0x2000>;
aef35104
MV		 840 interrupts = <10 14 15 16 17 18 19
841 20 21 22 23 24 25>;
bc3a59c1
DA		 842 status = "disabled";
843 };
844
845 spdif@80054000 {
0f06cde7 846 reg = <0x80054000 0x2000>;
bc3a59c1 847 interrupts = <45 66>;
f30fb03d
SG		 848 dmas = <&dma_apbx 2>;
849 dma-names = "tx";
bc3a59c1
DA		 850 status = "disabled";
851 };
852
853 rtc@80056000 {
f98c990c 854 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
0f06cde7 855 reg = <0x80056000 0x2000>;
f98c990c 856 interrupts = <29>;
bc3a59c1
DA		 857 };
858
859 i2c0: i2c@80058000 {
2a96e391
SG		 860 #address-cells = <1>;
861 #size-cells = <0>;
862 compatible = "fsl,imx28-i2c";
0f06cde7 863 reg = <0x80058000 0x2000>;
bc3a59c1 864 interrupts = <111 68>;
cd4f2d4a 865 clock-frequency = <100000>;
f30fb03d
SG		 866 dmas = <&dma_apbx 6>;
867 dma-names = "rx-tx";
62885f59 868 fsl,i2c-dma-channel = <6>;
bc3a59c1
DA		 869 status = "disabled";
870 };
871
872 i2c1: i2c@8005a000 {
2a96e391
SG		 873 #address-cells = <1>;
874 #size-cells = <0>;
875 compatible = "fsl,imx28-i2c";
0f06cde7 876 reg = <0x8005a000 0x2000>;
bc3a59c1 877 interrupts = <110 69>;
cd4f2d4a 878 clock-frequency = <100000>;
f30fb03d
SG		 879 dmas = <&dma_apbx 7>;
880 dma-names = "rx-tx";
62885f59 881 fsl,i2c-dma-channel = <7>;
bc3a59c1
DA		 882 status = "disabled";
883 };
884
52f7176b
SG		 885 pwm: pwm@80064000 {
886 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
0f06cde7 887 reg = <0x80064000 0x2000>;
b598b9f3 888 clocks = <&clks 44>;
52f7176b
SG		 889 #pwm-cells = <2>;
890 fsl,pwm-number = <8>;
bc3a59c1
DA		 891 status = "disabled";
892 };
893
894 timrot@80068000 {
eeca6e60 895 compatible = "fsl,imx28-timrot", "fsl,timrot";
0f06cde7 896 reg = <0x80068000 0x2000>;
eeca6e60 897 interrupts = <48 49 50 51>;
2efb9504 898 clocks = <&clks 26>;
bc3a59c1
DA		 899 };
900
901 auart0: serial@8006a000 {
80d969e4 902 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 903 reg = <0x8006a000 0x2000>;
904 interrupts = <112 70 71>;
f30fb03d
SG		 905 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
906 dma-names = "rx", "tx";
77a807dc 907 fsl,auart-dma-channel = <8 9>;
b598b9f3 908 clocks = <&clks 45>;
bc3a59c1
DA		 909 status = "disabled";
910 };
911
912 auart1: serial@8006c000 {
80d969e4 913 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 914 reg = <0x8006c000 0x2000>;
915 interrupts = <113 72 73>;
f30fb03d
SG		 916 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
917 dma-names = "rx", "tx";
b598b9f3 918 clocks = <&clks 45>;
bc3a59c1
DA		 919 status = "disabled";
920 };
921
922 auart2: serial@8006e000 {
80d969e4 923 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 924 reg = <0x8006e000 0x2000>;
925 interrupts = <114 74 75>;
f30fb03d
SG		 926 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
927 dma-names = "rx", "tx";
b598b9f3 928 clocks = <&clks 45>;
bc3a59c1
DA		 929 status = "disabled";
930 };
931
932 auart3: serial@80070000 {
80d969e4 933 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 934 reg = <0x80070000 0x2000>;
935 interrupts = <115 76 77>;
f30fb03d
SG		 936 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
937 dma-names = "rx", "tx";
b598b9f3 938 clocks = <&clks 45>;
bc3a59c1
DA		 939 status = "disabled";
940 };
941
942 auart4: serial@80072000 {
80d969e4 943 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1
DA		 944 reg = <0x80072000 0x2000>;
945 interrupts = <116 78 79>;
f30fb03d
SG		 946 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
947 dma-names = "rx", "tx";
b598b9f3 948 clocks = <&clks 45>;
bc3a59c1
DA		 949 status = "disabled";
950 };
951
952 duart: serial@80074000 {
953 compatible = "arm,pl011", "arm,primecell";
954 reg = <0x80074000 0x1000>;
955 interrupts = <47>;
b598b9f3
SG		 956 clocks = <&clks 45>, <&clks 26>;
957 clock-names = "uart", "apb_pclk";
bc3a59c1
DA		 958 status = "disabled";
959 };
960
961 usbphy0: usbphy@8007c000 {
5da01270 962 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 963 reg = <0x8007c000 0x2000>;
b598b9f3 964 clocks = <&clks 62>;
bc3a59c1
DA		 965 status = "disabled";
966 };
967
968 usbphy1: usbphy@8007e000 {
5da01270 969 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 970 reg = <0x8007e000 0x2000>;
b598b9f3 971 clocks = <&clks 63>;
bc3a59c1
DA		 972 status = "disabled";
973 };
974 };
975 };
976
977 ahb@80080000 {
978 compatible = "simple-bus";
979 #address-cells = <1>;
980 #size-cells = <1>;
981 reg = <0x80080000 0x80000>;
982 ranges;
983
5da01270
RZ		 984 usb0: usb@80080000 {
985 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 986 reg = <0x80080000 0x10000>;
5da01270 987 interrupts = <93>;
b598b9f3 988 clocks = <&clks 60>;
5da01270 989 fsl,usbphy = <&usbphy0>;
bc3a59c1
DA		 990 status = "disabled";
991 };
992
5da01270
RZ		 993 usb1: usb@80090000 {
994 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 995 reg = <0x80090000 0x10000>;
5da01270 996 interrupts = <92>;
b598b9f3 997 clocks = <&clks 61>;
5da01270 998 fsl,usbphy = <&usbphy1>;
bc3a59c1
DA		 999 status = "disabled";
1000 };
1001
1002 dflpt@800c0000 {
1003 reg = <0x800c0000 0x10000>;
1004 status = "disabled";
1005 };
1006
1007 mac0: ethernet@800f0000 {
1008 compatible = "fsl,imx28-fec";
1009 reg = <0x800f0000 0x4000>;
1010 interrupts = <101>;
f231a9fe
WS		 1011 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1012 clock-names = "ipg", "ahb", "enet_out";
bc3a59c1
DA		 1013 status = "disabled";
1014 };
1015
1016 mac1: ethernet@800f4000 {
1017 compatible = "fsl,imx28-fec";
1018 reg = <0x800f4000 0x4000>;
1019 interrupts = <102>;
b598b9f3
SG		 1020 clocks = <&clks 57>, <&clks 57>;
1021 clock-names = "ipg", "ahb";
bc3a59c1
DA		 1022 status = "disabled";
1023 };
1024
1025 switch@800f8000 {
1026 reg = <0x800f8000 0x8000>;
1027 status = "disabled";
1028 };
1029
1030 };
1031};
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