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ARM: dts: imx23-olinuxino: enable Low Resolution ADC
[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / imx28.dtsi
CommitLineData
bc3a59c1
DA		 1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
ce4c6f9b
SG		 17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 gpio3 = &gpio3;
22 gpio4 = &gpio4;
530f1d41
SG		 23 saif0 = &saif0;
24 saif1 = &saif1;
80d969e4
FE		 25 serial0 = &auart0;
26 serial1 = &auart1;
27 serial2 = &auart2;
28 serial3 = &auart3;
29 serial4 = &auart4;
8c41d573
MV		 30 ethernet0 = &mac0;
31 ethernet1 = &mac1;
ce4c6f9b
SG		 32 };
33
bc3a59c1 34 cpus {
7925e89f
LP		 35 #address-cells = <0>;
36 #size-cells = <0>;
37
38 cpu {
39 compatible = "arm,arm926ej-s";
40 device_type = "cpu";
bc3a59c1
DA		 41 };
42 };
43
44 apb@80000000 {
45 compatible = "simple-bus";
46 #address-cells = <1>;
47 #size-cells = <1>;
48 reg = <0x80000000 0x80000>;
49 ranges;
50
51 apbh@80000000 {
52 compatible = "simple-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
55 reg = <0x80000000 0x3c900>;
56 ranges;
57
58 icoll: interrupt-controller@80000000 {
83a84efc 59 compatible = "fsl,imx28-icoll", "fsl,icoll";
bc3a59c1
DA		 60 interrupt-controller;
61 #interrupt-cells = <1>;
62 reg = <0x80000000 0x2000>;
63 };
64
65 hsadc@80002000 {
0f06cde7 66 reg = <0x80002000 0x2000>;
7f2b9288 67 interrupts = <13>;
f30fb03d
SG		 68 dmas = <&dma_apbh 12>;
69 dma-names = "rx";
bc3a59c1
DA		 70 status = "disabled";
71 };
72
f30fb03d 73 dma_apbh: dma-apbh@80004000 {
84f3570a 74 compatible = "fsl,imx28-dma-apbh";
0f06cde7 75 reg = <0x80004000 0x2000>;
f30fb03d
SG		 76 interrupts = <82 83 84 85
77 88 88 88 88
78 88 88 88 88
79 87 86 0 0>;
80 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
81 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
82 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
83 "hsadc", "lcdif", "empty", "empty";
84 #dma-cells = <1>;
85 dma-channels = <16>;
b598b9f3 86 clocks = <&clks 25>;
bc3a59c1
DA		 87 };
88
89 perfmon@80006000 {
0f06cde7 90 reg = <0x80006000 0x800>;
bc3a59c1
DA		 91 interrupts = <27>;
92 status = "disabled";
93 };
94
7a8e5149
HS		 95 gpmi-nand@8000c000 {
96 compatible = "fsl,imx28-gpmi-nand";
97 #address-cells = <1>;
98 #size-cells = <1>;
0f06cde7 99 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
7a8e5149 100 reg-names = "gpmi-nand", "bch";
7f2b9288
SG		 101 interrupts = <41>;
102 interrupt-names = "bch";
b598b9f3 103 clocks = <&clks 50>;
b6442559 104 clock-names = "gpmi_io";
f30fb03d
SG		 105 dmas = <&dma_apbh 4>;
106 dma-names = "rx-tx";
bc3a59c1
DA		 107 status = "disabled";
108 };
109
110 ssp0: ssp@80010000 {
41bf5706
MR		 111 #address-cells = <1>;
112 #size-cells = <0>;
0f06cde7 113 reg = <0x80010000 0x2000>;
7f2b9288 114 interrupts = <96>;
b598b9f3 115 clocks = <&clks 46>;
f30fb03d
SG		 116 dmas = <&dma_apbh 0>;
117 dma-names = "rx-tx";
bc3a59c1
DA		 118 status = "disabled";
119 };
120
121 ssp1: ssp@80012000 {
41bf5706
MR		 122 #address-cells = <1>;
123 #size-cells = <0>;
0f06cde7 124 reg = <0x80012000 0x2000>;
7f2b9288 125 interrupts = <97>;
b598b9f3 126 clocks = <&clks 47>;
f30fb03d
SG		 127 dmas = <&dma_apbh 1>;
128 dma-names = "rx-tx";
bc3a59c1
DA		 129 status = "disabled";
130 };
131
132 ssp2: ssp@80014000 {
41bf5706
MR		 133 #address-cells = <1>;
134 #size-cells = <0>;
0f06cde7 135 reg = <0x80014000 0x2000>;
7f2b9288 136 interrupts = <98>;
b598b9f3 137 clocks = <&clks 48>;
f30fb03d
SG		 138 dmas = <&dma_apbh 2>;
139 dma-names = "rx-tx";
bc3a59c1
DA		 140 status = "disabled";
141 };
142
143 ssp3: ssp@80016000 {
41bf5706
MR		 144 #address-cells = <1>;
145 #size-cells = <0>;
0f06cde7 146 reg = <0x80016000 0x2000>;
7f2b9288 147 interrupts = <99>;
b598b9f3 148 clocks = <&clks 49>;
f30fb03d
SG		 149 dmas = <&dma_apbh 3>;
150 dma-names = "rx-tx";
bc3a59c1
DA		 151 status = "disabled";
152 };
153
154 pinctrl@80018000 {
155 #address-cells = <1>;
156 #size-cells = <0>;
ce4c6f9b 157 compatible = "fsl,imx28-pinctrl", "simple-bus";
0f06cde7 158 reg = <0x80018000 0x2000>;
bc3a59c1 159
ce4c6f9b
SG		 160 gpio0: gpio@0 {
161 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
162 interrupts = <127>;
163 gpio-controller;
164 #gpio-cells = <2>;
165 interrupt-controller;
166 #interrupt-cells = <2>;
167 };
168
169 gpio1: gpio@1 {
170 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
171 interrupts = <126>;
172 gpio-controller;
173 #gpio-cells = <2>;
174 interrupt-controller;
175 #interrupt-cells = <2>;
176 };
177
178 gpio2: gpio@2 {
179 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
180 interrupts = <125>;
181 gpio-controller;
182 #gpio-cells = <2>;
183 interrupt-controller;
184 #interrupt-cells = <2>;
185 };
186
187 gpio3: gpio@3 {
188 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
189 interrupts = <124>;
190 gpio-controller;
191 #gpio-cells = <2>;
192 interrupt-controller;
193 #interrupt-cells = <2>;
194 };
195
196 gpio4: gpio@4 {
197 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
198 interrupts = <123>;
199 gpio-controller;
200 #gpio-cells = <2>;
201 interrupt-controller;
202 #interrupt-cells = <2>;
203 };
204
bc3a59c1
DA		 205 duart_pins_a: duart@0 {
206 reg = <0>;
f14da767
SG		 207 fsl,pinmux-ids = <
208 0x3102 /* MX28_PAD_PWM0__DUART_RX */
209 0x3112 /* MX28_PAD_PWM1__DUART_TX */
210 >;
bc3a59c1
DA		 211 fsl,drive-strength = <0>;
212 fsl,voltage = <1>;
213 fsl,pull-up = <0>;
214 };
215
8385e7c1
MR		 216 duart_pins_b: duart@1 {
217 reg = <1>;
f14da767
SG		 218 fsl,pinmux-ids = <
219 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
220 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
221 >;
8385e7c1
MR		 222 fsl,drive-strength = <0>;
223 fsl,voltage = <1>;
224 fsl,pull-up = <0>;
225 };
226
e1a4d18f
SG		 227 duart_4pins_a: duart-4pins@0 {
228 reg = <0>;
229 fsl,pinmux-ids = <
230 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
231 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
232 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
233 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
234 >;
235 fsl,drive-strength = <0>;
236 fsl,voltage = <1>;
237 fsl,pull-up = <0>;
238 };
239
7a8e5149
HS		 240 gpmi_pins_a: gpmi-nand@0 {
241 reg = <0>;
f14da767
SG		 242 fsl,pinmux-ids = <
243 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
244 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
245 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
246 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
247 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
248 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
249 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
250 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
251 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
f14da767 252 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
f14da767
SG		 253 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
254 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
255 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
256 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
257 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
258 >;
7a8e5149
HS		 259 fsl,drive-strength = <0>;
260 fsl,voltage = <1>;
261 fsl,pull-up = <0>;
262 };
263
264 gpmi_status_cfg: gpmi-status-cfg {
f14da767
SG		 265 fsl,pinmux-ids = <
266 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
267 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
268 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
269 >;
7a8e5149
HS		 270 fsl,drive-strength = <2>;
271 };
272
80d969e4
FE		 273 auart0_pins_a: auart0@0 {
274 reg = <0>;
f14da767
SG		 275 fsl,pinmux-ids = <
276 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
277 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
278 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
279 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
280 >;
80d969e4 281 fsl,drive-strength = <0>;
8fa62e11
MV		 282 fsl,voltage = <1>;
283 fsl,pull-up = <0>;
284 };
285
286 auart0_2pins_a: auart0-2pins@0 {
287 reg = <0>;
288 fsl,pinmux-ids = <
289 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
290 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
291 >;
292 fsl,drive-strength = <0>;
80d969e4
FE		 293 fsl,voltage = <1>;
294 fsl,pull-up = <0>;
295 };
296
e1a4d18f
SG		 297 auart1_pins_a: auart1@0 {
298 reg = <0>;
299 fsl,pinmux-ids = <
300 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
301 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
302 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
303 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
304 >;
305 fsl,drive-strength = <0>;
306 fsl,voltage = <1>;
307 fsl,pull-up = <0>;
308 };
309
3143bbb4
SG		 310 auart1_2pins_a: auart1-2pins@0 {
311 reg = <0>;
312 fsl,pinmux-ids = <
313 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
314 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
315 >;
316 fsl,drive-strength = <0>;
317 fsl,voltage = <1>;
318 fsl,pull-up = <0>;
319 };
320
321 auart2_2pins_a: auart2-2pins@0 {
322 reg = <0>;
323 fsl,pinmux-ids = <
324 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
325 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
326 >;
327 fsl,drive-strength = <0>;
328 fsl,voltage = <1>;
329 fsl,pull-up = <0>;
330 };
331
f8040cf5
EB		 332 auart2_2pins_b: auart2-2pins@1 {
333 reg = <1>;
334 fsl,pinmux-ids = <
335 0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */
336 0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */
337 >;
338 fsl,drive-strength = <0>;
339 fsl,voltage = <1>;
340 fsl,pull-up = <0>;
341 };
342
80d969e4
FE		 343 auart3_pins_a: auart3@0 {
344 reg = <0>;
f14da767
SG		 345 fsl,pinmux-ids = <
346 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
347 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
348 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
349 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
350 >;
80d969e4
FE		 351 fsl,drive-strength = <0>;
352 fsl,voltage = <1>;
353 fsl,pull-up = <0>;
354 };
355
3143bbb4
SG		 356 auart3_2pins_a: auart3-2pins@0 {
357 reg = <0>;
358 fsl,pinmux-ids = <
359 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
360 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
361 >;
362 fsl,drive-strength = <0>;
363 fsl,voltage = <1>;
364 fsl,pull-up = <0>;
365 };
366
4812e746
EB		 367 auart3_2pins_b: auart3-2pins@1 {
368 reg = <1>;
369 fsl,pinmux-ids = <
370 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
371 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
372 >;
373 fsl,drive-strength = <0>;
374 fsl,voltage = <1>;
375 fsl,pull-up = <0>;
376 };
377
33678d12
EB		 378 auart4_2pins_a: auart4@0 {
379 reg = <0>;
380 fsl,pinmux-ids = <
381 0x2181 /* MX28_PAD_SSP3_SCK__AUART4_TX */
382 0x2191 /* MX28_PAD_SSP3_MOSI__AUART4_RX */
383 >;
384 fsl,drive-strength = <0>;
385 fsl,voltage = <1>;
386 fsl,pull-up = <0>;
387 };
388
bc3a59c1
DA		 389 mac0_pins_a: mac0@0 {
390 reg = <0>;
f14da767
SG		 391 fsl,pinmux-ids = <
392 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
393 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
394 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
395 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
396 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
397 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
398 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
399 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
400 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
401 >;
bc3a59c1
DA		 402 fsl,drive-strength = <1>;
403 fsl,voltage = <1>;
404 fsl,pull-up = <1>;
405 };
406
407 mac1_pins_a: mac1@0 {
408 reg = <0>;
f14da767
SG		 409 fsl,pinmux-ids = <
410 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
411 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
412 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
413 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
414 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
415 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
416 >;
bc3a59c1
DA		 417 fsl,drive-strength = <1>;
418 fsl,voltage = <1>;
419 fsl,pull-up = <1>;
420 };
35d23047
SG		 421
422 mmc0_8bit_pins_a: mmc0-8bit@0 {
423 reg = <0>;
f14da767
SG		 424 fsl,pinmux-ids = <
425 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
426 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
427 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
428 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
429 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
430 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
431 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
432 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
433 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
434 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
435 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
436 >;
35d23047
SG		 437 fsl,drive-strength = <1>;
438 fsl,voltage = <1>;
439 fsl,pull-up = <1>;
440 };
441
8385e7c1
MR		 442 mmc0_4bit_pins_a: mmc0-4bit@0 {
443 reg = <0>;
f14da767
SG		 444 fsl,pinmux-ids = <
445 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
446 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
447 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
448 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
449 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
450 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
451 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
452 >;
8385e7c1
MR		 453 fsl,drive-strength = <1>;
454 fsl,voltage = <1>;
455 fsl,pull-up = <1>;
456 };
457
35d23047 458 mmc0_cd_cfg: mmc0-cd-cfg {
f14da767
SG		 459 fsl,pinmux-ids = <
460 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
461 >;
35d23047
SG		 462 fsl,pull-up = <0>;
463 };
464
465 mmc0_sck_cfg: mmc0-sck-cfg {
f14da767
SG		 466 fsl,pinmux-ids = <
467 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
468 >;
35d23047
SG		 469 fsl,drive-strength = <2>;
470 fsl,pull-up = <0>;
471 };
2a96e391
SG		 472
473 i2c0_pins_a: i2c0@0 {
474 reg = <0>;
f14da767
SG		 475 fsl,pinmux-ids = <
476 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
477 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
478 >;
2a96e391
SG		 479 fsl,drive-strength = <1>;
480 fsl,voltage = <1>;
481 fsl,pull-up = <1>;
482 };
530f1d41 483
5c697ea2
MR		 484 i2c0_pins_b: i2c0@1 {
485 reg = <1>;
486 fsl,pinmux-ids = <
487 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
488 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
489 >;
490 fsl,drive-strength = <1>;
491 fsl,voltage = <1>;
492 fsl,pull-up = <1>;
493 };
494
de7e934f
MR		 495 i2c1_pins_a: i2c1@0 {
496 reg = <0>;
497 fsl,pinmux-ids = <
498 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
499 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
500 >;
501 fsl,drive-strength = <1>;
502 fsl,voltage = <1>;
503 fsl,pull-up = <1>;
504 };
505
530f1d41
SG		 506 saif0_pins_a: saif0@0 {
507 reg = <0>;
f14da767
SG		 508 fsl,pinmux-ids = <
509 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
510 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
511 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
512 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
513 >;
530f1d41
SG		 514 fsl,drive-strength = <2>;
515 fsl,voltage = <1>;
516 fsl,pull-up = <1>;
517 };
518
519 saif1_pins_a: saif1@0 {
520 reg = <0>;
f14da767
SG		 521 fsl,pinmux-ids = <
522 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
523 >;
530f1d41
SG		 524 fsl,drive-strength = <2>;
525 fsl,voltage = <1>;
526 fsl,pull-up = <1>;
527 };
52f7176b 528
e1a4d18f
SG		 529 pwm0_pins_a: pwm0@0 {
530 reg = <0>;
531 fsl,pinmux-ids = <
532 0x3100 /* MX28_PAD_PWM0__PWM_0 */
533 >;
534 fsl,drive-strength = <0>;
535 fsl,voltage = <1>;
536 fsl,pull-up = <0>;
537 };
538
52f7176b
SG		 539 pwm2_pins_a: pwm2@0 {
540 reg = <0>;
541 fsl,pinmux-ids = <
542 0x3120 /* MX28_PAD_PWM2__PWM_2 */
543 >;
544 fsl,drive-strength = <0>;
545 fsl,voltage = <1>;
546 fsl,pull-up = <0>;
547 };
a915ee42 548
2bde51cb
JB		 549 pwm3_pins_a: pwm3@0 {
550 reg = <0>;
551 fsl,pinmux-ids = <
552 0x31c0 /* MX28_PAD_PWM3__PWM_3 */
553 >;
554 fsl,drive-strength = <0>;
555 fsl,voltage = <1>;
556 fsl,pull-up = <0>;
557 };
558
d248620c
MR		 559 pwm3_pins_b: pwm3@1 {
560 reg = <1>;
561 fsl,pinmux-ids = <
562 0x3141 /* MX28_PAD_SAIF0_MCLK__PWM3 */
563 >;
564 fsl,drive-strength = <0>;
565 fsl,voltage = <1>;
566 fsl,pull-up = <0>;
567 };
568
2f44211f
MR		 569 pwm4_pins_a: pwm4@0 {
570 reg = <0>;
571 fsl,pinmux-ids = <
572 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
573 >;
574 fsl,drive-strength = <0>;
575 fsl,voltage = <1>;
576 fsl,pull-up = <0>;
577 };
578
a915ee42
SG		 579 lcdif_24bit_pins_a: lcdif-24bit@0 {
580 reg = <0>;
581 fsl,pinmux-ids = <
582 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
583 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
584 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
585 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
586 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
587 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
588 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
589 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
590 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
591 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
592 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
593 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
594 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
595 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
596 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
597 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
598 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
599 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
600 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
601 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
602 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
603 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
604 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
605 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
a915ee42
SG		 606 >;
607 fsl,drive-strength = <0>;
608 fsl,voltage = <1>;
609 fsl,pull-up = <0>;
610 };
6ca44acf 611
4ced2a40
GGM		 612 lcdif_16bit_pins_a: lcdif-16bit@0 {
613 reg = <0>;
614 fsl,pinmux-ids = <
615 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
616 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
617 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
618 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
619 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
620 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
621 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
622 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
623 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
624 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
625 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
626 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
627 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
628 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
629 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
630 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
631 >;
632 fsl,drive-strength = <0>;
633 fsl,voltage = <1>;
634 fsl,pull-up = <0>;
635 };
636
6ca44acf
SG		 637 can0_pins_a: can0@0 {
638 reg = <0>;
639 fsl,pinmux-ids = <
640 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
641 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
642 >;
643 fsl,drive-strength = <0>;
644 fsl,voltage = <1>;
645 fsl,pull-up = <0>;
646 };
647
648 can1_pins_a: can1@0 {
649 reg = <0>;
650 fsl,pinmux-ids = <
651 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
652 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
653 >;
654 fsl,drive-strength = <0>;
655 fsl,voltage = <1>;
656 fsl,pull-up = <0>;
657 };
7f122213
MV		 658
659 spi2_pins_a: spi2@0 {
660 reg = <0>;
661 fsl,pinmux-ids = <
662 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
663 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
664 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
665 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
666 >;
667 fsl,drive-strength = <1>;
668 fsl,voltage = <1>;
669 fsl,pull-up = <1>;
670 };
bb2f1261
MV		 671
672 usbphy0_pins_a: usbphy0@0 {
673 reg = <0>;
674 fsl,pinmux-ids = <
675 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
676 >;
677 fsl,drive-strength = <2>;
678 fsl,voltage = <1>;
679 fsl,pull-up = <0>;
680 };
681
682 usbphy0_pins_b: usbphy0@1 {
683 reg = <1>;
684 fsl,pinmux-ids = <
685 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
686 >;
687 fsl,drive-strength = <2>;
688 fsl,voltage = <1>;
689 fsl,pull-up = <0>;
690 };
691
692 usbphy1_pins_a: usbphy1@0 {
693 reg = <0>;
694 fsl,pinmux-ids = <
695 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
696 >;
697 fsl,drive-strength = <2>;
698 fsl,voltage = <1>;
699 fsl,pull-up = <0>;
700 };
bc3a59c1
DA		 701 };
702
703 digctl@8001c000 {
115581cf 704 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
0f06cde7 705 reg = <0x8001c000 0x2000>;
bc3a59c1
DA		 706 interrupts = <89>;
707 status = "disabled";
708 };
709
710 etm@80022000 {
0f06cde7 711 reg = <0x80022000 0x2000>;
bc3a59c1
DA		 712 status = "disabled";
713 };
714
f30fb03d 715 dma_apbx: dma-apbx@80024000 {
84f3570a 716 compatible = "fsl,imx28-dma-apbx";
0f06cde7 717 reg = <0x80024000 0x2000>;
f30fb03d
SG		 718 interrupts = <78 79 66 0
719 80 81 68 69
720 70 71 72 73
721 74 75 76 77>;
722 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
723 "saif0", "saif1", "i2c0", "i2c1",
724 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
725 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
726 #dma-cells = <1>;
727 dma-channels = <16>;
b598b9f3 728 clocks = <&clks 26>;
bc3a59c1
DA		 729 };
730
731 dcp@80028000 {
0f06cde7 732 reg = <0x80028000 0x2000>;
bc3a59c1 733 interrupts = <52 53 54>;
519d8b1a 734 compatible = "fsl-dcp";
bc3a59c1
DA		 735 };
736
737 pxp@8002a000 {
0f06cde7 738 reg = <0x8002a000 0x2000>;
bc3a59c1
DA		 739 interrupts = <39>;
740 status = "disabled";
741 };
742
743 ocotp@8002c000 {
69d75a02 744 compatible = "fsl,ocotp";
0f06cde7 745 reg = <0x8002c000 0x2000>;
bc3a59c1
DA		 746 status = "disabled";
747 };
748
749 axi-ahb@8002e000 {
0f06cde7 750 reg = <0x8002e000 0x2000>;
bc3a59c1
DA		 751 status = "disabled";
752 };
753
754 lcdif@80030000 {
a915ee42 755 compatible = "fsl,imx28-lcdif";
0f06cde7 756 reg = <0x80030000 0x2000>;
7f2b9288 757 interrupts = <38>;
b598b9f3 758 clocks = <&clks 55>;
f30fb03d
SG		 759 dmas = <&dma_apbh 13>;
760 dma-names = "rx";
bc3a59c1
DA		 761 status = "disabled";
762 };
763
764 can0: can@80032000 {
6ca44acf 765 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 766 reg = <0x80032000 0x2000>;
bc3a59c1 767 interrupts = <8>;
b598b9f3
SG		 768 clocks = <&clks 58>, <&clks 58>;
769 clock-names = "ipg", "per";
bc3a59c1
DA		 770 status = "disabled";
771 };
772
773 can1: can@80034000 {
6ca44acf 774 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
0f06cde7 775 reg = <0x80034000 0x2000>;
bc3a59c1 776 interrupts = <9>;
b598b9f3
SG		 777 clocks = <&clks 59>, <&clks 59>;
778 clock-names = "ipg", "per";
bc3a59c1
DA		 779 status = "disabled";
780 };
781
782 simdbg@8003c000 {
0f06cde7 783 reg = <0x8003c000 0x200>;
bc3a59c1
DA		 784 status = "disabled";
785 };
786
787 simgpmisel@8003c200 {
0f06cde7 788 reg = <0x8003c200 0x100>;
bc3a59c1
DA		 789 status = "disabled";
790 };
791
792 simsspsel@8003c300 {
0f06cde7 793 reg = <0x8003c300 0x100>;
bc3a59c1
DA		 794 status = "disabled";
795 };
796
797 simmemsel@8003c400 {
0f06cde7 798 reg = <0x8003c400 0x100>;
bc3a59c1
DA		 799 status = "disabled";
800 };
801
802 gpiomon@8003c500 {
0f06cde7 803 reg = <0x8003c500 0x100>;
bc3a59c1
DA		 804 status = "disabled";
805 };
806
807 simenet@8003c700 {
0f06cde7 808 reg = <0x8003c700 0x100>;
bc3a59c1
DA		 809 status = "disabled";
810 };
811
812 armjtag@8003c800 {
0f06cde7 813 reg = <0x8003c800 0x100>;
bc3a59c1
DA		 814 status = "disabled";
815 };
816 };
817
818 apbx@80040000 {
819 compatible = "simple-bus";
820 #address-cells = <1>;
821 #size-cells = <1>;
822 reg = <0x80040000 0x40000>;
823 ranges;
824
b598b9f3 825 clks: clkctrl@80040000 {
8f7cf881 826 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
0f06cde7 827 reg = <0x80040000 0x2000>;
b598b9f3 828 #clock-cells = <1>;
bc3a59c1
DA		 829 };
830
831 saif0: saif@80042000 {
530f1d41 832 compatible = "fsl,imx28-saif";
0f06cde7 833 reg = <0x80042000 0x2000>;
7f2b9288 834 interrupts = <59>;
66acaf3f 835 #clock-cells = <0>;
b598b9f3 836 clocks = <&clks 53>;
f30fb03d
SG		 837 dmas = <&dma_apbx 4>;
838 dma-names = "rx-tx";
bc3a59c1
DA		 839 status = "disabled";
840 };
841
842 power@80044000 {
0f06cde7 843 reg = <0x80044000 0x2000>;
bc3a59c1
DA		 844 status = "disabled";
845 };
846
847 saif1: saif@80046000 {
530f1d41 848 compatible = "fsl,imx28-saif";
0f06cde7 849 reg = <0x80046000 0x2000>;
7f2b9288 850 interrupts = <58>;
b598b9f3 851 clocks = <&clks 54>;
f30fb03d
SG		 852 dmas = <&dma_apbx 5>;
853 dma-names = "rx-tx";
bc3a59c1
DA		 854 status = "disabled";
855 };
856
857 lradc@80050000 {
aef35104 858 compatible = "fsl,imx28-lradc";
0f06cde7 859 reg = <0x80050000 0x2000>;
aef35104
MV		 860 interrupts = <10 14 15 16 17 18 19
861 20 21 22 23 24 25>;
bc3a59c1
DA		 862 status = "disabled";
863 };
864
865 spdif@80054000 {
0f06cde7 866 reg = <0x80054000 0x2000>;
7f2b9288 867 interrupts = <45>;
f30fb03d
SG		 868 dmas = <&dma_apbx 2>;
869 dma-names = "tx";
bc3a59c1
DA		 870 status = "disabled";
871 };
872
873 rtc@80056000 {
f98c990c 874 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
0f06cde7 875 reg = <0x80056000 0x2000>;
f98c990c 876 interrupts = <29>;
bc3a59c1
DA		 877 };
878
879 i2c0: i2c@80058000 {
2a96e391
SG		 880 #address-cells = <1>;
881 #size-cells = <0>;
882 compatible = "fsl,imx28-i2c";
0f06cde7 883 reg = <0x80058000 0x2000>;
7f2b9288 884 interrupts = <111>;
cd4f2d4a 885 clock-frequency = <100000>;
f30fb03d
SG		 886 dmas = <&dma_apbx 6>;
887 dma-names = "rx-tx";
bc3a59c1
DA		 888 status = "disabled";
889 };
890
891 i2c1: i2c@8005a000 {
2a96e391
SG		 892 #address-cells = <1>;
893 #size-cells = <0>;
894 compatible = "fsl,imx28-i2c";
0f06cde7 895 reg = <0x8005a000 0x2000>;
7f2b9288 896 interrupts = <110>;
cd4f2d4a 897 clock-frequency = <100000>;
f30fb03d
SG		 898 dmas = <&dma_apbx 7>;
899 dma-names = "rx-tx";
bc3a59c1
DA		 900 status = "disabled";
901 };
902
52f7176b
SG		 903 pwm: pwm@80064000 {
904 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
0f06cde7 905 reg = <0x80064000 0x2000>;
b598b9f3 906 clocks = <&clks 44>;
52f7176b
SG		 907 #pwm-cells = <2>;
908 fsl,pwm-number = <8>;
bc3a59c1
DA		 909 status = "disabled";
910 };
911
912 timrot@80068000 {
eeca6e60 913 compatible = "fsl,imx28-timrot", "fsl,timrot";
0f06cde7 914 reg = <0x80068000 0x2000>;
eeca6e60 915 interrupts = <48 49 50 51>;
2efb9504 916 clocks = <&clks 26>;
bc3a59c1
DA		 917 };
918
919 auart0: serial@8006a000 {
80d969e4 920 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 921 reg = <0x8006a000 0x2000>;
7f2b9288 922 interrupts = <112>;
f30fb03d
SG		 923 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
924 dma-names = "rx", "tx";
b598b9f3 925 clocks = <&clks 45>;
bc3a59c1
DA		 926 status = "disabled";
927 };
928
929 auart1: serial@8006c000 {
80d969e4 930 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 931 reg = <0x8006c000 0x2000>;
7f2b9288 932 interrupts = <113>;
f30fb03d
SG		 933 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
934 dma-names = "rx", "tx";
b598b9f3 935 clocks = <&clks 45>;
bc3a59c1
DA		 936 status = "disabled";
937 };
938
939 auart2: serial@8006e000 {
80d969e4 940 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 941 reg = <0x8006e000 0x2000>;
7f2b9288 942 interrupts = <114>;
f30fb03d
SG		 943 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
944 dma-names = "rx", "tx";
b598b9f3 945 clocks = <&clks 45>;
bc3a59c1
DA		 946 status = "disabled";
947 };
948
949 auart3: serial@80070000 {
80d969e4 950 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 951 reg = <0x80070000 0x2000>;
7f2b9288 952 interrupts = <115>;
f30fb03d
SG		 953 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
954 dma-names = "rx", "tx";
b598b9f3 955 clocks = <&clks 45>;
bc3a59c1
DA		 956 status = "disabled";
957 };
958
959 auart4: serial@80072000 {
80d969e4 960 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
bc3a59c1 961 reg = <0x80072000 0x2000>;
7f2b9288 962 interrupts = <116>;
f30fb03d
SG		 963 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
964 dma-names = "rx", "tx";
b598b9f3 965 clocks = <&clks 45>;
bc3a59c1
DA		 966 status = "disabled";
967 };
968
969 duart: serial@80074000 {
970 compatible = "arm,pl011", "arm,primecell";
971 reg = <0x80074000 0x1000>;
972 interrupts = <47>;
b598b9f3
SG		 973 clocks = <&clks 45>, <&clks 26>;
974 clock-names = "uart", "apb_pclk";
bc3a59c1
DA		 975 status = "disabled";
976 };
977
978 usbphy0: usbphy@8007c000 {
5da01270 979 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 980 reg = <0x8007c000 0x2000>;
b598b9f3 981 clocks = <&clks 62>;
bc3a59c1
DA		 982 status = "disabled";
983 };
984
985 usbphy1: usbphy@8007e000 {
5da01270 986 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
bc3a59c1 987 reg = <0x8007e000 0x2000>;
b598b9f3 988 clocks = <&clks 63>;
bc3a59c1
DA		 989 status = "disabled";
990 };
991 };
992 };
993
994 ahb@80080000 {
995 compatible = "simple-bus";
996 #address-cells = <1>;
997 #size-cells = <1>;
998 reg = <0x80080000 0x80000>;
999 ranges;
1000
5da01270
RZ		 1001 usb0: usb@80080000 {
1002 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 1003 reg = <0x80080000 0x10000>;
5da01270 1004 interrupts = <93>;
b598b9f3 1005 clocks = <&clks 60>;
5da01270 1006 fsl,usbphy = <&usbphy0>;
bc3a59c1
DA		 1007 status = "disabled";
1008 };
1009
5da01270
RZ		 1010 usb1: usb@80090000 {
1011 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
bc3a59c1 1012 reg = <0x80090000 0x10000>;
5da01270 1013 interrupts = <92>;
b598b9f3 1014 clocks = <&clks 61>;
5da01270 1015 fsl,usbphy = <&usbphy1>;
bc3a59c1
DA		 1016 status = "disabled";
1017 };
1018
1019 dflpt@800c0000 {
1020 reg = <0x800c0000 0x10000>;
1021 status = "disabled";
1022 };
1023
1024 mac0: ethernet@800f0000 {
1025 compatible = "fsl,imx28-fec";
1026 reg = <0x800f0000 0x4000>;
1027 interrupts = <101>;
f231a9fe
WS		 1028 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1029 clock-names = "ipg", "ahb", "enet_out";
bc3a59c1
DA		 1030 status = "disabled";
1031 };
1032
1033 mac1: ethernet@800f4000 {
1034 compatible = "fsl,imx28-fec";
1035 reg = <0x800f4000 0x4000>;
1036 interrupts = <102>;
b598b9f3
SG		 1037 clocks = <&clks 57>, <&clks 57>;
1038 clock-names = "ipg", "ahb";
bc3a59c1
DA		 1039 status = "disabled";
1040 };
1041
1042 switch@800f8000 {
1043 reg = <0x800f8000 0x8000>;
1044 status = "disabled";
1045 };
1046
1047 };
1048};
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