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1 | /* |
2 | * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | /include/ "skeleton.dtsi" | |
13 | ||
14 | / { | |
15 | aliases { | |
16 | serial0 = &uart1; | |
17 | serial1 = &uart2; | |
18 | serial2 = &uart3; | |
19 | serial3 = &uart4; | |
20 | serial4 = &uart5; | |
21 | }; | |
22 | ||
23 | avic: avic-interrupt-controller@60000000 { | |
24 | compatible = "fsl,imx31-avic", "fsl,avic"; | |
25 | interrupt-controller; | |
26 | #interrupt-cells = <1>; | |
27 | reg = <0x60000000 0x100000>; | |
28 | }; | |
29 | ||
30 | soc { | |
31 | #address-cells = <1>; | |
32 | #size-cells = <1>; | |
33 | compatible = "simple-bus"; | |
34 | interrupt-parent = <&avic>; | |
35 | ranges; | |
36 | ||
37 | aips@43f00000 { /* AIPS1 */ | |
38 | compatible = "fsl,aips-bus", "simple-bus"; | |
39 | #address-cells = <1>; | |
40 | #size-cells = <1>; | |
41 | reg = <0x43f00000 0x100000>; | |
42 | ranges; | |
43 | ||
44 | uart1: serial@43f90000 { | |
45 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | |
46 | reg = <0x43f90000 0x4000>; | |
47 | interrupts = <45>; | |
ef0e4a60 FE |
48 | clocks = <&clks 10>, <&clks 30>; |
49 | clock-names = "ipg", "per"; | |
d2a37b3d DGC |
50 | status = "disabled"; |
51 | }; | |
52 | ||
53 | uart2: serial@43f94000 { | |
54 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | |
55 | reg = <0x43f94000 0x4000>; | |
56 | interrupts = <32>; | |
ef0e4a60 FE |
57 | clocks = <&clks 10>, <&clks 31>; |
58 | clock-names = "ipg", "per"; | |
d2a37b3d DGC |
59 | status = "disabled"; |
60 | }; | |
61 | ||
62 | uart4: serial@43fb0000 { | |
63 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | |
64 | reg = <0x43fb0000 0x4000>; | |
ef0e4a60 FE |
65 | clocks = <&clks 10>, <&clks 49>; |
66 | clock-names = "ipg", "per"; | |
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67 | interrupts = <46>; |
68 | status = "disabled"; | |
69 | }; | |
70 | ||
71 | uart5: serial@43fb4000 { | |
72 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | |
73 | reg = <0x43fb4000 0x4000>; | |
74 | interrupts = <47>; | |
ef0e4a60 FE |
75 | clocks = <&clks 10>, <&clks 50>; |
76 | clock-names = "ipg", "per"; | |
d2a37b3d DGC |
77 | status = "disabled"; |
78 | }; | |
79 | }; | |
80 | ||
81 | spba@50000000 { | |
82 | compatible = "fsl,spba-bus", "simple-bus"; | |
83 | #address-cells = <1>; | |
84 | #size-cells = <1>; | |
85 | reg = <0x50000000 0x100000>; | |
86 | ranges; | |
87 | ||
88 | uart3: serial@5000c000 { | |
89 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | |
90 | reg = <0x5000c000 0x4000>; | |
91 | interrupts = <18>; | |
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92 | clocks = <&clks 10>, <&clks 48>; |
93 | clock-names = "ipg", "per"; | |
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94 | status = "disabled"; |
95 | }; | |
ef0e4a60 FE |
96 | |
97 | clks: ccm@53f80000{ | |
98 | compatible = "fsl,imx31-ccm"; | |
99 | reg = <0x53f80000 0x4000>; | |
100 | interrupts = <0 31 0x04 0 53 0x04>; | |
101 | #clock-cells = <1>; | |
102 | }; | |
d2a37b3d DGC |
103 | }; |
104 | }; | |
105 | }; |