[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx31.dtsi

// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
// Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	 * The decompressor and also some bootloaders rely on a
	 * pre-existing /chosen node to be available to insert the
	 * command line and merge other ATAGS info.
	 * Also for U-Boot there must be a pre-existing /memory node.
	 */
	chosen {};
	memory { device_type = "memory"; };

	aliases {
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		spi0 = &spi1;
		spi1 = &spi2;
		spi2 = &spi3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,arm1136jf-s";
			device_type = "cpu";
			reg = <0>;
		};
	};

	avic: interrupt-controller@68000000 {
		compatible = "fsl,imx31-avic", "fsl,avic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x68000000 0x100000>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&avic>;
		ranges;

		iram: iram@1fffc000 {
			compatible = "mmio-sram";
			reg = <0x1fffc000 0x4000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x1fffc000 0x4000>;
		};

		aips@43f00000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x43f00000 0x100000>;
			ranges;

			i2c1: i2c@43f80000 {
				compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
				reg = <0x43f80000 0x4000>;
				interrupts = <10>;
				clocks = <&clks 33>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c3: i2c@43f84000 {
				compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
				reg = <0x43f84000 0x4000>;
				interrupts = <3>;
				clocks = <&clks 35>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			ata: ata@43f8c000 {
				compatible = "fsl,imx31-pata", "fsl,imx27-pata";
				reg = <0x43f8c000 0x4000>;
				interrupts = <15>;
				clocks = <&clks 26>;
				status = "disabled";
			};

			uart1: serial@43f90000 {
				compatible = "fsl,imx31-uart", "fsl,imx21-uart";
				reg = <0x43f90000 0x4000>;
				interrupts = <45>;
				clocks = <&clks 10>, <&clks 30>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@43f94000 {
				compatible = "fsl,imx31-uart", "fsl,imx21-uart";
				reg = <0x43f94000 0x4000>;
				interrupts = <32>;
				clocks = <&clks 10>, <&clks 31>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c2: i2c@43f98000 {
				compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
				reg = <0x43f98000 0x4000>;
				interrupts = <4>;
				clocks = <&clks 34>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi1: spi@43fa4000 {
				compatible = "fsl,imx31-cspi";
				reg = <0x43fa4000 0x4000>;
				interrupts = <14>;
				clocks = <&clks 10>, <&clks 53>;
				clock-names = "ipg", "per";
				dmas = <&sdma 8 8 0>, <&sdma 9 8 0>;
				dma-names = "rx", "tx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			kpp: kpp@43fa8000 {
				compatible = "fsl,imx31-kpp", "fsl,imx21-kpp";
				reg = <0x43fa8000 0x4000>;
				interrupts = <24>;
				clocks = <&clks 46>;
				status = "disabled";
			};

			uart4: serial@43fb0000 {
				compatible = "fsl,imx31-uart", "fsl,imx21-uart";
				reg = <0x43fb0000 0x4000>;
				clocks = <&clks 10>, <&clks 49>;
				clock-names = "ipg", "per";
				interrupts = <46>;
				status = "disabled";
			};

			uart5: serial@43fb4000 {
				compatible = "fsl,imx31-uart", "fsl,imx21-uart";
				reg = <0x43fb4000 0x4000>;
				interrupts = <47>;
				clocks = <&clks 10>, <&clks 50>;
				clock-names = "ipg", "per";
				status = "disabled";
			};
		};

		spba@50000000 {
			compatible = "fsl,spba-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x50000000 0x100000>;
			ranges;

			sdhci1: sdhci@50004000 {
				compatible = "fsl,imx31-mmc";
				reg = <0x50004000 0x4000>;
				interrupts = <9>;
				clocks = <&clks 10>, <&clks 20>;
				clock-names = "ipg", "per";
				dmas = <&sdma 20 3 0>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			sdhci2: sdhci@50008000 {
				compatible = "fsl,imx31-mmc";
				reg = <0x50008000 0x4000>;
				interrupts = <8>;
				clocks = <&clks 10>, <&clks 21>;
				clock-names = "ipg", "per";
				dmas = <&sdma 21 3 0>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			uart3: serial@5000c000 {
				compatible = "fsl,imx31-uart", "fsl,imx21-uart";
				reg = <0x5000c000 0x4000>;
				interrupts = <18>;
				clocks = <&clks 10>, <&clks 48>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			spi2: spi@50010000 {
				compatible = "fsl,imx31-cspi";
				reg = <0x50010000 0x4000>;
				interrupts = <13>;
				clocks = <&clks 10>, <&clks 54>;
				clock-names = "ipg", "per";
				dmas = <&sdma 6 8 0>, <&sdma 7 8 0>;
				dma-names = "rx", "tx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			iim: iim@5001c000 {
				compatible = "fsl,imx31-iim", "fsl,imx27-iim";
				reg = <0x5001c000 0x1000>;
				interrupts = <19>;
				clocks = <&clks 25>;
			};
		};

		aips@53f00000 { /* AIPS2 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x53f00000 0x100000>;
			ranges;

			clks: ccm@53f80000{
				compatible = "fsl,imx31-ccm";
				reg = <0x53f80000 0x4000>;
				interrupts = <31>, <53>;
				#clock-cells = <1>;
			};

			spi3: spi@53f84000 {
				compatible = "fsl,imx31-cspi";
				reg = <0x53f84000 0x4000>;
				interrupts = <17>;
				clocks = <&clks 10>, <&clks 28>;
				clock-names = "ipg", "per";
				dmas = <&sdma 10 8 0>, <&sdma 11 8 0>;
				dma-names = "rx", "tx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			gpt: timer@53f90000 {
				compatible = "fsl,imx31-gpt";
				reg = <0x53f90000 0x4000>;
				interrupts = <29>;
				clocks = <&clks 10>, <&clks 22>;
				clock-names = "ipg", "per";
			};

			gpio3: gpio@53fa4000 {
				compatible = "fsl,imx31-gpio";
				reg = <0x53fa4000 0x4000>;
				interrupts = <56>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			rng@53fb0000 {
				compatible = "fsl,imx31-rnga";
				reg = <0x53fb0000 0x4000>;
				interrupts = <22>;
				clocks = <&clks 29>;
			};

			gpio1: gpio@53fcc000 {
				compatible = "fsl,imx31-gpio";
				reg = <0x53fcc000 0x4000>;
				interrupts = <52>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@53fd0000 {
				compatible = "fsl,imx31-gpio";
				reg = <0x53fd0000 0x4000>;
				interrupts = <51>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			sdma: sdma@53fd4000 {
				compatible = "fsl,imx31-sdma";
				reg = <0x53fd4000 0x4000>;
				interrupts = <34>;
				clocks = <&clks 10>, <&clks 27>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin";
			};

			rtc: rtc@53fd8000 {
				compatible = "fsl,imx31-rtc", "fsl,imx21-rtc";
				reg = <0x53fd8000 0x4000>;
				interrupts = <25>;
				clocks = <&clks 2>, <&clks 40>;
				clock-names = "ref", "ipg";
			};

			wdog: wdog@53fdc000 {
				compatible = "fsl,imx31-wdt", "fsl,imx21-wdt";
				reg = <0x53fdc000 0x4000>;
				clocks = <&clks 41>;
			};

			pwm: pwm@53fe0000 {
				compatible = "fsl,imx31-pwm", "fsl,imx27-pwm";
				reg = <0x53fe0000 0x4000>;
				interrupts = <26>;
				clocks = <&clks 10>, <&clks 42>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
				status = "disabled";
			};
		};

		emi@b8000000 { /* External Memory Interface */
			compatible = "simple-bus";
			reg = <0xb8000000 0x5000>;
			ranges;
			#address-cells = <1>;
			#size-cells = <1>;

			nfc: nand@b8000000 {
				compatible = "fsl,imx31-nand", "fsl,imx27-nand";
				reg = <0xb8000000 0x1000>;
				interrupts = <33>;
				clocks = <&clks 9>;
				dmas = <&sdma 30 17 0>;
				dma-names = "rx-tx";
				#address-cells = <1>;
				#size-cells = <1>;
				status = "disabled";
			};

			weim: weim@b8002000 {
				compatible = "fsl,imx31-weim", "fsl,imx27-weim";
				reg = <0xb8002000 0x1000>;
				clocks = <&clks 56>;
				#address-cells = <2>;
				#size-cells = <1>;
				ranges = <0 0 0xa0000000 0x08000000
					  1 0 0xa8000000 0x08000000
					  2 0 0xb0000000 0x02000000
					  3 0 0xb2000000 0x02000000
					  4 0 0xb4000000 0x02000000
					  5 0 0xb6000000 0x02000000>;
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
241f76b2 FE	1	// SPDX-License-Identifier: GPL-2.0+
241f76b2 FE	2	//
465b3d77	3	// Copyright 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
241f76b2	4	// Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
d2a37b3d	5
d2a37b3d	6	/ {
7f107887 FE	7	#address-cells = <1>;
7f107887 FE	8	#size-cells = <1>;
a971c554 FE	9	/*
	10	* The decompressor and also some bootloaders rely on a
	11	* pre-existing /chosen node to be available to insert the
	12	* command line and merge other ATAGS info.
	13	* Also for U-Boot there must be a pre-existing /memory node.
	14	*/
	15	chosen {};
7f08e6aa	16	memory { device_type = "memory"; };
7f107887	17
d2a37b3d	18	aliases {
465b3d77 VZ	19	gpio0 = &gpio1;
	20	gpio1 = &gpio2;
	21	gpio2 = &gpio3;
	22	i2c0 = &i2c1;
	23	i2c1 = &i2c2;
	24	i2c2 = &i2c3;
d2a37b3d DGC	25	serial0 = &uart1;
	26	serial1 = &uart2;
	27	serial2 = &uart3;
	28	serial3 = &uart4;
	29	serial4 = &uart5;
465b3d77 VZ	30	spi0 = &spi1;
	31	spi1 = &spi2;
	32	spi2 = &spi3;
d2a37b3d DGC	33	};
d2a37b3d DGC	34
070bd7e4	35	cpus {
d447dd88	36	#address-cells = <1>;
070bd7e4 FE	37	#size-cells = <0>;
070bd7e4 FE	38
d447dd88	39	cpu@0 {
bc6cde35	40	compatible = "arm,arm1136jf-s";
070bd7e4	41	device_type = "cpu";
d447dd88	42	reg = <0>;
070bd7e4 FE	43	};
	44	};
	45
af92305e	46	avic: interrupt-controller@68000000 {
d2a37b3d DGC	47	compatible = "fsl,imx31-avic", "fsl,avic";
	48	interrupt-controller;
	49	#interrupt-cells = <1>;
af92305e	50	reg = <0x68000000 0x100000>;
d2a37b3d DGC	51	};
	52
	53	soc {
	54	#address-cells = <1>;
	55	#size-cells = <1>;
	56	compatible = "simple-bus";
	57	interrupt-parent = <&avic>;
	58	ranges;
	59
465b3d77 VZ	60	iram: iram@1fffc000 {
	61	compatible = "mmio-sram";
	62	reg = <0x1fffc000 0x4000>;
	63	#address-cells = <1>;
	64	#size-cells = <1>;
	65	ranges = <0 0x1fffc000 0x4000>;
	66	};
	67
d2a37b3d DGC	68	aips@43f00000 { /* AIPS1 */
	69	compatible = "fsl,aips-bus", "simple-bus";
	70	#address-cells = <1>;
	71	#size-cells = <1>;
	72	reg = <0x43f00000 0x100000>;
	73	ranges;
	74
465b3d77 VZ	75	i2c1: i2c@43f80000 {
	76	compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
	77	reg = <0x43f80000 0x4000>;
	78	interrupts = <10>;
	79	clocks = <&clks 33>;
	80	#address-cells = <1>;
	81	#size-cells = <0>;
	82	status = "disabled";
	83	};
	84
	85	i2c3: i2c@43f84000 {
	86	compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
	87	reg = <0x43f84000 0x4000>;
	88	interrupts = <3>;
	89	clocks = <&clks 35>;
	90	#address-cells = <1>;
	91	#size-cells = <0>;
	92	status = "disabled";
	93	};
	94
	95	ata: ata@43f8c000 {
	96	compatible = "fsl,imx31-pata", "fsl,imx27-pata";
	97	reg = <0x43f8c000 0x4000>;
	98	interrupts = <15>;
	99	clocks = <&clks 26>;
	100	status = "disabled";
	101	};
	102
d2a37b3d DGC	103	uart1: serial@43f90000 {
	104	compatible = "fsl,imx31-uart", "fsl,imx21-uart";
	105	reg = <0x43f90000 0x4000>;
	106	interrupts = <45>;
ef0e4a60 FE	107	clocks = <&clks 10>, <&clks 30>;
ef0e4a60 FE	108	clock-names = "ipg", "per";
d2a37b3d DGC	109	status = "disabled";
	110	};
	111
	112	uart2: serial@43f94000 {
	113	compatible = "fsl,imx31-uart", "fsl,imx21-uart";
	114	reg = <0x43f94000 0x4000>;
	115	interrupts = <32>;
ef0e4a60 FE	116	clocks = <&clks 10>, <&clks 31>;
ef0e4a60 FE	117	clock-names = "ipg", "per";
d2a37b3d DGC	118	status = "disabled";
	119	};
	120
465b3d77 VZ	121	i2c2: i2c@43f98000 {
	122	compatible = "fsl,imx31-i2c", "fsl,imx21-i2c";
	123	reg = <0x43f98000 0x4000>;
	124	interrupts = <4>;
	125	clocks = <&clks 34>;
	126	#address-cells = <1>;
	127	#size-cells = <0>;
	128	status = "disabled";
	129	};
	130
	131	spi1: spi@43fa4000 {
	132	compatible = "fsl,imx31-cspi";
	133	reg = <0x43fa4000 0x4000>;
	134	interrupts = <14>;
	135	clocks = <&clks 10>, <&clks 53>;
	136	clock-names = "ipg", "per";
	137	dmas = <&sdma 8 8 0>, <&sdma 9 8 0>;
	138	dma-names = "rx", "tx";
	139	#address-cells = <1>;
	140	#size-cells = <0>;
	141	status = "disabled";
	142	};
	143
d8c8c70c AK	144	kpp: kpp@43fa8000 {
	145	compatible = "fsl,imx31-kpp", "fsl,imx21-kpp";
	146	reg = <0x43fa8000 0x4000>;
	147	interrupts = <24>;
	148	clocks = <&clks 46>;
	149	status = "disabled";
	150	};
	151
d2a37b3d DGC	152	uart4: serial@43fb0000 {
	153	compatible = "fsl,imx31-uart", "fsl,imx21-uart";
	154	reg = <0x43fb0000 0x4000>;
ef0e4a60 FE	155	clocks = <&clks 10>, <&clks 49>;
ef0e4a60 FE	156	clock-names = "ipg", "per";
d2a37b3d DGC	157	interrupts = <46>;
	158	status = "disabled";
	159	};
	160
	161	uart5: serial@43fb4000 {
	162	compatible = "fsl,imx31-uart", "fsl,imx21-uart";
	163	reg = <0x43fb4000 0x4000>;
	164	interrupts = <47>;
ef0e4a60 FE	165	clocks = <&clks 10>, <&clks 50>;
ef0e4a60 FE	166	clock-names = "ipg", "per";
d2a37b3d DGC	167	status = "disabled";
	168	};
	169	};
	170
	171	spba@50000000 {
	172	compatible = "fsl,spba-bus", "simple-bus";
	173	#address-cells = <1>;
	174	#size-cells = <1>;
	175	reg = <0x50000000 0x100000>;
	176	ranges;
	177
465b3d77 VZ	178	sdhci1: sdhci@50004000 {
	179	compatible = "fsl,imx31-mmc";
	180	reg = <0x50004000 0x4000>;
	181	interrupts = <9>;
	182	clocks = <&clks 10>, <&clks 20>;
	183	clock-names = "ipg", "per";
	184	dmas = <&sdma 20 3 0>;
	185	dma-names = "rx-tx";
	186	status = "disabled";
	187	};
	188
	189	sdhci2: sdhci@50008000 {
	190	compatible = "fsl,imx31-mmc";
	191	reg = <0x50008000 0x4000>;
	192	interrupts = <8>;
	193	clocks = <&clks 10>, <&clks 21>;
	194	clock-names = "ipg", "per";
	195	dmas = <&sdma 21 3 0>;
	196	dma-names = "rx-tx";
	197	status = "disabled";
	198	};
	199
d2a37b3d DGC	200	uart3: serial@5000c000 {
	201	compatible = "fsl,imx31-uart", "fsl,imx21-uart";
	202	reg = <0x5000c000 0x4000>;
	203	interrupts = <18>;
ef0e4a60 FE	204	clocks = <&clks 10>, <&clks 48>;
ef0e4a60 FE	205	clock-names = "ipg", "per";
d2a37b3d DGC	206	status = "disabled";
d2a37b3d DGC	207	};
ef0e4a60	208
5a2ecf0d	209	spi2: spi@50010000 {
465b3d77 VZ	210	compatible = "fsl,imx31-cspi";
	211	reg = <0x50010000 0x4000>;
	212	interrupts = <13>;
	213	clocks = <&clks 10>, <&clks 54>;
	214	clock-names = "ipg", "per";
	215	dmas = <&sdma 6 8 0>, <&sdma 7 8 0>;
	216	dma-names = "rx", "tx";
	217	#address-cells = <1>;
	218	#size-cells = <0>;
	219	status = "disabled";
	220	};
	221
9c5d5909 SH	222	iim: iim@5001c000 {
	223	compatible = "fsl,imx31-iim", "fsl,imx27-iim";
	224	reg = <0x5001c000 0x1000>;
	225	interrupts = <19>;
	226	clocks = <&clks 25>;
	227	};
d2a37b3d	228	};
a44eed9a SH	229
	230	aips@53f00000 { /* AIPS2 */
	231	compatible = "fsl,aips-bus", "simple-bus";
	232	#address-cells = <1>;
	233	#size-cells = <1>;
	234	reg = <0x53f00000 0x100000>;
	235	ranges;
	236
1f87aee6 VZ	237	clks: ccm@53f80000{
	238	compatible = "fsl,imx31-ccm";
	239	reg = <0x53f80000 0x4000>;
	240	interrupts = <31>, <53>;
	241	#clock-cells = <1>;
	242	};
	243
5a2ecf0d	244	spi3: spi@53f84000 {
465b3d77 VZ	245	compatible = "fsl,imx31-cspi";
	246	reg = <0x53f84000 0x4000>;
	247	interrupts = <17>;
	248	clocks = <&clks 10>, <&clks 28>;
	249	clock-names = "ipg", "per";
	250	dmas = <&sdma 10 8 0>, <&sdma 11 8 0>;
	251	dma-names = "rx", "tx";
	252	#address-cells = <1>;
	253	#size-cells = <0>;
	254	status = "disabled";
	255	};
	256
a44eed9a SH	257	gpt: timer@53f90000 {
	258	compatible = "fsl,imx31-gpt";
	259	reg = <0x53f90000 0x4000>;
	260	interrupts = <29>;
	261	clocks = <&clks 10>, <&clks 22>;
	262	clock-names = "ipg", "per";
	263	};
465b3d77 VZ	264
	265	gpio3: gpio@53fa4000 {
	266	compatible = "fsl,imx31-gpio";
	267	reg = <0x53fa4000 0x4000>;
	268	interrupts = <56>;
	269	gpio-controller;
	270	#gpio-cells = <2>;
	271	interrupt-controller;
	272	#interrupt-cells = <2>;
	273	};
	274
	275	rng@53fb0000 {
	276	compatible = "fsl,imx31-rnga";
	277	reg = <0x53fb0000 0x4000>;
	278	interrupts = <22>;
	279	clocks = <&clks 29>;
	280	};
	281
	282	gpio1: gpio@53fcc000 {
	283	compatible = "fsl,imx31-gpio";
	284	reg = <0x53fcc000 0x4000>;
	285	interrupts = <52>;
	286	gpio-controller;
	287	#gpio-cells = <2>;
	288	interrupt-controller;
	289	#interrupt-cells = <2>;
	290	};
	291
	292	gpio2: gpio@53fd0000 {
	293	compatible = "fsl,imx31-gpio";
	294	reg = <0x53fd0000 0x4000>;
	295	interrupts = <51>;
	296	gpio-controller;
	297	#gpio-cells = <2>;
	298	interrupt-controller;
	299	#interrupt-cells = <2>;
	300	};
	301
	302	sdma: sdma@53fd4000 {
	303	compatible = "fsl,imx31-sdma";
	304	reg = <0x53fd4000 0x4000>;
	305	interrupts = <34>;
	306	clocks = <&clks 10>, <&clks 27>;
	307	clock-names = "ipg", "ahb";
	308	#dma-cells = <3>;
	309	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin";
	310	};
	311
	312	rtc: rtc@53fd8000 {
	313	compatible = "fsl,imx31-rtc", "fsl,imx21-rtc";
	314	reg = <0x53fd8000 0x4000>;
	315	interrupts = <25>;
	316	clocks = <&clks 2>, <&clks 40>;
	317	clock-names = "ref", "ipg";
	318	};
	319
	320	wdog: wdog@53fdc000 {
	321	compatible = "fsl,imx31-wdt", "fsl,imx21-wdt";
	322	reg = <0x53fdc000 0x4000>;
	323	clocks = <&clks 41>;
	324	};
	325
	326	pwm: pwm@53fe0000 {
	327	compatible = "fsl,imx31-pwm", "fsl,imx27-pwm";
328	reg = <0x53fe0000 0x4000>;
329	interrupts = <26>;
330	clocks = <&clks 10>, <&clks 42>;
331	clock-names = "ipg", "per";
332	#pwm-cells = <2>;
333	status = "disabled";
334	};
335	};
336
337	emi@b8000000 { /* External Memory Interface */
338	compatible = "simple-bus";
339	reg = <0xb8000000 0x5000>;
340	ranges;
341	#address-cells = <1>;
342	#size-cells = <1>;
343
344	nfc: nand@b8000000 {
345	compatible = "fsl,imx31-nand", "fsl,imx27-nand";
346	reg = <0xb8000000 0x1000>;
347	interrupts = <33>;
348	clocks = <&clks 9>;
349	dmas = <&sdma 30 17 0>;
350	dma-names = "rx-tx";
351	#address-cells = <1>;
352	#size-cells = <1>;
353	status = "disabled";
354	};
355
356	weim: weim@b8002000 {
357	compatible = "fsl,imx31-weim", "fsl,imx27-weim";
358	reg = <0xb8002000 0x1000>;
359	clocks = <&clks 56>;
360	#address-cells = <2>;
361	#size-cells = <1>;
362	ranges = <0 0 0xa0000000 0x08000000
363	1 0 0xa8000000 0x08000000
364	2 0 0xb0000000 0x02000000
365	3 0 0xb2000000 0x02000000
366	4 0 0xb4000000 0x02000000
367	5 0 0xb6000000 0x02000000>;
368	status = "disabled";
369	};
a44eed9a	370	};
d2a37b3d DGC	371	};
d2a37b3d DGC	372	};