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Merge tag 'xtensa-20190715' of git://github.com/jcmvbkbc/linux-xtensa
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx35-eukrea-mbimxsd35-baseboard.dts
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c942fddf 1// SPDX-License-Identifier: GPL-2.0-or-later
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2/*
3 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
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4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10#include "imx35-eukrea-cpuimx35.dtsi"
11
12/ {
13 model = "Eukrea CPUIMX35";
14 compatible = "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35";
15
16 gpio_keys {
17 compatible = "gpio-keys";
18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_bp1>;
20
21 bp1 {
22 label = "BP1";
23 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
24 linux,code = <BTN_MISC>;
26cefdd1 25 wakeup-source;
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26 linux,input-type = <1>;
27 };
28 };
29
30 leds {
31 compatible = "gpio-leds";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_led1>;
34
35 led1 {
36 label = "led1";
37 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
38 linux,default-trigger = "heartbeat";
39 };
40 };
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41
42 sound {
43 compatible = "eukrea,asoc-tlv320";
44 eukrea,model = "imx35-eukrea-tlv320aic23";
45 ssi-controller = <&ssi1>;
46 fsl,mux-int-port = <1>;
47 fsl,mux-ext-port = <4>;
48 };
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49};
50
51&audmux {
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_audmux>;
54 status = "okay";
55};
56
57&esdhc1 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_esdhc1>;
2dee62e0 60 cd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
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61 status = "okay";
62};
63
64&i2c1 {
65 tlv320aic23: codec@1a {
66 compatible = "ti,tlv320aic23";
67 reg = <0x1a>;
68 };
69};
70
71&iomuxc {
72 imx35-eukrea {
73 pinctrl_audmux: audmuxgrp {
74 fsl,pins = <
75 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS 0x80000000
76 MX35_PAD_STXD4__AUDMUX_AUD4_TXD 0x80000000
77 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD 0x80000000
78 MX35_PAD_SCK4__AUDMUX_AUD4_TXC 0x80000000
79 >;
80 };
81
82 pinctrl_bp1: bp1grp {
83 fsl,pins = <MX35_PAD_LD19__GPIO3_25 0x80000000>;
84 };
85
86 pinctrl_esdhc1: esdhc1grp {
87 fsl,pins = <
88 MX35_PAD_SD1_CMD__ESDHC1_CMD 0x80000000
89 MX35_PAD_SD1_CLK__ESDHC1_CLK 0x80000000
90 MX35_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000
91 MX35_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000
92 MX35_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000
93 MX35_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000
94 MX35_PAD_LD18__GPIO3_24 0x80000000 /* CD */
95 >;
96 };
97
98 pinctrl_led1: led1grp {
99 fsl,pins = <MX35_PAD_LD23__GPIO3_29 0x80000000>;
100 };
101
102 pinctrl_reg_lcd_3v3: reg-lcd-3v3 {
103 fsl,pins = <MX35_PAD_D3_CLS__GPIO1_4 0x80000000>;
104 };
105
106 pinctrl_uart1: uart1grp {
107 fsl,pins = <
108 MX35_PAD_TXD1__UART1_TXD_MUX 0x1c5
109 MX35_PAD_RXD1__UART1_RXD_MUX 0x1c5
110 MX35_PAD_CTS1__UART1_CTS 0x1c5
111 MX35_PAD_RTS1__UART1_RTS 0x1c5
112 >;
113 };
114
115 pinctrl_uart2: uart2grp {
116 fsl,pins = <
117 MX35_PAD_RXD2__UART2_RXD_MUX 0x1c5
118 MX35_PAD_TXD2__UART2_TXD_MUX 0x1c5
119 MX35_PAD_RTS2__UART2_RTS 0x1c5
120 MX35_PAD_CTS2__UART2_CTS 0x1c5
121 >;
122 };
123 };
124};
125
126&ssi1 {
499c8bf5 127 codec-handle = <&tlv320aic23>;
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128 status = "okay";
129};
130
131&uart1 {
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_uart1>;
2e7c416c 134 uart-has-rtscts;
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135 status = "okay";
136};
137
138&uart2 {
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_uart2>;
2e7c416c 141 uart-has-rtscts;
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142 status = "okay";
143};
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144
145&usbhost1 {
146 phy_type = "serial";
147 dr_mode = "host";
148 status = "okay";
149};
150
151&usbotg {
152 phy_type = "utmi";
153 dr_mode = "otg";
154 external-vbus-divider;
155 status = "okay";
156};