[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / imx50.dtsi

/*
 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "skeleton.dtsi"
#include "imx50-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>

/ {
	aliases {
		ethernet0 = &fec;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0x0>;
		};
	};

	tzic: tz-interrupt-controller@0fffc000 {
		compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x0fffc000 0x4000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		ckil {
			compatible = "fsl,imx-ckil", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};

		ckih1 {
			compatible = "fsl,imx-ckih1", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <22579200>;
		};

		ckih2 {
			compatible = "fsl,imx-ckih2", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		osc {
			compatible = "fsl,imx-osc", "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&tzic>;
		ranges;

		aips@50000000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x50000000 0x10000000>;
			ranges;

			spba@50000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x50000000 0x40000>;
				ranges;

				esdhc1: esdhc@50004000 {
					compatible = "fsl,imx50-esdhc";
					reg = <0x50004000 0x4000>;
					interrupts = <1>;
					clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC1_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				esdhc2: esdhc@50008000 {
					compatible = "fsl,imx50-esdhc";
					reg = <0x50008000 0x4000>;
					interrupts = <2>;
					clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC2_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				uart3: serial@5000c000 {
					compatible = "fsl,imx50-uart", "fsl,imx21-uart";
					reg = <0x5000c000 0x4000>;
					interrupts = <33>;
					clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
					         <&clks IMX5_CLK_UART3_PER_GATE>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi1: ecspi@50010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
					reg = <0x50010000 0x4000>;
					interrupts = <36>;
					clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
					         <&clks IMX5_CLK_ECSPI1_PER_GATE>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ssi2: ssi@50014000 {
					compatible = "fsl,imx50-ssi",
							"fsl,imx51-ssi",
							"fsl,imx21-ssi";
					reg = <0x50014000 0x4000>;
					interrupts = <30>;
					clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
					fsl,fifo-depth = <15>;
					fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
					status = "disabled";
				};

				esdhc3: esdhc@50020000 {
					compatible = "fsl,imx50-esdhc";
					reg = <0x50020000 0x4000>;
					interrupts = <3>;
					clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC3_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				esdhc4: esdhc@50024000 {
					compatible = "fsl,imx50-esdhc";
					reg = <0x50024000 0x4000>;
					interrupts = <4>;
					clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
					         <&clks IMX5_CLK_DUMMY>,
					         <&clks IMX5_CLK_ESDHC4_PER_GATE>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};
			};

			usbotg: usb@53f80000 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80000 0x0200>;
				interrupts = <18>;
				clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
				status = "disabled";
			};

			usbh1: usb@53f80200 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80200 0x0200>;
				interrupts = <14>;
				clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
				status = "disabled";
			};

			usbh2: usb@53f80400 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80400 0x0200>;
				interrupts = <16>;
				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
				status = "disabled";
			};

			usbh3: usb@53f80600 {
				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
				reg = <0x53f80600 0x0200>;
				interrupts = <17>;
				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
				status = "disabled";
			};

			gpio1: gpio@53f84000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f84000 0x4000>;
				interrupts = <50 51>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@53f88000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f88000 0x4000>;
				interrupts = <52 53>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@53f8c000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f8c000 0x4000>;
				interrupts = <54 55>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@53f90000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53f90000 0x4000>;
				interrupts = <56 57>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			wdog1: wdog@53f98000 {
				compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
				reg = <0x53f98000 0x4000>;
				interrupts = <58>;
				clocks = <&clks IMX5_CLK_DUMMY>;
			};

			gpt: timer@53fa0000 {
				compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
				reg = <0x53fa0000 0x4000>;
				interrupts = <39>;
				clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
				         <&clks IMX5_CLK_GPT_HF_GATE>;
				clock-names = "ipg", "per";
			};

			iomuxc: iomuxc@53fa8000 {
				compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
				reg = <0x53fa8000 0x4000>;
			};

			gpr: iomuxc-gpr@53fa8000 {
				compatible = "fsl,imx50-iomuxc-gpr", "syscon";
				reg = <0x53fa8000 0xc>;
			};

			pwm1: pwm@53fb4000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
				reg = <0x53fb4000 0x4000>;
				clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
				         <&clks IMX5_CLK_PWM1_HF_GATE>;
				clock-names = "ipg", "per";
				interrupts = <61>;
			};

			pwm2: pwm@53fb8000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
				reg = <0x53fb8000 0x4000>;
				clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
				         <&clks IMX5_CLK_PWM2_HF_GATE>;
				clock-names = "ipg", "per";
				interrupts = <94>;
			};

			uart1: serial@53fbc000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x53fbc000 0x4000>;
				interrupts = <31>;
				clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
				         <&clks IMX5_CLK_UART1_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@53fc0000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x53fc0000 0x4000>;
				interrupts = <32>;
				clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
				         <&clks IMX5_CLK_UART2_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			src: src@53fd0000 {
				compatible = "fsl,imx50-src", "fsl,imx51-src";
				reg = <0x53fd0000 0x4000>;
				#reset-cells = <1>;
			};

			clks: ccm@53fd4000{
				compatible = "fsl,imx50-ccm";
				reg = <0x53fd4000 0x4000>;
				interrupts = <0 71 0x04 0 72 0x04>;
				#clock-cells = <1>;
			};

			gpio5: gpio@53fdc000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53fdc000 0x4000>;
				interrupts = <103 104>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio6: gpio@53fe0000 {
				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
				reg = <0x53fe0000 0x4000>;
				interrupts = <105 106>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			i2c3: i2c@53fec000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
				reg = <0x53fec000 0x4000>;
				interrupts = <64>;
				clocks = <&clks IMX5_CLK_I2C3_GATE>;
				status = "disabled";
			};

			uart4: serial@53ff0000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x53ff0000 0x4000>;
				interrupts = <13>;
				clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
				         <&clks IMX5_CLK_UART4_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};
		};

		aips@60000000 {	/* AIPS2 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x60000000 0x10000000>;
			ranges;

			uart5: serial@63f90000 {
				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
				reg = <0x63f90000 0x4000>;
				interrupts = <86>;
				clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
				         <&clks IMX5_CLK_UART5_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			owire: owire@63fa4000 {
				compatible = "fsl,imx50-owire", "fsl,imx21-owire";
				reg = <0x63fa4000 0x4000>;
				clocks = <&clks IMX5_CLK_OWIRE_GATE>;
				status = "disabled";
			};

			ecspi2: ecspi@63fac000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
				reg = <0x63fac000 0x4000>;
				interrupts = <37>;
				clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
				         <&clks IMX5_CLK_ECSPI2_PER_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			sdma: sdma@63fb0000 {
				compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
				reg = <0x63fb0000 0x4000>;
				interrupts = <6>;
				clocks = <&clks IMX5_CLK_SDMA_GATE>,
				         <&clks IMX5_CLK_SDMA_GATE>;
				clock-names = "ipg", "ahb";
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
			};

			cspi: cspi@63fc0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
				reg = <0x63fc0000 0x4000>;
				interrupts = <38>;
				clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
				         <&clks IMX5_CLK_CSPI_IPG_GATE>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c2: i2c@63fc4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
				reg = <0x63fc4000 0x4000>;
				interrupts = <63>;
				clocks = <&clks IMX5_CLK_I2C2_GATE>;
				status = "disabled";
			};

			i2c1: i2c@63fc8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
				reg = <0x63fc8000 0x4000>;
				interrupts = <62>;
				clocks = <&clks IMX5_CLK_I2C1_GATE>;
				status = "disabled";
			};

			ssi1: ssi@63fcc000 {
				compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
							"fsl,imx21-ssi";
				reg = <0x63fcc000 0x4000>;
				interrupts = <29>;
				clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
				fsl,fifo-depth = <15>;
				fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
				status = "disabled";
			};

			audmux: audmux@63fd0000 {
				compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
				reg = <0x63fd0000 0x4000>;
				status = "disabled";
			};

			fec: ethernet@63fec000 {
				compatible = "fsl,imx53-fec", "fsl,imx25-fec";
				reg = <0x63fec000 0x4000>;
				interrupts = <87>;
				clocks = <&clks IMX5_CLK_FEC_GATE>,
				         <&clks IMX5_CLK_FEC_GATE>,
				         <&clks IMX5_CLK_FEC_GATE>;
				clock-names = "ipg", "ahb", "ptp";
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
64972acd GU	1	/*
	2	* Copyright 2013 Greg Ungerer <gerg@uclinux.org>
	3	* Copyright 2011 Freescale Semiconductor, Inc.
	4	* Copyright 2011 Linaro Ltd.
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
	14	#include "skeleton.dtsi"
	15	#include "imx50-pinfunc.h"
6650d6db	16	#include <dt-bindings/clock/imx5-clock.h>
64972acd GU	17
	18	/ {
	19	aliases {
22970070	20	ethernet0 = &fec;
64972acd GU	21	gpio0 = &gpio1;
	22	gpio1 = &gpio2;
	23	gpio2 = &gpio3;
	24	gpio3 = &gpio4;
	25	gpio4 = &gpio5;
	26	gpio5 = &gpio6;
	27	serial0 = &uart1;
	28	serial1 = &uart2;
	29	serial2 = &uart3;
	30	serial3 = &uart4;
	31	serial4 = &uart5;
	32	};
	33
	34	cpus {
	35	#address-cells = <1>;
	36	#size-cells = <0>;
	37	cpu@0 {
	38	device_type = "cpu";
	39	compatible = "arm,cortex-a8";
	40	reg = <0x0>;
	41	};
	42	};
	43
	44	tzic: tz-interrupt-controller@0fffc000 {
	45	compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
	46	interrupt-controller;
	47	#interrupt-cells = <1>;
	48	reg = <0x0fffc000 0x4000>;
	49	};
	50
	51	clocks {
	52	#address-cells = <1>;
	53	#size-cells = <0>;
	54
	55	ckil {
	56	compatible = "fsl,imx-ckil", "fixed-clock";
4b2b4043	57	#clock-cells = <0>;
64972acd GU	58	clock-frequency = <32768>;
	59	};
	60
	61	ckih1 {
	62	compatible = "fsl,imx-ckih1", "fixed-clock";
4b2b4043	63	#clock-cells = <0>;
64972acd GU	64	clock-frequency = <22579200>;
	65	};
	66
	67	ckih2 {
	68	compatible = "fsl,imx-ckih2", "fixed-clock";
4b2b4043	69	#clock-cells = <0>;
64972acd GU	70	clock-frequency = <0>;
	71	};
	72
	73	osc {
	74	compatible = "fsl,imx-osc", "fixed-clock";
4b2b4043	75	#clock-cells = <0>;
64972acd GU	76	clock-frequency = <24000000>;
	77	};
	78	};
	79
	80	soc {
	81	#address-cells = <1>;
	82	#size-cells = <1>;
	83	compatible = "simple-bus";
	84	interrupt-parent = <&tzic>;
	85	ranges;
	86
	87	aips@50000000 { /* AIPS1 */
	88	compatible = "fsl,aips-bus", "simple-bus";
	89	#address-cells = <1>;
	90	#size-cells = <1>;
	91	reg = <0x50000000 0x10000000>;
	92	ranges;
	93
	94	spba@50000000 {
	95	compatible = "fsl,spba-bus", "simple-bus";
	96	#address-cells = <1>;
	97	#size-cells = <1>;
	98	reg = <0x50000000 0x40000>;
	99	ranges;
	100
	101	esdhc1: esdhc@50004000 {
	102	compatible = "fsl,imx50-esdhc";
	103	reg = <0x50004000 0x4000>;
	104	interrupts = <1>;
6650d6db LS	105	clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
	106	<&clks IMX5_CLK_DUMMY>,
	107	<&clks IMX5_CLK_ESDHC1_PER_GATE>;
64972acd GU	108	clock-names = "ipg", "ahb", "per";
	109	bus-width = <4>;
	110	status = "disabled";
	111	};
	112
	113	esdhc2: esdhc@50008000 {
	114	compatible = "fsl,imx50-esdhc";
	115	reg = <0x50008000 0x4000>;
	116	interrupts = <2>;
6650d6db LS	117	clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
	118	<&clks IMX5_CLK_DUMMY>,
	119	<&clks IMX5_CLK_ESDHC2_PER_GATE>;
64972acd GU	120	clock-names = "ipg", "ahb", "per";
	121	bus-width = <4>;
	122	status = "disabled";
	123	};
	124
	125	uart3: serial@5000c000 {
	126	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	127	reg = <0x5000c000 0x4000>;
	128	interrupts = <33>;
6650d6db LS	129	clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
6650d6db LS	130	<&clks IMX5_CLK_UART3_PER_GATE>;
64972acd GU	131	clock-names = "ipg", "per";
	132	status = "disabled";
	133	};
	134
	135	ecspi1: ecspi@50010000 {
	136	#address-cells = <1>;
	137	#size-cells = <0>;
	138	compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
	139	reg = <0x50010000 0x4000>;
	140	interrupts = <36>;
6650d6db LS	141	clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
6650d6db LS	142	<&clks IMX5_CLK_ECSPI1_PER_GATE>;
64972acd GU	143	clock-names = "ipg", "per";
	144	status = "disabled";
	145	};
	146
	147	ssi2: ssi@50014000 {
28f93d0b MP	148	compatible = "fsl,imx50-ssi",
	149	"fsl,imx51-ssi",
	150	"fsl,imx21-ssi";
64972acd GU	151	reg = <0x50014000 0x4000>;
64972acd GU	152	interrupts = <30>;
6650d6db	153	clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
64972acd GU	154	fsl,fifo-depth = <15>;
	155	fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
	156	status = "disabled";
	157	};
	158
	159	esdhc3: esdhc@50020000 {
	160	compatible = "fsl,imx50-esdhc";
	161	reg = <0x50020000 0x4000>;
	162	interrupts = <3>;
6650d6db LS	163	clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
	164	<&clks IMX5_CLK_DUMMY>,
	165	<&clks IMX5_CLK_ESDHC3_PER_GATE>;
64972acd GU	166	clock-names = "ipg", "ahb", "per";
	167	bus-width = <4>;
	168	status = "disabled";
	169	};
	170
	171	esdhc4: esdhc@50024000 {
	172	compatible = "fsl,imx50-esdhc";
	173	reg = <0x50024000 0x4000>;
	174	interrupts = <4>;
6650d6db LS	175	clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
	176	<&clks IMX5_CLK_DUMMY>,
	177	<&clks IMX5_CLK_ESDHC4_PER_GATE>;
64972acd GU	178	clock-names = "ipg", "ahb", "per";
	179	bus-width = <4>;
	180	status = "disabled";
	181	};
	182	};
	183
	184	usbotg: usb@53f80000 {
	185	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	186	reg = <0x53f80000 0x0200>;
	187	interrupts = <18>;
6650d6db	188	clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
64972acd GU	189	status = "disabled";
	190	};
	191
	192	usbh1: usb@53f80200 {
	193	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	194	reg = <0x53f80200 0x0200>;
	195	interrupts = <14>;
6650d6db	196	clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
64972acd GU	197	status = "disabled";
	198	};
	199
	200	usbh2: usb@53f80400 {
	201	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	202	reg = <0x53f80400 0x0200>;
	203	interrupts = <16>;
6650d6db	204	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
64972acd GU	205	status = "disabled";
	206	};
	207
	208	usbh3: usb@53f80600 {
	209	compatible = "fsl,imx50-usb", "fsl,imx27-usb";
	210	reg = <0x53f80600 0x0200>;
	211	interrupts = <17>;
6650d6db	212	clocks = <&clks IMX5_CLK_USBOH3_GATE>;
64972acd GU	213	status = "disabled";
	214	};
	215
	216	gpio1: gpio@53f84000 {
	217	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	218	reg = <0x53f84000 0x4000>;
	219	interrupts = <50 51>;
	220	gpio-controller;
	221	#gpio-cells = <2>;
	222	interrupt-controller;
	223	#interrupt-cells = <2>;
	224	};
	225
	226	gpio2: gpio@53f88000 {
	227	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	228	reg = <0x53f88000 0x4000>;
	229	interrupts = <52 53>;
	230	gpio-controller;
	231	#gpio-cells = <2>;
	232	interrupt-controller;
	233	#interrupt-cells = <2>;
	234	};
	235
	236	gpio3: gpio@53f8c000 {
	237	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	238	reg = <0x53f8c000 0x4000>;
	239	interrupts = <54 55>;
	240	gpio-controller;
	241	#gpio-cells = <2>;
	242	interrupt-controller;
	243	#interrupt-cells = <2>;
	244	};
	245
	246	gpio4: gpio@53f90000 {
	247	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	248	reg = <0x53f90000 0x4000>;
	249	interrupts = <56 57>;
	250	gpio-controller;
	251	#gpio-cells = <2>;
	252	interrupt-controller;
	253	#interrupt-cells = <2>;
	254	};
	255
	256	wdog1: wdog@53f98000 {
	257	compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
	258	reg = <0x53f98000 0x4000>;
	259	interrupts = <58>;
6650d6db	260	clocks = <&clks IMX5_CLK_DUMMY>;
64972acd GU	261	};
	262
	263	gpt: timer@53fa0000 {
	264	compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
	265	reg = <0x53fa0000 0x4000>;
	266	interrupts = <39>;
6650d6db LS	267	clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
6650d6db LS	268	<&clks IMX5_CLK_GPT_HF_GATE>;
64972acd GU	269	clock-names = "ipg", "per";
	270	};
	271
	272	iomuxc: iomuxc@53fa8000 {
	273	compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
	274	reg = <0x53fa8000 0x4000>;
	275	};
	276
	277	gpr: iomuxc-gpr@53fa8000 {
	278	compatible = "fsl,imx50-iomuxc-gpr", "syscon";
	279	reg = <0x53fa8000 0xc>;
	280	};
	281
	282	pwm1: pwm@53fb4000 {
	283	#pwm-cells = <2>;
	284	compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
	285	reg = <0x53fb4000 0x4000>;
6650d6db LS	286	clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
6650d6db LS	287	<&clks IMX5_CLK_PWM1_HF_GATE>;
64972acd GU	288	clock-names = "ipg", "per";
	289	interrupts = <61>;
	290	};
	291
	292	pwm2: pwm@53fb8000 {
	293	#pwm-cells = <2>;
	294	compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
	295	reg = <0x53fb8000 0x4000>;
6650d6db LS	296	clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
6650d6db LS	297	<&clks IMX5_CLK_PWM2_HF_GATE>;
64972acd GU	298	clock-names = "ipg", "per";
	299	interrupts = <94>;
	300	};
	301
	302	uart1: serial@53fbc000 {
	303	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	304	reg = <0x53fbc000 0x4000>;
	305	interrupts = <31>;
6650d6db LS	306	clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
6650d6db LS	307	<&clks IMX5_CLK_UART1_PER_GATE>;
64972acd GU	308	clock-names = "ipg", "per";
	309	status = "disabled";
	310	};
	311
	312	uart2: serial@53fc0000 {
	313	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	314	reg = <0x53fc0000 0x4000>;
	315	interrupts = <32>;
6650d6db LS	316	clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
6650d6db LS	317	<&clks IMX5_CLK_UART2_PER_GATE>;
64972acd GU	318	clock-names = "ipg", "per";
	319	status = "disabled";
	320	};
	321
	322	src: src@53fd0000 {
	323	compatible = "fsl,imx50-src", "fsl,imx51-src";
	324	reg = <0x53fd0000 0x4000>;
	325	#reset-cells = <1>;
	326	};
	327
	328	clks: ccm@53fd4000{
	329	compatible = "fsl,imx50-ccm";
	330	reg = <0x53fd4000 0x4000>;
	331	interrupts = <0 71 0x04 0 72 0x04>;
	332	#clock-cells = <1>;
	333	};
	334
	335	gpio5: gpio@53fdc000 {
	336	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	337	reg = <0x53fdc000 0x4000>;
	338	interrupts = <103 104>;
	339	gpio-controller;
	340	#gpio-cells = <2>;
	341	interrupt-controller;
	342	#interrupt-cells = <2>;
	343	};
	344
	345	gpio6: gpio@53fe0000 {
	346	compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
	347	reg = <0x53fe0000 0x4000>;
	348	interrupts = <105 106>;
	349	gpio-controller;
	350	#gpio-cells = <2>;
	351	interrupt-controller;
	352	#interrupt-cells = <2>;
	353	};
	354
	355	i2c3: i2c@53fec000 {
	356	#address-cells = <1>;
	357	#size-cells = <0>;
	358	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	359	reg = <0x53fec000 0x4000>;
	360	interrupts = <64>;
6650d6db	361	clocks = <&clks IMX5_CLK_I2C3_GATE>;
64972acd GU	362	status = "disabled";
	363	};
	364
	365	uart4: serial@53ff0000 {
	366	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	367	reg = <0x53ff0000 0x4000>;
	368	interrupts = <13>;
6650d6db LS	369	clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
6650d6db LS	370	<&clks IMX5_CLK_UART4_PER_GATE>;
64972acd GU	371	clock-names = "ipg", "per";
	372	status = "disabled";
	373	};
	374	};
	375
	376	aips@60000000 { /* AIPS2 */
	377	compatible = "fsl,aips-bus", "simple-bus";
	378	#address-cells = <1>;
	379	#size-cells = <1>;
	380	reg = <0x60000000 0x10000000>;
	381	ranges;
	382
	383	uart5: serial@63f90000 {
	384	compatible = "fsl,imx50-uart", "fsl,imx21-uart";
	385	reg = <0x63f90000 0x4000>;
	386	interrupts = <86>;
6650d6db LS	387	clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
6650d6db LS	388	<&clks IMX5_CLK_UART5_PER_GATE>;
64972acd GU	389	clock-names = "ipg", "per";
	390	status = "disabled";
	391	};
	392
	393	owire: owire@63fa4000 {
	394	compatible = "fsl,imx50-owire", "fsl,imx21-owire";
	395	reg = <0x63fa4000 0x4000>;
6650d6db	396	clocks = <&clks IMX5_CLK_OWIRE_GATE>;
64972acd GU	397	status = "disabled";
	398	};
	399
	400	ecspi2: ecspi@63fac000 {
	401	#address-cells = <1>;
	402	#size-cells = <0>;
	403	compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
	404	reg = <0x63fac000 0x4000>;
	405	interrupts = <37>;
6650d6db LS	406	clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
6650d6db LS	407	<&clks IMX5_CLK_ECSPI2_PER_GATE>;
64972acd GU	408	clock-names = "ipg", "per";
	409	status = "disabled";
	410	};
	411
	412	sdma: sdma@63fb0000 {
	413	compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
	414	reg = <0x63fb0000 0x4000>;
	415	interrupts = <6>;
6650d6db LS	416	clocks = <&clks IMX5_CLK_SDMA_GATE>,
6650d6db LS	417	<&clks IMX5_CLK_SDMA_GATE>;
64972acd GU	418	clock-names = "ipg", "ahb";
	419	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
	420	};
	421
	422	cspi: cspi@63fc0000 {
	423	#address-cells = <1>;
	424	#size-cells = <0>;
	425	compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
	426	reg = <0x63fc0000 0x4000>;
	427	interrupts = <38>;
6650d6db LS	428	clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
6650d6db LS	429	<&clks IMX5_CLK_CSPI_IPG_GATE>;
64972acd GU	430	clock-names = "ipg", "per";
	431	status = "disabled";
	432	};
	433
	434	i2c2: i2c@63fc4000 {
	435	#address-cells = <1>;
	436	#size-cells = <0>;
	437	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	438	reg = <0x63fc4000 0x4000>;
	439	interrupts = <63>;
6650d6db	440	clocks = <&clks IMX5_CLK_I2C2_GATE>;
64972acd GU	441	status = "disabled";
	442	};
	443
	444	i2c1: i2c@63fc8000 {
	445	#address-cells = <1>;
	446	#size-cells = <0>;
	447	compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
	448	reg = <0x63fc8000 0x4000>;
	449	interrupts = <62>;
6650d6db	450	clocks = <&clks IMX5_CLK_I2C1_GATE>;
64972acd GU	451	status = "disabled";
	452	};
	453
	454	ssi1: ssi@63fcc000 {
28f93d0b MP	455	compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
28f93d0b MP	456	"fsl,imx21-ssi";
64972acd GU	457	reg = <0x63fcc000 0x4000>;
64972acd GU	458	interrupts = <29>;
6650d6db	459	clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
64972acd GU	460	fsl,fifo-depth = <15>;
	461	fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
	462	status = "disabled";
	463	};
	464
	465	audmux: audmux@63fd0000 {
	466	compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
	467	reg = <0x63fd0000 0x4000>;
	468	status = "disabled";
	469	};
	470
	471	fec: ethernet@63fec000 {
	472	compatible = "fsl,imx53-fec", "fsl,imx25-fec";
	473	reg = <0x63fec000 0x4000>;
	474	interrupts = <87>;
6650d6db LS	475	clocks = <&clks IMX5_CLK_FEC_GATE>,
	476	<&clks IMX5_CLK_FEC_GATE>,
	477	<&clks IMX5_CLK_FEC_GATE>;
64972acd GU	478	clock-names = "ipg", "ahb", "ptp";
	479	status = "disabled";
	480	};
	481	};
	482	};
	483	};