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40906354 AS |
1 | /* |
2 | * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | #include "imx51-digi-connectcore-som.dtsi" | |
13 | ||
14 | / { | |
15 | model = "Digi ConnectCore CC(W)-MX51 JSK"; | |
16 | compatible = "digi,connectcore-ccxmx51-jsk", | |
17 | "digi,connectcore-ccxmx51-som", "fsl,imx51"; | |
18 | ||
19 | chosen { | |
20 | linux,stdout-path = &uart1; | |
21 | }; | |
22 | }; | |
23 | ||
24 | &owire { | |
25 | pinctrl-names = "default"; | |
26 | pinctrl-0 = <&pinctrl_owire>; | |
27 | status = "okay"; | |
28 | }; | |
29 | ||
30 | &uart1 { | |
31 | pinctrl-names = "default"; | |
32 | pinctrl-0 = <&pinctrl_uart1>; | |
33 | status = "okay"; | |
34 | }; | |
35 | ||
36 | &uart2 { | |
37 | pinctrl-names = "default"; | |
38 | pinctrl-0 = <&pinctrl_uart2>; | |
39 | status = "okay"; | |
40 | }; | |
41 | ||
42 | &uart3 { | |
43 | pinctrl-names = "default"; | |
44 | pinctrl-0 = <&pinctrl_uart3>; | |
45 | status = "okay"; | |
46 | }; | |
47 | ||
48 | &usbotg { | |
49 | dr_mode = "otg"; | |
50 | status = "okay"; | |
51 | }; | |
52 | ||
53 | &usbh1 { | |
54 | pinctrl-names = "default"; | |
55 | pinctrl-0 = <&pinctrl_usbh1>; | |
56 | dr_mode = "host"; | |
57 | phy_type = "ulpi"; | |
58 | disable-over-current; | |
59 | status = "okay"; | |
60 | }; | |
61 | ||
62 | &iomuxc { | |
63 | imx51-digi-connectcore-jsk { | |
64 | pinctrl_owire: owiregrp { | |
65 | fsl,pins = < | |
66 | MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x40000000 | |
67 | >; | |
68 | }; | |
69 | ||
70 | pinctrl_uart1: uart1grp { | |
71 | fsl,pins = < | |
72 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 | |
73 | MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 | |
74 | >; | |
75 | }; | |
76 | ||
77 | pinctrl_uart2: uart2grp { | |
78 | fsl,pins = < | |
79 | MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 | |
80 | MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 | |
81 | >; | |
82 | }; | |
83 | ||
84 | pinctrl_uart3: uart3grp { | |
85 | fsl,pins = < | |
86 | MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 | |
87 | MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 | |
88 | >; | |
89 | }; | |
90 | ||
91 | pinctrl_usbh1: usbh1grp { | |
92 | fsl,pins = < | |
93 | MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 | |
94 | MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 | |
95 | MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 | |
96 | MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 | |
97 | MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 | |
98 | MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 | |
99 | MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 | |
100 | MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 | |
101 | MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 | |
102 | MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 | |
103 | MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 | |
104 | MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 | |
105 | >; | |
106 | }; | |
107 | }; | |
108 | }; |