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9daaf31a SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
36dffd8f | 13 | #include "skeleton.dtsi" |
e1641531 | 14 | #include "imx51-pinfunc.h" |
ff65d4ca | 15 | #include <dt-bindings/clock/imx5-clock.h> |
bdb3eec7 | 16 | #include <dt-bindings/gpio/gpio.h> |
72d86d26 AS |
17 | #include <dt-bindings/input/input.h> |
18 | #include <dt-bindings/interrupt-controller/irq.h> | |
9daaf31a SG |
19 | |
20 | / { | |
21 | aliases { | |
22970070 | 22 | ethernet0 = &fec; |
5230f8fe SG |
23 | gpio0 = &gpio1; |
24 | gpio1 = &gpio2; | |
25 | gpio2 = &gpio3; | |
26 | gpio3 = &gpio4; | |
e3b73c68 SH |
27 | i2c0 = &i2c1; |
28 | i2c1 = &i2c2; | |
f742c22c SH |
29 | mmc0 = &esdhc1; |
30 | mmc1 = &esdhc2; | |
31 | mmc2 = &esdhc3; | |
32 | mmc3 = &esdhc4; | |
e3b73c68 SH |
33 | serial0 = &uart1; |
34 | serial1 = &uart2; | |
35 | serial2 = &uart3; | |
36 | spi0 = &ecspi1; | |
37 | spi1 = &ecspi2; | |
38 | spi2 = &cspi; | |
9daaf31a SG |
39 | }; |
40 | ||
41 | tzic: tz-interrupt-controller@e0000000 { | |
42 | compatible = "fsl,imx51-tzic", "fsl,tzic"; | |
43 | interrupt-controller; | |
44 | #interrupt-cells = <1>; | |
45 | reg = <0xe0000000 0x4000>; | |
46 | }; | |
47 | ||
48 | clocks { | |
49 | #address-cells = <1>; | |
50 | #size-cells = <0>; | |
51 | ||
52 | ckil { | |
53 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
4b2b4043 | 54 | #clock-cells = <0>; |
9daaf31a SG |
55 | clock-frequency = <32768>; |
56 | }; | |
57 | ||
58 | ckih1 { | |
59 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
4b2b4043 | 60 | #clock-cells = <0>; |
677e28b1 | 61 | clock-frequency = <0>; |
9daaf31a SG |
62 | }; |
63 | ||
64 | ckih2 { | |
65 | compatible = "fsl,imx-ckih2", "fixed-clock"; | |
4b2b4043 | 66 | #clock-cells = <0>; |
9daaf31a SG |
67 | clock-frequency = <0>; |
68 | }; | |
69 | ||
70 | osc { | |
71 | compatible = "fsl,imx-osc", "fixed-clock"; | |
4b2b4043 | 72 | #clock-cells = <0>; |
9daaf31a SG |
73 | clock-frequency = <24000000>; |
74 | }; | |
75 | }; | |
76 | ||
6f9d62d4 MP |
77 | cpus { |
78 | #address-cells = <1>; | |
79 | #size-cells = <0>; | |
6acde887 | 80 | cpu: cpu@0 { |
6f9d62d4 MP |
81 | device_type = "cpu"; |
82 | compatible = "arm,cortex-a8"; | |
83 | reg = <0>; | |
6acde887 | 84 | clock-latency = <62500>; |
ff65d4ca | 85 | clocks = <&clks IMX5_CLK_CPU_PODF>; |
6f9d62d4 MP |
86 | clock-names = "cpu"; |
87 | operating-points = < | |
6acde887 AS |
88 | 166000 1000000 |
89 | 600000 1050000 | |
90 | 800000 1100000 | |
6f9d62d4 | 91 | >; |
6acde887 | 92 | voltage-tolerance = <5>; |
6f9d62d4 MP |
93 | }; |
94 | }; | |
95 | ||
4e942303 AS |
96 | usbphy { |
97 | #address-cells = <1>; | |
98 | #size-cells = <0>; | |
99 | compatible = "simple-bus"; | |
100 | ||
101 | usbphy0: usbphy@0 { | |
102 | compatible = "usb-nop-xceiv"; | |
103 | reg = <0>; | |
104 | clocks = <&clks IMX5_CLK_USB_PHY_GATE>; | |
105 | clock-names = "main_clk"; | |
6f9d62d4 MP |
106 | }; |
107 | }; | |
108 | ||
de10e04e PZ |
109 | display-subsystem { |
110 | compatible = "fsl,imx-display-subsystem"; | |
111 | ports = <&ipu_di0>, <&ipu_di1>; | |
112 | }; | |
113 | ||
9daaf31a SG |
114 | soc { |
115 | #address-cells = <1>; | |
116 | #size-cells = <1>; | |
117 | compatible = "simple-bus"; | |
118 | interrupt-parent = <&tzic>; | |
119 | ranges; | |
120 | ||
da38ea33 AS |
121 | iram: iram@1ffe0000 { |
122 | compatible = "mmio-sram"; | |
123 | reg = <0x1ffe0000 0x20000>; | |
124 | }; | |
125 | ||
b5af6b10 | 126 | ipu: ipu@40000000 { |
de10e04e PZ |
127 | #address-cells = <1>; |
128 | #size-cells = <0>; | |
b5af6b10 SH |
129 | compatible = "fsl,imx51-ipu"; |
130 | reg = <0x40000000 0x20000000>; | |
131 | interrupts = <11 10>; | |
ff65d4ca LS |
132 | clocks = <&clks IMX5_CLK_IPU_GATE>, |
133 | <&clks IMX5_CLK_IPU_DI0_GATE>, | |
134 | <&clks IMX5_CLK_IPU_DI1_GATE>; | |
4438a6a1 | 135 | clock-names = "bus", "di0", "di1"; |
8d84c374 | 136 | resets = <&src 2>; |
de10e04e PZ |
137 | |
138 | ipu_di0: port@2 { | |
139 | reg = <2>; | |
140 | ||
141 | ipu_di0_disp0: endpoint { | |
142 | }; | |
143 | }; | |
144 | ||
145 | ipu_di1: port@3 { | |
146 | reg = <3>; | |
147 | ||
148 | ipu_di1_disp1: endpoint { | |
149 | }; | |
150 | }; | |
b5af6b10 SH |
151 | }; |
152 | ||
9daaf31a SG |
153 | aips@70000000 { /* AIPS1 */ |
154 | compatible = "fsl,aips-bus", "simple-bus"; | |
155 | #address-cells = <1>; | |
156 | #size-cells = <1>; | |
157 | reg = <0x70000000 0x10000000>; | |
158 | ranges; | |
159 | ||
160 | spba@70000000 { | |
161 | compatible = "fsl,spba-bus", "simple-bus"; | |
162 | #address-cells = <1>; | |
163 | #size-cells = <1>; | |
164 | reg = <0x70000000 0x40000>; | |
165 | ranges; | |
166 | ||
7b7d6727 | 167 | esdhc1: esdhc@70004000 { |
9daaf31a SG |
168 | compatible = "fsl,imx51-esdhc"; |
169 | reg = <0x70004000 0x4000>; | |
170 | interrupts = <1>; | |
ff65d4ca LS |
171 | clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, |
172 | <&clks IMX5_CLK_DUMMY>, | |
173 | <&clks IMX5_CLK_ESDHC1_PER_GATE>; | |
f40f38d1 | 174 | clock-names = "ipg", "ahb", "per"; |
9daaf31a SG |
175 | status = "disabled"; |
176 | }; | |
177 | ||
7b7d6727 | 178 | esdhc2: esdhc@70008000 { |
9daaf31a SG |
179 | compatible = "fsl,imx51-esdhc"; |
180 | reg = <0x70008000 0x4000>; | |
181 | interrupts = <2>; | |
ff65d4ca LS |
182 | clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, |
183 | <&clks IMX5_CLK_DUMMY>, | |
184 | <&clks IMX5_CLK_ESDHC2_PER_GATE>; | |
f40f38d1 | 185 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 186 | bus-width = <4>; |
9daaf31a SG |
187 | status = "disabled"; |
188 | }; | |
189 | ||
0c456cfa | 190 | uart3: serial@7000c000 { |
9daaf31a SG |
191 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
192 | reg = <0x7000c000 0x4000>; | |
193 | interrupts = <33>; | |
ff65d4ca LS |
194 | clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, |
195 | <&clks IMX5_CLK_UART3_PER_GATE>; | |
f40f38d1 | 196 | clock-names = "ipg", "per"; |
9daaf31a SG |
197 | status = "disabled"; |
198 | }; | |
199 | ||
7b7d6727 | 200 | ecspi1: ecspi@70010000 { |
9daaf31a SG |
201 | #address-cells = <1>; |
202 | #size-cells = <0>; | |
203 | compatible = "fsl,imx51-ecspi"; | |
204 | reg = <0x70010000 0x4000>; | |
205 | interrupts = <36>; | |
ff65d4ca LS |
206 | clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, |
207 | <&clks IMX5_CLK_ECSPI1_PER_GATE>; | |
f40f38d1 | 208 | clock-names = "ipg", "per"; |
9daaf31a SG |
209 | status = "disabled"; |
210 | }; | |
211 | ||
a15d9f89 SG |
212 | ssi2: ssi@70014000 { |
213 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; | |
214 | reg = <0x70014000 0x4000>; | |
215 | interrupts = <30>; | |
ff65d4ca | 216 | clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; |
5da826ab SG |
217 | dmas = <&sdma 24 1 0>, |
218 | <&sdma 25 1 0>; | |
219 | dma-names = "rx", "tx"; | |
a15d9f89 SG |
220 | fsl,fifo-depth = <15>; |
221 | fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ | |
222 | status = "disabled"; | |
223 | }; | |
224 | ||
7b7d6727 | 225 | esdhc3: esdhc@70020000 { |
9daaf31a SG |
226 | compatible = "fsl,imx51-esdhc"; |
227 | reg = <0x70020000 0x4000>; | |
228 | interrupts = <3>; | |
ff65d4ca LS |
229 | clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, |
230 | <&clks IMX5_CLK_DUMMY>, | |
231 | <&clks IMX5_CLK_ESDHC3_PER_GATE>; | |
f40f38d1 | 232 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 233 | bus-width = <4>; |
9daaf31a SG |
234 | status = "disabled"; |
235 | }; | |
236 | ||
7b7d6727 | 237 | esdhc4: esdhc@70024000 { |
9daaf31a SG |
238 | compatible = "fsl,imx51-esdhc"; |
239 | reg = <0x70024000 0x4000>; | |
240 | interrupts = <4>; | |
ff65d4ca LS |
241 | clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, |
242 | <&clks IMX5_CLK_DUMMY>, | |
243 | <&clks IMX5_CLK_ESDHC4_PER_GATE>; | |
f40f38d1 | 244 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 245 | bus-width = <4>; |
9daaf31a SG |
246 | status = "disabled"; |
247 | }; | |
248 | }; | |
249 | ||
7b7d6727 | 250 | usbotg: usb@73f80000 { |
212d0b83 MG |
251 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
252 | reg = <0x73f80000 0x0200>; | |
253 | interrupts = <18>; | |
ff65d4ca | 254 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
a5735021 | 255 | fsl,usbmisc = <&usbmisc 0>; |
a79025c4 | 256 | fsl,usbphy = <&usbphy0>; |
212d0b83 MG |
257 | status = "disabled"; |
258 | }; | |
259 | ||
7b7d6727 | 260 | usbh1: usb@73f80200 { |
212d0b83 MG |
261 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
262 | reg = <0x73f80200 0x0200>; | |
263 | interrupts = <14>; | |
ff65d4ca | 264 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
a5735021 | 265 | fsl,usbmisc = <&usbmisc 1>; |
212d0b83 MG |
266 | status = "disabled"; |
267 | }; | |
268 | ||
7b7d6727 | 269 | usbh2: usb@73f80400 { |
212d0b83 MG |
270 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
271 | reg = <0x73f80400 0x0200>; | |
272 | interrupts = <16>; | |
ff65d4ca | 273 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
a5735021 | 274 | fsl,usbmisc = <&usbmisc 2>; |
212d0b83 MG |
275 | status = "disabled"; |
276 | }; | |
277 | ||
7b7d6727 | 278 | usbh3: usb@73f80600 { |
212d0b83 MG |
279 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
280 | reg = <0x73f80600 0x0200>; | |
281 | interrupts = <17>; | |
ff65d4ca | 282 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
a5735021 | 283 | fsl,usbmisc = <&usbmisc 3>; |
212d0b83 MG |
284 | status = "disabled"; |
285 | }; | |
286 | ||
a5735021 MG |
287 | usbmisc: usbmisc@73f80800 { |
288 | #index-cells = <1>; | |
289 | compatible = "fsl,imx51-usbmisc"; | |
290 | reg = <0x73f80800 0x200>; | |
ff65d4ca | 291 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
a5735021 MG |
292 | }; |
293 | ||
4d191868 | 294 | gpio1: gpio@73f84000 { |
aeb27748 | 295 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
9daaf31a SG |
296 | reg = <0x73f84000 0x4000>; |
297 | interrupts = <50 51>; | |
298 | gpio-controller; | |
299 | #gpio-cells = <2>; | |
300 | interrupt-controller; | |
88cde8b7 | 301 | #interrupt-cells = <2>; |
9daaf31a SG |
302 | }; |
303 | ||
4d191868 | 304 | gpio2: gpio@73f88000 { |
aeb27748 | 305 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
9daaf31a SG |
306 | reg = <0x73f88000 0x4000>; |
307 | interrupts = <52 53>; | |
308 | gpio-controller; | |
309 | #gpio-cells = <2>; | |
310 | interrupt-controller; | |
88cde8b7 | 311 | #interrupt-cells = <2>; |
9daaf31a SG |
312 | }; |
313 | ||
4d191868 | 314 | gpio3: gpio@73f8c000 { |
aeb27748 | 315 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
9daaf31a SG |
316 | reg = <0x73f8c000 0x4000>; |
317 | interrupts = <54 55>; | |
318 | gpio-controller; | |
319 | #gpio-cells = <2>; | |
320 | interrupt-controller; | |
88cde8b7 | 321 | #interrupt-cells = <2>; |
9daaf31a SG |
322 | }; |
323 | ||
4d191868 | 324 | gpio4: gpio@73f90000 { |
aeb27748 | 325 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
9daaf31a SG |
326 | reg = <0x73f90000 0x4000>; |
327 | interrupts = <56 57>; | |
328 | gpio-controller; | |
329 | #gpio-cells = <2>; | |
330 | interrupt-controller; | |
88cde8b7 | 331 | #interrupt-cells = <2>; |
9daaf31a SG |
332 | }; |
333 | ||
6012555c LY |
334 | kpp: kpp@73f94000 { |
335 | compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; | |
336 | reg = <0x73f94000 0x4000>; | |
337 | interrupts = <60>; | |
ff65d4ca | 338 | clocks = <&clks IMX5_CLK_DUMMY>; |
6012555c LY |
339 | status = "disabled"; |
340 | }; | |
341 | ||
7b7d6727 | 342 | wdog1: wdog@73f98000 { |
9daaf31a SG |
343 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; |
344 | reg = <0x73f98000 0x4000>; | |
345 | interrupts = <58>; | |
ff65d4ca | 346 | clocks = <&clks IMX5_CLK_DUMMY>; |
9daaf31a SG |
347 | }; |
348 | ||
7b7d6727 | 349 | wdog2: wdog@73f9c000 { |
9daaf31a SG |
350 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; |
351 | reg = <0x73f9c000 0x4000>; | |
352 | interrupts = <59>; | |
ff65d4ca | 353 | clocks = <&clks IMX5_CLK_DUMMY>; |
9daaf31a SG |
354 | status = "disabled"; |
355 | }; | |
356 | ||
ed73c63a SH |
357 | gpt: timer@73fa0000 { |
358 | compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; | |
359 | reg = <0x73fa0000 0x4000>; | |
360 | interrupts = <39>; | |
ff65d4ca LS |
361 | clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, |
362 | <&clks IMX5_CLK_GPT_HF_GATE>; | |
ed73c63a SH |
363 | clock-names = "ipg", "per"; |
364 | }; | |
365 | ||
7b7d6727 | 366 | iomuxc: iomuxc@73fa8000 { |
b72cf105 SG |
367 | compatible = "fsl,imx51-iomuxc"; |
368 | reg = <0x73fa8000 0x4000>; | |
b72cf105 SG |
369 | }; |
370 | ||
82a618da SH |
371 | pwm1: pwm@73fb4000 { |
372 | #pwm-cells = <2>; | |
373 | compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; | |
374 | reg = <0x73fb4000 0x4000>; | |
ff65d4ca LS |
375 | clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, |
376 | <&clks IMX5_CLK_PWM1_HF_GATE>; | |
82a618da SH |
377 | clock-names = "ipg", "per"; |
378 | interrupts = <61>; | |
379 | }; | |
380 | ||
381 | pwm2: pwm@73fb8000 { | |
382 | #pwm-cells = <2>; | |
383 | compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; | |
384 | reg = <0x73fb8000 0x4000>; | |
ff65d4ca LS |
385 | clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, |
386 | <&clks IMX5_CLK_PWM2_HF_GATE>; | |
82a618da SH |
387 | clock-names = "ipg", "per"; |
388 | interrupts = <94>; | |
389 | }; | |
390 | ||
0c456cfa | 391 | uart1: serial@73fbc000 { |
9daaf31a SG |
392 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
393 | reg = <0x73fbc000 0x4000>; | |
394 | interrupts = <31>; | |
ff65d4ca LS |
395 | clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, |
396 | <&clks IMX5_CLK_UART1_PER_GATE>; | |
f40f38d1 | 397 | clock-names = "ipg", "per"; |
9daaf31a SG |
398 | status = "disabled"; |
399 | }; | |
400 | ||
0c456cfa | 401 | uart2: serial@73fc0000 { |
9daaf31a SG |
402 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
403 | reg = <0x73fc0000 0x4000>; | |
404 | interrupts = <32>; | |
ff65d4ca LS |
405 | clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, |
406 | <&clks IMX5_CLK_UART2_PER_GATE>; | |
f40f38d1 | 407 | clock-names = "ipg", "per"; |
9daaf31a SG |
408 | status = "disabled"; |
409 | }; | |
f40f38d1 | 410 | |
8d84c374 PZ |
411 | src: src@73fd0000 { |
412 | compatible = "fsl,imx51-src"; | |
413 | reg = <0x73fd0000 0x4000>; | |
414 | #reset-cells = <1>; | |
415 | }; | |
416 | ||
f40f38d1 FE |
417 | clks: ccm@73fd4000{ |
418 | compatible = "fsl,imx51-ccm"; | |
419 | reg = <0x73fd4000 0x4000>; | |
420 | interrupts = <0 71 0x04 0 72 0x04>; | |
421 | #clock-cells = <1>; | |
422 | }; | |
9daaf31a SG |
423 | }; |
424 | ||
425 | aips@80000000 { /* AIPS2 */ | |
426 | compatible = "fsl,aips-bus", "simple-bus"; | |
427 | #address-cells = <1>; | |
428 | #size-cells = <1>; | |
429 | reg = <0x80000000 0x10000000>; | |
430 | ranges; | |
431 | ||
6510ea25 SH |
432 | iim: iim@83f98000 { |
433 | compatible = "fsl,imx51-iim", "fsl,imx27-iim"; | |
434 | reg = <0x83f98000 0x4000>; | |
435 | interrupts = <69>; | |
ff65d4ca | 436 | clocks = <&clks IMX5_CLK_IIM_GATE>; |
6510ea25 SH |
437 | }; |
438 | ||
ad15f08c AS |
439 | owire: owire@83fa4000 { |
440 | compatible = "fsl,imx51-owire", "fsl,imx21-owire"; | |
441 | reg = <0x83fa4000 0x4000>; | |
442 | interrupts = <88>; | |
ff65d4ca | 443 | clocks = <&clks IMX5_CLK_OWIRE_GATE>; |
ad15f08c AS |
444 | status = "disabled"; |
445 | }; | |
446 | ||
7b7d6727 | 447 | ecspi2: ecspi@83fac000 { |
9daaf31a SG |
448 | #address-cells = <1>; |
449 | #size-cells = <0>; | |
450 | compatible = "fsl,imx51-ecspi"; | |
451 | reg = <0x83fac000 0x4000>; | |
452 | interrupts = <37>; | |
ff65d4ca LS |
453 | clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, |
454 | <&clks IMX5_CLK_ECSPI2_PER_GATE>; | |
f40f38d1 | 455 | clock-names = "ipg", "per"; |
9daaf31a SG |
456 | status = "disabled"; |
457 | }; | |
458 | ||
7b7d6727 | 459 | sdma: sdma@83fb0000 { |
9daaf31a SG |
460 | compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; |
461 | reg = <0x83fb0000 0x4000>; | |
462 | interrupts = <6>; | |
ff65d4ca LS |
463 | clocks = <&clks IMX5_CLK_SDMA_GATE>, |
464 | <&clks IMX5_CLK_SDMA_GATE>; | |
f40f38d1 | 465 | clock-names = "ipg", "ahb"; |
fb72bb21 | 466 | #dma-cells = <3>; |
7e4f0365 | 467 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; |
9daaf31a SG |
468 | }; |
469 | ||
7b7d6727 | 470 | cspi: cspi@83fc0000 { |
9daaf31a SG |
471 | #address-cells = <1>; |
472 | #size-cells = <0>; | |
473 | compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; | |
474 | reg = <0x83fc0000 0x4000>; | |
475 | interrupts = <38>; | |
ff65d4ca LS |
476 | clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, |
477 | <&clks IMX5_CLK_CSPI_IPG_GATE>; | |
f40f38d1 | 478 | clock-names = "ipg", "per"; |
9daaf31a SG |
479 | status = "disabled"; |
480 | }; | |
481 | ||
7b7d6727 | 482 | i2c2: i2c@83fc4000 { |
9daaf31a SG |
483 | #address-cells = <1>; |
484 | #size-cells = <0>; | |
5bdfba29 | 485 | compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; |
9daaf31a SG |
486 | reg = <0x83fc4000 0x4000>; |
487 | interrupts = <63>; | |
ff65d4ca | 488 | clocks = <&clks IMX5_CLK_I2C2_GATE>; |
9daaf31a SG |
489 | status = "disabled"; |
490 | }; | |
491 | ||
7b7d6727 | 492 | i2c1: i2c@83fc8000 { |
9daaf31a SG |
493 | #address-cells = <1>; |
494 | #size-cells = <0>; | |
5bdfba29 | 495 | compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; |
9daaf31a SG |
496 | reg = <0x83fc8000 0x4000>; |
497 | interrupts = <62>; | |
ff65d4ca | 498 | clocks = <&clks IMX5_CLK_I2C1_GATE>; |
9daaf31a SG |
499 | status = "disabled"; |
500 | }; | |
501 | ||
a15d9f89 SG |
502 | ssi1: ssi@83fcc000 { |
503 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; | |
504 | reg = <0x83fcc000 0x4000>; | |
505 | interrupts = <29>; | |
ff65d4ca | 506 | clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; |
5da826ab SG |
507 | dmas = <&sdma 28 0 0>, |
508 | <&sdma 29 0 0>; | |
509 | dma-names = "rx", "tx"; | |
a15d9f89 SG |
510 | fsl,fifo-depth = <15>; |
511 | fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ | |
512 | status = "disabled"; | |
513 | }; | |
514 | ||
7b7d6727 | 515 | audmux: audmux@83fd0000 { |
a15d9f89 SG |
516 | compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; |
517 | reg = <0x83fd0000 0x4000>; | |
ff65d4ca | 518 | clocks = <&clks IMX5_CLK_DUMMY>; |
e030df9d | 519 | clock-names = "audmux"; |
a15d9f89 SG |
520 | status = "disabled"; |
521 | }; | |
522 | ||
edd05286 AS |
523 | weim: weim@83fda000 { |
524 | #address-cells = <2>; | |
525 | #size-cells = <1>; | |
526 | compatible = "fsl,imx51-weim"; | |
527 | reg = <0x83fda000 0x1000>; | |
ff65d4ca | 528 | clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>; |
edd05286 AS |
529 | ranges = < |
530 | 0 0 0xb0000000 0x08000000 | |
531 | 1 0 0xb8000000 0x08000000 | |
532 | 2 0 0xc0000000 0x08000000 | |
533 | 3 0 0xc8000000 0x04000000 | |
534 | 4 0 0xcc000000 0x02000000 | |
535 | 5 0 0xce000000 0x02000000 | |
536 | >; | |
537 | status = "disabled"; | |
538 | }; | |
539 | ||
7b7d6727 | 540 | nfc: nand@83fdb000 { |
f0e3f89e AS |
541 | #address-cells = <1>; |
542 | #size-cells = <1>; | |
75453a08 SH |
543 | compatible = "fsl,imx51-nand"; |
544 | reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; | |
545 | interrupts = <8>; | |
ff65d4ca | 546 | clocks = <&clks IMX5_CLK_NFC_GATE>; |
75453a08 SH |
547 | status = "disabled"; |
548 | }; | |
549 | ||
718a3500 SH |
550 | pata: pata@83fe0000 { |
551 | compatible = "fsl,imx51-pata", "fsl,imx27-pata"; | |
552 | reg = <0x83fe0000 0x4000>; | |
553 | interrupts = <70>; | |
ff65d4ca | 554 | clocks = <&clks IMX5_CLK_PATA_GATE>; |
718a3500 SH |
555 | status = "disabled"; |
556 | }; | |
557 | ||
a15d9f89 SG |
558 | ssi3: ssi@83fe8000 { |
559 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; | |
560 | reg = <0x83fe8000 0x4000>; | |
561 | interrupts = <96>; | |
ff65d4ca | 562 | clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; |
5da826ab SG |
563 | dmas = <&sdma 46 0 0>, |
564 | <&sdma 47 0 0>; | |
565 | dma-names = "rx", "tx"; | |
a15d9f89 SG |
566 | fsl,fifo-depth = <15>; |
567 | fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ | |
568 | status = "disabled"; | |
569 | }; | |
570 | ||
7b7d6727 | 571 | fec: ethernet@83fec000 { |
9daaf31a SG |
572 | compatible = "fsl,imx51-fec", "fsl,imx27-fec"; |
573 | reg = <0x83fec000 0x4000>; | |
574 | interrupts = <87>; | |
ff65d4ca LS |
575 | clocks = <&clks IMX5_CLK_FEC_GATE>, |
576 | <&clks IMX5_CLK_FEC_GATE>, | |
577 | <&clks IMX5_CLK_FEC_GATE>; | |
f40f38d1 | 578 | clock-names = "ipg", "ahb", "ptp"; |
9daaf31a SG |
579 | status = "disabled"; |
580 | }; | |
581 | }; | |
582 | }; | |
583 | }; |