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Commit | Line | Data |
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9daaf31a SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
36dffd8f | 13 | #include "skeleton.dtsi" |
e1641531 | 14 | #include "imx51-pinfunc.h" |
9daaf31a SG |
15 | |
16 | / { | |
17 | aliases { | |
5230f8fe SG |
18 | gpio0 = &gpio1; |
19 | gpio1 = &gpio2; | |
20 | gpio2 = &gpio3; | |
21 | gpio3 = &gpio4; | |
e3b73c68 SH |
22 | i2c0 = &i2c1; |
23 | i2c1 = &i2c2; | |
24 | serial0 = &uart1; | |
25 | serial1 = &uart2; | |
26 | serial2 = &uart3; | |
27 | spi0 = &ecspi1; | |
28 | spi1 = &ecspi2; | |
29 | spi2 = &cspi; | |
9daaf31a SG |
30 | }; |
31 | ||
32 | tzic: tz-interrupt-controller@e0000000 { | |
33 | compatible = "fsl,imx51-tzic", "fsl,tzic"; | |
34 | interrupt-controller; | |
35 | #interrupt-cells = <1>; | |
36 | reg = <0xe0000000 0x4000>; | |
37 | }; | |
38 | ||
39 | clocks { | |
40 | #address-cells = <1>; | |
41 | #size-cells = <0>; | |
42 | ||
43 | ckil { | |
44 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
45 | clock-frequency = <32768>; | |
46 | }; | |
47 | ||
48 | ckih1 { | |
49 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
677e28b1 | 50 | clock-frequency = <0>; |
9daaf31a SG |
51 | }; |
52 | ||
53 | ckih2 { | |
54 | compatible = "fsl,imx-ckih2", "fixed-clock"; | |
55 | clock-frequency = <0>; | |
56 | }; | |
57 | ||
58 | osc { | |
59 | compatible = "fsl,imx-osc", "fixed-clock"; | |
60 | clock-frequency = <24000000>; | |
61 | }; | |
62 | }; | |
63 | ||
6f9d62d4 MP |
64 | cpus { |
65 | #address-cells = <1>; | |
66 | #size-cells = <0>; | |
67 | cpu@0 { | |
68 | device_type = "cpu"; | |
69 | compatible = "arm,cortex-a8"; | |
70 | reg = <0>; | |
71 | clock-latency = <61036>; /* two CLK32 periods */ | |
72 | clocks = <&clks 24>; | |
73 | clock-names = "cpu"; | |
74 | operating-points = < | |
75 | /* kHz uV (No regulator support) */ | |
76 | 160000 0 | |
77 | 800000 0 | |
78 | >; | |
79 | }; | |
80 | }; | |
81 | ||
9daaf31a SG |
82 | soc { |
83 | #address-cells = <1>; | |
84 | #size-cells = <1>; | |
85 | compatible = "simple-bus"; | |
86 | interrupt-parent = <&tzic>; | |
87 | ranges; | |
88 | ||
b5af6b10 SH |
89 | ipu: ipu@40000000 { |
90 | #crtc-cells = <1>; | |
91 | compatible = "fsl,imx51-ipu"; | |
92 | reg = <0x40000000 0x20000000>; | |
93 | interrupts = <11 10>; | |
4438a6a1 PZ |
94 | clocks = <&clks 59>, <&clks 110>, <&clks 61>; |
95 | clock-names = "bus", "di0", "di1"; | |
8d84c374 | 96 | resets = <&src 2>; |
b5af6b10 SH |
97 | }; |
98 | ||
9daaf31a SG |
99 | aips@70000000 { /* AIPS1 */ |
100 | compatible = "fsl,aips-bus", "simple-bus"; | |
101 | #address-cells = <1>; | |
102 | #size-cells = <1>; | |
103 | reg = <0x70000000 0x10000000>; | |
104 | ranges; | |
105 | ||
106 | spba@70000000 { | |
107 | compatible = "fsl,spba-bus", "simple-bus"; | |
108 | #address-cells = <1>; | |
109 | #size-cells = <1>; | |
110 | reg = <0x70000000 0x40000>; | |
111 | ranges; | |
112 | ||
7b7d6727 | 113 | esdhc1: esdhc@70004000 { |
9daaf31a SG |
114 | compatible = "fsl,imx51-esdhc"; |
115 | reg = <0x70004000 0x4000>; | |
116 | interrupts = <1>; | |
f40f38d1 FE |
117 | clocks = <&clks 44>, <&clks 0>, <&clks 71>; |
118 | clock-names = "ipg", "ahb", "per"; | |
9daaf31a SG |
119 | status = "disabled"; |
120 | }; | |
121 | ||
7b7d6727 | 122 | esdhc2: esdhc@70008000 { |
9daaf31a SG |
123 | compatible = "fsl,imx51-esdhc"; |
124 | reg = <0x70008000 0x4000>; | |
125 | interrupts = <2>; | |
f40f38d1 FE |
126 | clocks = <&clks 45>, <&clks 0>, <&clks 72>; |
127 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 128 | bus-width = <4>; |
9daaf31a SG |
129 | status = "disabled"; |
130 | }; | |
131 | ||
0c456cfa | 132 | uart3: serial@7000c000 { |
9daaf31a SG |
133 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
134 | reg = <0x7000c000 0x4000>; | |
135 | interrupts = <33>; | |
f40f38d1 FE |
136 | clocks = <&clks 32>, <&clks 33>; |
137 | clock-names = "ipg", "per"; | |
9daaf31a SG |
138 | status = "disabled"; |
139 | }; | |
140 | ||
7b7d6727 | 141 | ecspi1: ecspi@70010000 { |
9daaf31a SG |
142 | #address-cells = <1>; |
143 | #size-cells = <0>; | |
144 | compatible = "fsl,imx51-ecspi"; | |
145 | reg = <0x70010000 0x4000>; | |
146 | interrupts = <36>; | |
f40f38d1 FE |
147 | clocks = <&clks 51>, <&clks 52>; |
148 | clock-names = "ipg", "per"; | |
9daaf31a SG |
149 | status = "disabled"; |
150 | }; | |
151 | ||
a15d9f89 SG |
152 | ssi2: ssi@70014000 { |
153 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; | |
154 | reg = <0x70014000 0x4000>; | |
155 | interrupts = <30>; | |
f40f38d1 | 156 | clocks = <&clks 49>; |
5da826ab SG |
157 | dmas = <&sdma 24 1 0>, |
158 | <&sdma 25 1 0>; | |
159 | dma-names = "rx", "tx"; | |
a15d9f89 SG |
160 | fsl,fifo-depth = <15>; |
161 | fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ | |
162 | status = "disabled"; | |
163 | }; | |
164 | ||
7b7d6727 | 165 | esdhc3: esdhc@70020000 { |
9daaf31a SG |
166 | compatible = "fsl,imx51-esdhc"; |
167 | reg = <0x70020000 0x4000>; | |
168 | interrupts = <3>; | |
f40f38d1 FE |
169 | clocks = <&clks 46>, <&clks 0>, <&clks 73>; |
170 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 171 | bus-width = <4>; |
9daaf31a SG |
172 | status = "disabled"; |
173 | }; | |
174 | ||
7b7d6727 | 175 | esdhc4: esdhc@70024000 { |
9daaf31a SG |
176 | compatible = "fsl,imx51-esdhc"; |
177 | reg = <0x70024000 0x4000>; | |
178 | interrupts = <4>; | |
f40f38d1 FE |
179 | clocks = <&clks 47>, <&clks 0>, <&clks 74>; |
180 | clock-names = "ipg", "ahb", "per"; | |
c104b6a2 | 181 | bus-width = <4>; |
9daaf31a SG |
182 | status = "disabled"; |
183 | }; | |
184 | }; | |
185 | ||
a79025c4 MG |
186 | usbphy0: usbphy@0 { |
187 | compatible = "usb-nop-xceiv"; | |
188 | clocks = <&clks 124>; | |
189 | clock-names = "main_clk"; | |
190 | status = "okay"; | |
191 | }; | |
192 | ||
7b7d6727 | 193 | usbotg: usb@73f80000 { |
212d0b83 MG |
194 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
195 | reg = <0x73f80000 0x0200>; | |
196 | interrupts = <18>; | |
8e388908 | 197 | clocks = <&clks 108>; |
a5735021 | 198 | fsl,usbmisc = <&usbmisc 0>; |
a79025c4 | 199 | fsl,usbphy = <&usbphy0>; |
212d0b83 MG |
200 | status = "disabled"; |
201 | }; | |
202 | ||
7b7d6727 | 203 | usbh1: usb@73f80200 { |
212d0b83 MG |
204 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
205 | reg = <0x73f80200 0x0200>; | |
206 | interrupts = <14>; | |
8e388908 | 207 | clocks = <&clks 108>; |
a5735021 | 208 | fsl,usbmisc = <&usbmisc 1>; |
212d0b83 MG |
209 | status = "disabled"; |
210 | }; | |
211 | ||
7b7d6727 | 212 | usbh2: usb@73f80400 { |
212d0b83 MG |
213 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
214 | reg = <0x73f80400 0x0200>; | |
215 | interrupts = <16>; | |
8e388908 | 216 | clocks = <&clks 108>; |
a5735021 | 217 | fsl,usbmisc = <&usbmisc 2>; |
212d0b83 MG |
218 | status = "disabled"; |
219 | }; | |
220 | ||
7b7d6727 | 221 | usbh3: usb@73f80600 { |
212d0b83 MG |
222 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
223 | reg = <0x73f80600 0x0200>; | |
224 | interrupts = <17>; | |
8e388908 | 225 | clocks = <&clks 108>; |
a5735021 | 226 | fsl,usbmisc = <&usbmisc 3>; |
212d0b83 MG |
227 | status = "disabled"; |
228 | }; | |
229 | ||
a5735021 MG |
230 | usbmisc: usbmisc@73f80800 { |
231 | #index-cells = <1>; | |
232 | compatible = "fsl,imx51-usbmisc"; | |
233 | reg = <0x73f80800 0x200>; | |
8e388908 | 234 | clocks = <&clks 108>; |
a5735021 MG |
235 | }; |
236 | ||
4d191868 | 237 | gpio1: gpio@73f84000 { |
aeb27748 | 238 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
9daaf31a SG |
239 | reg = <0x73f84000 0x4000>; |
240 | interrupts = <50 51>; | |
241 | gpio-controller; | |
242 | #gpio-cells = <2>; | |
243 | interrupt-controller; | |
88cde8b7 | 244 | #interrupt-cells = <2>; |
9daaf31a SG |
245 | }; |
246 | ||
4d191868 | 247 | gpio2: gpio@73f88000 { |
aeb27748 | 248 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
9daaf31a SG |
249 | reg = <0x73f88000 0x4000>; |
250 | interrupts = <52 53>; | |
251 | gpio-controller; | |
252 | #gpio-cells = <2>; | |
253 | interrupt-controller; | |
88cde8b7 | 254 | #interrupt-cells = <2>; |
9daaf31a SG |
255 | }; |
256 | ||
4d191868 | 257 | gpio3: gpio@73f8c000 { |
aeb27748 | 258 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
9daaf31a SG |
259 | reg = <0x73f8c000 0x4000>; |
260 | interrupts = <54 55>; | |
261 | gpio-controller; | |
262 | #gpio-cells = <2>; | |
263 | interrupt-controller; | |
88cde8b7 | 264 | #interrupt-cells = <2>; |
9daaf31a SG |
265 | }; |
266 | ||
4d191868 | 267 | gpio4: gpio@73f90000 { |
aeb27748 | 268 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
9daaf31a SG |
269 | reg = <0x73f90000 0x4000>; |
270 | interrupts = <56 57>; | |
271 | gpio-controller; | |
272 | #gpio-cells = <2>; | |
273 | interrupt-controller; | |
88cde8b7 | 274 | #interrupt-cells = <2>; |
9daaf31a SG |
275 | }; |
276 | ||
6012555c LY |
277 | kpp: kpp@73f94000 { |
278 | compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; | |
279 | reg = <0x73f94000 0x4000>; | |
280 | interrupts = <60>; | |
281 | clocks = <&clks 0>; | |
282 | status = "disabled"; | |
283 | }; | |
284 | ||
7b7d6727 | 285 | wdog1: wdog@73f98000 { |
9daaf31a SG |
286 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; |
287 | reg = <0x73f98000 0x4000>; | |
288 | interrupts = <58>; | |
f40f38d1 | 289 | clocks = <&clks 0>; |
9daaf31a SG |
290 | }; |
291 | ||
7b7d6727 | 292 | wdog2: wdog@73f9c000 { |
9daaf31a SG |
293 | compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; |
294 | reg = <0x73f9c000 0x4000>; | |
295 | interrupts = <59>; | |
f40f38d1 | 296 | clocks = <&clks 0>; |
9daaf31a SG |
297 | status = "disabled"; |
298 | }; | |
299 | ||
ed73c63a SH |
300 | gpt: timer@73fa0000 { |
301 | compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; | |
302 | reg = <0x73fa0000 0x4000>; | |
303 | interrupts = <39>; | |
304 | clocks = <&clks 36>, <&clks 41>; | |
305 | clock-names = "ipg", "per"; | |
306 | }; | |
307 | ||
7b7d6727 | 308 | iomuxc: iomuxc@73fa8000 { |
b72cf105 SG |
309 | compatible = "fsl,imx51-iomuxc"; |
310 | reg = <0x73fa8000 0x4000>; | |
311 | ||
312 | audmux { | |
313 | pinctrl_audmux_1: audmuxgrp-1 { | |
314 | fsl,pins = < | |
e1641531 SG |
315 | MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000 |
316 | MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000 | |
317 | MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000 | |
318 | MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000 | |
b72cf105 SG |
319 | >; |
320 | }; | |
321 | }; | |
322 | ||
323 | fec { | |
324 | pinctrl_fec_1: fecgrp-1 { | |
325 | fsl,pins = < | |
e1641531 SG |
326 | MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 |
327 | MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 | |
328 | MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 | |
329 | MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 | |
330 | MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 | |
331 | MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 | |
332 | MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 | |
333 | MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 | |
334 | MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 | |
335 | MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 | |
336 | MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 | |
337 | MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 | |
338 | MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 | |
339 | MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 | |
340 | MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 | |
341 | MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 | |
342 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 | |
b72cf105 SG |
343 | >; |
344 | }; | |
1982d5b6 LC |
345 | |
346 | pinctrl_fec_2: fecgrp-2 { | |
347 | fsl,pins = < | |
e1641531 SG |
348 | MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 |
349 | MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 | |
350 | MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 | |
351 | MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 | |
352 | MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 | |
353 | MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 | |
354 | MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 | |
355 | MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 | |
356 | MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 | |
357 | MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 | |
358 | MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 | |
359 | MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 | |
360 | MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 | |
361 | MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 | |
362 | MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 | |
363 | MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 | |
364 | MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 | |
365 | MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 | |
1982d5b6 LC |
366 | >; |
367 | }; | |
b72cf105 SG |
368 | }; |
369 | ||
370 | ecspi1 { | |
371 | pinctrl_ecspi1_1: ecspi1grp-1 { | |
372 | fsl,pins = < | |
e1641531 SG |
373 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 |
374 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 | |
375 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 | |
b72cf105 SG |
376 | >; |
377 | }; | |
378 | }; | |
379 | ||
a15ac4a6 GGM |
380 | ecspi2 { |
381 | pinctrl_ecspi2_1: ecspi2grp-1 { | |
382 | fsl,pins = < | |
383 | MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185 | |
384 | MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185 | |
385 | MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185 | |
386 | >; | |
387 | }; | |
388 | }; | |
389 | ||
b72cf105 SG |
390 | esdhc1 { |
391 | pinctrl_esdhc1_1: esdhc1grp-1 { | |
392 | fsl,pins = < | |
e1641531 SG |
393 | MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 |
394 | MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 | |
395 | MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 | |
396 | MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 | |
397 | MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 | |
398 | MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 | |
b72cf105 SG |
399 | >; |
400 | }; | |
401 | }; | |
402 | ||
403 | esdhc2 { | |
404 | pinctrl_esdhc2_1: esdhc2grp-1 { | |
405 | fsl,pins = < | |
e1641531 SG |
406 | MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5 |
407 | MX51_PAD_SD2_CLK__SD2_CLK 0x20d5 | |
408 | MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5 | |
409 | MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5 | |
410 | MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5 | |
411 | MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5 | |
b72cf105 SG |
412 | >; |
413 | }; | |
414 | }; | |
415 | ||
416 | i2c2 { | |
417 | pinctrl_i2c2_1: i2c2grp-1 { | |
418 | fsl,pins = < | |
e1641531 SG |
419 | MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed |
420 | MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed | |
b72cf105 SG |
421 | >; |
422 | }; | |
52c9aa94 GGM |
423 | |
424 | pinctrl_i2c2_2: i2c2grp-2 { | |
425 | fsl,pins = < | |
426 | MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed | |
427 | MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed | |
428 | >; | |
429 | }; | |
b72cf105 SG |
430 | }; |
431 | ||
b5af6b10 SH |
432 | ipu_disp1 { |
433 | pinctrl_ipu_disp1_1: ipudisp1grp-1 { | |
434 | fsl,pins = < | |
e1641531 SG |
435 | MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 |
436 | MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 | |
437 | MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 | |
438 | MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 | |
439 | MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 | |
440 | MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 | |
441 | MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 | |
442 | MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 | |
443 | MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 | |
444 | MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 | |
445 | MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 | |
446 | MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 | |
447 | MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 | |
448 | MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 | |
449 | MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 | |
450 | MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 | |
451 | MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 | |
452 | MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 | |
453 | MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 | |
454 | MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 | |
455 | MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 | |
456 | MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 | |
457 | MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 | |
458 | MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 | |
459 | MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */ | |
460 | MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */ | |
b5af6b10 SH |
461 | >; |
462 | }; | |
463 | }; | |
464 | ||
465 | ipu_disp2 { | |
466 | pinctrl_ipu_disp2_1: ipudisp2grp-1 { | |
467 | fsl,pins = < | |
e1641531 SG |
468 | MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5 |
469 | MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5 | |
470 | MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5 | |
471 | MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5 | |
472 | MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5 | |
473 | MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5 | |
474 | MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5 | |
475 | MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5 | |
476 | MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5 | |
477 | MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5 | |
478 | MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5 | |
479 | MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5 | |
480 | MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5 | |
481 | MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5 | |
482 | MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5 | |
483 | MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5 | |
484 | MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */ | |
485 | MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */ | |
486 | MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 | |
487 | MX51_PAD_DI_GP4__DI2_PIN15 0x5 | |
b5af6b10 SH |
488 | >; |
489 | }; | |
490 | }; | |
491 | ||
a9031820 SH |
492 | kpp { |
493 | pinctrl_kpp_1: kppgrp-1 { | |
494 | fsl,pins = < | |
495 | MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0 | |
496 | MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0 | |
497 | MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0 | |
498 | MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0 | |
499 | MX51_PAD_KEY_COL0__KEY_COL0 0xe8 | |
500 | MX51_PAD_KEY_COL1__KEY_COL1 0xe8 | |
501 | MX51_PAD_KEY_COL2__KEY_COL2 0xe8 | |
502 | MX51_PAD_KEY_COL3__KEY_COL3 0xe8 | |
503 | >; | |
504 | }; | |
505 | }; | |
506 | ||
718a3500 SH |
507 | pata { |
508 | pinctrl_pata_1: patagrp-1 { | |
509 | fsl,pins = < | |
510 | MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004 | |
511 | MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004 | |
512 | MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004 | |
513 | MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004 | |
514 | MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004 | |
515 | MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004 | |
516 | MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004 | |
517 | MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004 | |
518 | MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004 | |
519 | MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004 | |
520 | MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004 | |
521 | MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004 | |
522 | MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004 | |
523 | MX51_PAD_NANDF_D15__PATA_DATA15 0x2004 | |
524 | MX51_PAD_NANDF_D14__PATA_DATA14 0x2004 | |
525 | MX51_PAD_NANDF_D13__PATA_DATA13 0x2004 | |
526 | MX51_PAD_NANDF_D12__PATA_DATA12 0x2004 | |
527 | MX51_PAD_NANDF_D11__PATA_DATA11 0x2004 | |
528 | MX51_PAD_NANDF_D10__PATA_DATA10 0x2004 | |
529 | MX51_PAD_NANDF_D9__PATA_DATA9 0x2004 | |
530 | MX51_PAD_NANDF_D8__PATA_DATA8 0x2004 | |
531 | MX51_PAD_NANDF_D7__PATA_DATA7 0x2004 | |
532 | MX51_PAD_NANDF_D6__PATA_DATA6 0x2004 | |
533 | MX51_PAD_NANDF_D5__PATA_DATA5 0x2004 | |
534 | MX51_PAD_NANDF_D4__PATA_DATA4 0x2004 | |
535 | MX51_PAD_NANDF_D3__PATA_DATA3 0x2004 | |
536 | MX51_PAD_NANDF_D2__PATA_DATA2 0x2004 | |
537 | MX51_PAD_NANDF_D1__PATA_DATA1 0x2004 | |
538 | MX51_PAD_NANDF_D0__PATA_DATA0 0x2004 | |
539 | >; | |
540 | }; | |
541 | }; | |
542 | ||
b72cf105 SG |
543 | uart1 { |
544 | pinctrl_uart1_1: uart1grp-1 { | |
545 | fsl,pins = < | |
e1641531 SG |
546 | MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 |
547 | MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 | |
548 | MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 | |
549 | MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 | |
b72cf105 SG |
550 | >; |
551 | }; | |
552 | }; | |
553 | ||
554 | uart2 { | |
555 | pinctrl_uart2_1: uart2grp-1 { | |
556 | fsl,pins = < | |
e1641531 SG |
557 | MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 |
558 | MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 | |
b72cf105 SG |
559 | >; |
560 | }; | |
561 | }; | |
562 | ||
563 | uart3 { | |
564 | pinctrl_uart3_1: uart3grp-1 { | |
565 | fsl,pins = < | |
e1641531 SG |
566 | MX51_PAD_EIM_D25__UART3_RXD 0x1c5 |
567 | MX51_PAD_EIM_D26__UART3_TXD 0x1c5 | |
568 | MX51_PAD_EIM_D27__UART3_RTS 0x1c5 | |
569 | MX51_PAD_EIM_D24__UART3_CTS 0x1c5 | |
b72cf105 SG |
570 | >; |
571 | }; | |
1982d5b6 LC |
572 | |
573 | pinctrl_uart3_2: uart3grp-2 { | |
574 | fsl,pins = < | |
e1641531 SG |
575 | MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 |
576 | MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 | |
1982d5b6 LC |
577 | >; |
578 | }; | |
b72cf105 | 579 | }; |
aeaa951f SH |
580 | |
581 | usbh1 { | |
582 | pinctrl_usbh1_1: usbh1grp-1 { | |
583 | fsl,pins = < | |
584 | MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5 | |
585 | MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5 | |
586 | MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5 | |
587 | MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5 | |
588 | MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5 | |
589 | MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5 | |
590 | MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5 | |
591 | MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5 | |
592 | MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5 | |
593 | MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5 | |
594 | MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5 | |
595 | MX51_PAD_USBH1_STP__USBH1_STP 0x1e5 | |
596 | >; | |
597 | }; | |
598 | }; | |
599 | ||
600 | usbh2 { | |
601 | pinctrl_usbh2_1: usbh2grp-1 { | |
602 | fsl,pins = < | |
603 | MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5 | |
604 | MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5 | |
605 | MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5 | |
606 | MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5 | |
607 | MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5 | |
608 | MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5 | |
609 | MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5 | |
610 | MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5 | |
611 | MX51_PAD_EIM_A24__USBH2_CLK 0x1e5 | |
612 | MX51_PAD_EIM_A25__USBH2_DIR 0x1e5 | |
613 | MX51_PAD_EIM_A27__USBH2_NXT 0x1e5 | |
614 | MX51_PAD_EIM_A26__USBH2_STP 0x1e5 | |
615 | >; | |
616 | }; | |
617 | }; | |
b72cf105 SG |
618 | }; |
619 | ||
82a618da SH |
620 | pwm1: pwm@73fb4000 { |
621 | #pwm-cells = <2>; | |
622 | compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; | |
623 | reg = <0x73fb4000 0x4000>; | |
624 | clocks = <&clks 37>, <&clks 38>; | |
625 | clock-names = "ipg", "per"; | |
626 | interrupts = <61>; | |
627 | }; | |
628 | ||
629 | pwm2: pwm@73fb8000 { | |
630 | #pwm-cells = <2>; | |
631 | compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; | |
632 | reg = <0x73fb8000 0x4000>; | |
633 | clocks = <&clks 39>, <&clks 40>; | |
634 | clock-names = "ipg", "per"; | |
635 | interrupts = <94>; | |
636 | }; | |
637 | ||
0c456cfa | 638 | uart1: serial@73fbc000 { |
9daaf31a SG |
639 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
640 | reg = <0x73fbc000 0x4000>; | |
641 | interrupts = <31>; | |
f40f38d1 FE |
642 | clocks = <&clks 28>, <&clks 29>; |
643 | clock-names = "ipg", "per"; | |
9daaf31a SG |
644 | status = "disabled"; |
645 | }; | |
646 | ||
0c456cfa | 647 | uart2: serial@73fc0000 { |
9daaf31a SG |
648 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
649 | reg = <0x73fc0000 0x4000>; | |
650 | interrupts = <32>; | |
f40f38d1 FE |
651 | clocks = <&clks 30>, <&clks 31>; |
652 | clock-names = "ipg", "per"; | |
9daaf31a SG |
653 | status = "disabled"; |
654 | }; | |
f40f38d1 | 655 | |
8d84c374 PZ |
656 | src: src@73fd0000 { |
657 | compatible = "fsl,imx51-src"; | |
658 | reg = <0x73fd0000 0x4000>; | |
659 | #reset-cells = <1>; | |
660 | }; | |
661 | ||
f40f38d1 FE |
662 | clks: ccm@73fd4000{ |
663 | compatible = "fsl,imx51-ccm"; | |
664 | reg = <0x73fd4000 0x4000>; | |
665 | interrupts = <0 71 0x04 0 72 0x04>; | |
666 | #clock-cells = <1>; | |
667 | }; | |
9daaf31a SG |
668 | }; |
669 | ||
670 | aips@80000000 { /* AIPS2 */ | |
671 | compatible = "fsl,aips-bus", "simple-bus"; | |
672 | #address-cells = <1>; | |
673 | #size-cells = <1>; | |
674 | reg = <0x80000000 0x10000000>; | |
675 | ranges; | |
676 | ||
6510ea25 SH |
677 | iim: iim@83f98000 { |
678 | compatible = "fsl,imx51-iim", "fsl,imx27-iim"; | |
679 | reg = <0x83f98000 0x4000>; | |
680 | interrupts = <69>; | |
681 | clocks = <&clks 107>; | |
682 | }; | |
683 | ||
7b7d6727 | 684 | ecspi2: ecspi@83fac000 { |
9daaf31a SG |
685 | #address-cells = <1>; |
686 | #size-cells = <0>; | |
687 | compatible = "fsl,imx51-ecspi"; | |
688 | reg = <0x83fac000 0x4000>; | |
689 | interrupts = <37>; | |
f40f38d1 FE |
690 | clocks = <&clks 53>, <&clks 54>; |
691 | clock-names = "ipg", "per"; | |
9daaf31a SG |
692 | status = "disabled"; |
693 | }; | |
694 | ||
7b7d6727 | 695 | sdma: sdma@83fb0000 { |
9daaf31a SG |
696 | compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; |
697 | reg = <0x83fb0000 0x4000>; | |
698 | interrupts = <6>; | |
f40f38d1 FE |
699 | clocks = <&clks 56>, <&clks 56>; |
700 | clock-names = "ipg", "ahb"; | |
fb72bb21 | 701 | #dma-cells = <3>; |
7e4f0365 | 702 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; |
9daaf31a SG |
703 | }; |
704 | ||
7b7d6727 | 705 | cspi: cspi@83fc0000 { |
9daaf31a SG |
706 | #address-cells = <1>; |
707 | #size-cells = <0>; | |
708 | compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; | |
709 | reg = <0x83fc0000 0x4000>; | |
710 | interrupts = <38>; | |
37523dc5 | 711 | clocks = <&clks 55>, <&clks 55>; |
f40f38d1 | 712 | clock-names = "ipg", "per"; |
9daaf31a SG |
713 | status = "disabled"; |
714 | }; | |
715 | ||
7b7d6727 | 716 | i2c2: i2c@83fc4000 { |
9daaf31a SG |
717 | #address-cells = <1>; |
718 | #size-cells = <0>; | |
5bdfba29 | 719 | compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; |
9daaf31a SG |
720 | reg = <0x83fc4000 0x4000>; |
721 | interrupts = <63>; | |
f40f38d1 | 722 | clocks = <&clks 35>; |
9daaf31a SG |
723 | status = "disabled"; |
724 | }; | |
725 | ||
7b7d6727 | 726 | i2c1: i2c@83fc8000 { |
9daaf31a SG |
727 | #address-cells = <1>; |
728 | #size-cells = <0>; | |
5bdfba29 | 729 | compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; |
9daaf31a SG |
730 | reg = <0x83fc8000 0x4000>; |
731 | interrupts = <62>; | |
f40f38d1 | 732 | clocks = <&clks 34>; |
9daaf31a SG |
733 | status = "disabled"; |
734 | }; | |
735 | ||
a15d9f89 SG |
736 | ssi1: ssi@83fcc000 { |
737 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; | |
738 | reg = <0x83fcc000 0x4000>; | |
739 | interrupts = <29>; | |
f40f38d1 | 740 | clocks = <&clks 48>; |
5da826ab SG |
741 | dmas = <&sdma 28 0 0>, |
742 | <&sdma 29 0 0>; | |
743 | dma-names = "rx", "tx"; | |
a15d9f89 SG |
744 | fsl,fifo-depth = <15>; |
745 | fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ | |
746 | status = "disabled"; | |
747 | }; | |
748 | ||
7b7d6727 | 749 | audmux: audmux@83fd0000 { |
a15d9f89 SG |
750 | compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; |
751 | reg = <0x83fd0000 0x4000>; | |
752 | status = "disabled"; | |
753 | }; | |
754 | ||
edd05286 AS |
755 | weim: weim@83fda000 { |
756 | #address-cells = <2>; | |
757 | #size-cells = <1>; | |
758 | compatible = "fsl,imx51-weim"; | |
759 | reg = <0x83fda000 0x1000>; | |
760 | clocks = <&clks 57>; | |
761 | ranges = < | |
762 | 0 0 0xb0000000 0x08000000 | |
763 | 1 0 0xb8000000 0x08000000 | |
764 | 2 0 0xc0000000 0x08000000 | |
765 | 3 0 0xc8000000 0x04000000 | |
766 | 4 0 0xcc000000 0x02000000 | |
767 | 5 0 0xce000000 0x02000000 | |
768 | >; | |
769 | status = "disabled"; | |
770 | }; | |
771 | ||
7b7d6727 | 772 | nfc: nand@83fdb000 { |
75453a08 SH |
773 | compatible = "fsl,imx51-nand"; |
774 | reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; | |
775 | interrupts = <8>; | |
f40f38d1 | 776 | clocks = <&clks 60>; |
75453a08 SH |
777 | status = "disabled"; |
778 | }; | |
779 | ||
718a3500 SH |
780 | pata: pata@83fe0000 { |
781 | compatible = "fsl,imx51-pata", "fsl,imx27-pata"; | |
782 | reg = <0x83fe0000 0x4000>; | |
783 | interrupts = <70>; | |
784 | clocks = <&clks 161>; | |
785 | status = "disabled"; | |
786 | }; | |
787 | ||
a15d9f89 SG |
788 | ssi3: ssi@83fe8000 { |
789 | compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; | |
790 | reg = <0x83fe8000 0x4000>; | |
791 | interrupts = <96>; | |
f40f38d1 | 792 | clocks = <&clks 50>; |
5da826ab SG |
793 | dmas = <&sdma 46 0 0>, |
794 | <&sdma 47 0 0>; | |
795 | dma-names = "rx", "tx"; | |
a15d9f89 SG |
796 | fsl,fifo-depth = <15>; |
797 | fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ | |
798 | status = "disabled"; | |
799 | }; | |
800 | ||
7b7d6727 | 801 | fec: ethernet@83fec000 { |
9daaf31a SG |
802 | compatible = "fsl,imx51-fec", "fsl,imx27-fec"; |
803 | reg = <0x83fec000 0x4000>; | |
804 | interrupts = <87>; | |
f40f38d1 FE |
805 | clocks = <&clks 42>, <&clks 42>, <&clks 42>; |
806 | clock-names = "ipg", "ahb", "ptp"; | |
9daaf31a SG |
807 | status = "disabled"; |
808 | }; | |
809 | }; | |
810 | }; | |
811 | }; |