[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / imx51.dtsi

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
	};

	tzic: tz-interrupt-controller@e0000000 {
		compatible = "fsl,imx51-tzic", "fsl,tzic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0xe0000000 0x4000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		ckil {
			compatible = "fsl,imx-ckil", "fixed-clock";
			clock-frequency = <32768>;
		};

		ckih1 {
			compatible = "fsl,imx-ckih1", "fixed-clock";
			clock-frequency = <22579200>;
		};

		ckih2 {
			compatible = "fsl,imx-ckih2", "fixed-clock";
			clock-frequency = <0>;
		};

		osc {
			compatible = "fsl,imx-osc", "fixed-clock";
			clock-frequency = <24000000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&tzic>;
		ranges;

		aips@70000000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x70000000 0x10000000>;
			ranges;

			spba@70000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x70000000 0x40000>;
				ranges;

				esdhc@70004000 { /* ESDHC1 */
					compatible = "fsl,imx51-esdhc";
					reg = <0x70004000 0x4000>;
					interrupts = <1>;
					status = "disabled";
				};

				esdhc@70008000 { /* ESDHC2 */
					compatible = "fsl,imx51-esdhc";
					reg = <0x70008000 0x4000>;
					interrupts = <2>;
					status = "disabled";
				};

				uart3: serial@7000c000 {
					compatible = "fsl,imx51-uart", "fsl,imx21-uart";
					reg = <0x7000c000 0x4000>;
					interrupts = <33>;
					status = "disabled";
				};

				ecspi@70010000 { /* ECSPI1 */
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx51-ecspi";
					reg = <0x70010000 0x4000>;
					interrupts = <36>;
					status = "disabled";
				};

				ssi2: ssi@70014000 {
					compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
					reg = <0x70014000 0x4000>;
					interrupts = <30>;
					fsl,fifo-depth = <15>;
					fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
					status = "disabled";
				};

				esdhc@70020000 { /* ESDHC3 */
					compatible = "fsl,imx51-esdhc";
					reg = <0x70020000 0x4000>;
					interrupts = <3>;
					status = "disabled";
				};

				esdhc@70024000 { /* ESDHC4 */
					compatible = "fsl,imx51-esdhc";
					reg = <0x70024000 0x4000>;
					interrupts = <4>;
					status = "disabled";
				};
			};

			usb@73f80000 {
				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
				reg = <0x73f80000 0x0200>;
				interrupts = <18>;
				status = "disabled";
			};

			usb@73f80200 {
				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
				reg = <0x73f80200 0x0200>;
				interrupts = <14>;
				status = "disabled";
			};

			usb@73f80400 {
				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
				reg = <0x73f80400 0x0200>;
				interrupts = <16>;
				status = "disabled";
			};

			usb@73f80600 {
				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
				reg = <0x73f80600 0x0200>;
				interrupts = <17>;
				status = "disabled";
			};

			gpio1: gpio@73f84000 {
				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
				reg = <0x73f84000 0x4000>;
				interrupts = <50 51>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@73f88000 {
				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
				reg = <0x73f88000 0x4000>;
				interrupts = <52 53>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@73f8c000 {
				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
				reg = <0x73f8c000 0x4000>;
				interrupts = <54 55>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@73f90000 {
				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
				reg = <0x73f90000 0x4000>;
				interrupts = <56 57>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			wdog@73f98000 { /* WDOG1 */
				compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
				reg = <0x73f98000 0x4000>;
				interrupts = <58>;
			};

			wdog@73f9c000 { /* WDOG2 */
				compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
				reg = <0x73f9c000 0x4000>;
				interrupts = <59>;
				status = "disabled";
			};

			iomuxc@73fa8000 {
				compatible = "fsl,imx51-iomuxc";
				reg = <0x73fa8000 0x4000>;

				audmux {
					pinctrl_audmux_1: audmuxgrp-1 {
						fsl,pins = <
							384 0x80000000	/* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
							386 0x80000000	/* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
							389 0x80000000	/* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
							391 0x80000000	/* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
						>;
					};
				};

				fec {
					pinctrl_fec_1: fecgrp-1 {
						fsl,pins = <
							128 0x80000000	/* MX51_PAD_EIM_EB2__FEC_MDIO */
							134 0x80000000	/* MX51_PAD_EIM_EB3__FEC_RDATA1 */
							146 0x80000000	/* MX51_PAD_EIM_CS2__FEC_RDATA2 */
							152 0x80000000	/* MX51_PAD_EIM_CS3__FEC_RDATA3 */
							158 0x80000000	/* MX51_PAD_EIM_CS4__FEC_RX_ER */
							165 0x80000000	/* MX51_PAD_EIM_CS5__FEC_CRS */
							206 0x80000000	/* MX51_PAD_NANDF_RB2__FEC_COL */
							213 0x80000000	/* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
							293 0x80000000	/* MX51_PAD_NANDF_D9__FEC_RDATA0 */
							298 0x80000000	/* MX51_PAD_NANDF_D8__FEC_TDATA0 */
							225 0x80000000	/* MX51_PAD_NANDF_CS2__FEC_TX_ER */
							231 0x80000000	/* MX51_PAD_NANDF_CS3__FEC_MDC */
							237 0x80000000	/* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
							243 0x80000000	/* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
							250 0x80000000	/* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
							255 0x80000000	/* MX51_PAD_NANDF_CS7__FEC_TX_EN */
							260 0x80000000	/* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
						>;
					};
				};

				ecspi1 {
					pinctrl_ecspi1_1: ecspi1grp-1 {
						fsl,pins = <
							398 0x185	/* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
							394 0x185	/* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
							409 0x185	/* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
						>;
					};
				};

				esdhc1 {
					pinctrl_esdhc1_1: esdhc1grp-1 {
						fsl,pins = <
							666 0x400020d5	/* MX51_PAD_SD1_CMD__SD1_CMD */
							669 0x20d5	/* MX51_PAD_SD1_CLK__SD1_CLK */
							672 0x20d5	/* MX51_PAD_SD1_DATA0__SD1_DATA0 */
							678 0x20d5	/* MX51_PAD_SD1_DATA1__SD1_DATA1 */
							684 0x20d5	/* MX51_PAD_SD1_DATA2__SD1_DATA2 */
							691 0x20d5	/* MX51_PAD_SD1_DATA3__SD1_DATA3 */
						>;
					};
				};

				esdhc2 {
					pinctrl_esdhc2_1: esdhc2grp-1 {
						fsl,pins = <
							704 0x400020d5	/* MX51_PAD_SD2_CMD__SD2_CMD */
							707 0x20d5	/* MX51_PAD_SD2_CLK__SD2_CLK */
							710 0x20d5	/* MX51_PAD_SD2_DATA0__SD2_DATA0 */
							712 0x20d5	/* MX51_PAD_SD2_DATA1__SD2_DATA1 */
							715 0x20d5	/* MX51_PAD_SD2_DATA2__SD2_DATA2 */
							719 0x20d5	/* MX51_PAD_SD2_DATA3__SD2_DATA3 */
						>;
					};
				};

				i2c2 {
					pinctrl_i2c2_1: i2c2grp-1 {
						fsl,pins = <
							449 0x400001ed	/* MX51_PAD_KEY_COL4__I2C2_SCL */
							454 0x400001ed	/* MX51_PAD_KEY_COL5__I2C2_SDA */
						>;
					};
				};

				uart1 {
					pinctrl_uart1_1: uart1grp-1 {
						fsl,pins = <
							413 0x1c5	/* MX51_PAD_UART1_RXD__UART1_RXD */
							416 0x1c5	/* MX51_PAD_UART1_TXD__UART1_TXD */
							418 0x1c5	/* MX51_PAD_UART1_RTS__UART1_RTS */
							420 0x1c5	/* MX51_PAD_UART1_CTS__UART1_CTS */
						>;
					};
				};

				uart2 {
					pinctrl_uart2_1: uart2grp-1 {
						fsl,pins = <
							423 0x1c5	/* MX51_PAD_UART2_RXD__UART2_RXD */
							426 0x1c5	/* MX51_PAD_UART2_TXD__UART2_TXD */
						>;
					};
				};

				uart3 {
					pinctrl_uart3_1: uart3grp-1 {
						fsl,pins = <
							54 0x1c5	/* MX51_PAD_EIM_D25__UART3_RXD */
							59 0x1c5	/* MX51_PAD_EIM_D26__UART3_TXD */
							65 0x1c5	/* MX51_PAD_EIM_D27__UART3_RTS */
							49 0x1c5	/* MX51_PAD_EIM_D24__UART3_CTS */
						>;
					};
				};
			};

			uart1: serial@73fbc000 {
				compatible = "fsl,imx51-uart", "fsl,imx21-uart";
				reg = <0x73fbc000 0x4000>;
				interrupts = <31>;
				status = "disabled";
			};

			uart2: serial@73fc0000 {
				compatible = "fsl,imx51-uart", "fsl,imx21-uart";
				reg = <0x73fc0000 0x4000>;
				interrupts = <32>;
				status = "disabled";
			};
		};

		aips@80000000 {	/* AIPS2 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x80000000 0x10000000>;
			ranges;

			ecspi@83fac000 { /* ECSPI2 */
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx51-ecspi";
				reg = <0x83fac000 0x4000>;
				interrupts = <37>;
				status = "disabled";
			};

			sdma@83fb0000 {
				compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
				reg = <0x83fb0000 0x4000>;
				interrupts = <6>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
			};

			cspi@83fc0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
				reg = <0x83fc0000 0x4000>;
				interrupts = <38>;
				status = "disabled";
			};

			i2c@83fc4000 { /* I2C2 */
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
				reg = <0x83fc4000 0x4000>;
				interrupts = <63>;
				status = "disabled";
			};

			i2c@83fc8000 { /* I2C1 */
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
				reg = <0x83fc8000 0x4000>;
				interrupts = <62>;
				status = "disabled";
			};

			ssi1: ssi@83fcc000 {
				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
				reg = <0x83fcc000 0x4000>;
				interrupts = <29>;
				fsl,fifo-depth = <15>;
				fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
				status = "disabled";
			};

			audmux@83fd0000 {
				compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
				reg = <0x83fd0000 0x4000>;
				status = "disabled";
			};

			ssi3: ssi@83fe8000 {
				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
				reg = <0x83fe8000 0x4000>;
				interrupts = <96>;
				fsl,fifo-depth = <15>;
				fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
				status = "disabled";
			};

			ethernet@83fec000 {
				compatible = "fsl,imx51-fec", "fsl,imx27-fec";
				reg = <0x83fec000 0x4000>;
				interrupts = <87>;
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
9daaf31a SG	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc.
	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
	13	/include/ "skeleton.dtsi"
	14
	15	/ {
	16	aliases {
8f9ffecf RZ	17	serial0 = &uart1;
	18	serial1 = &uart2;
	19	serial2 = &uart3;
5230f8fe SG	20	gpio0 = &gpio1;
	21	gpio1 = &gpio2;
	22	gpio2 = &gpio3;
	23	gpio3 = &gpio4;
9daaf31a SG	24	};
	25
	26	tzic: tz-interrupt-controller@e0000000 {
	27	compatible = "fsl,imx51-tzic", "fsl,tzic";
	28	interrupt-controller;
	29	#interrupt-cells = <1>;
	30	reg = <0xe0000000 0x4000>;
	31	};
	32
	33	clocks {
	34	#address-cells = <1>;
	35	#size-cells = <0>;
	36
	37	ckil {
	38	compatible = "fsl,imx-ckil", "fixed-clock";
	39	clock-frequency = <32768>;
	40	};
	41
	42	ckih1 {
	43	compatible = "fsl,imx-ckih1", "fixed-clock";
	44	clock-frequency = <22579200>;
	45	};
	46
	47	ckih2 {
	48	compatible = "fsl,imx-ckih2", "fixed-clock";
	49	clock-frequency = <0>;
	50	};
	51
	52	osc {
	53	compatible = "fsl,imx-osc", "fixed-clock";
	54	clock-frequency = <24000000>;
	55	};
	56	};
	57
	58	soc {
	59	#address-cells = <1>;
	60	#size-cells = <1>;
	61	compatible = "simple-bus";
	62	interrupt-parent = <&tzic>;
	63	ranges;
	64
	65	aips@70000000 { /* AIPS1 */
	66	compatible = "fsl,aips-bus", "simple-bus";
	67	#address-cells = <1>;
	68	#size-cells = <1>;
	69	reg = <0x70000000 0x10000000>;
	70	ranges;
	71
	72	spba@70000000 {
	73	compatible = "fsl,spba-bus", "simple-bus";
	74	#address-cells = <1>;
	75	#size-cells = <1>;
	76	reg = <0x70000000 0x40000>;
	77	ranges;
	78
	79	esdhc@70004000 { /* ESDHC1 */
	80	compatible = "fsl,imx51-esdhc";
	81	reg = <0x70004000 0x4000>;
	82	interrupts = <1>;
	83	status = "disabled";
	84	};
	85
	86	esdhc@70008000 { /* ESDHC2 */
	87	compatible = "fsl,imx51-esdhc";
88	reg = <0x70008000 0x4000>;
89	interrupts = <2>;
90	status = "disabled";
91	};
92
0c456cfa	93	uart3: serial@7000c000 {
9daaf31a SG	94	compatible = "fsl,imx51-uart", "fsl,imx21-uart";
	95	reg = <0x7000c000 0x4000>;
	96	interrupts = <33>;
	97	status = "disabled";
	98	};
	99
	100	ecspi@70010000 { /* ECSPI1 */
	101	#address-cells = <1>;
	102	#size-cells = <0>;
	103	compatible = "fsl,imx51-ecspi";
	104	reg = <0x70010000 0x4000>;
	105	interrupts = <36>;
	106	status = "disabled";
	107	};
	108
a15d9f89 SG	109	ssi2: ssi@70014000 {
	110	compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
	111	reg = <0x70014000 0x4000>;
	112	interrupts = <30>;
	113	fsl,fifo-depth = <15>;
	114	fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
	115	status = "disabled";
	116	};
	117
9daaf31a SG	118	esdhc@70020000 { /* ESDHC3 */
	119	compatible = "fsl,imx51-esdhc";
	120	reg = <0x70020000 0x4000>;
	121	interrupts = <3>;
	122	status = "disabled";
	123	};
	124
	125	esdhc@70024000 { /* ESDHC4 */
	126	compatible = "fsl,imx51-esdhc";
	127	reg = <0x70024000 0x4000>;
	128	interrupts = <4>;
	129	status = "disabled";
	130	};
	131	};
	132
212d0b83 MG	133	usb@73f80000 {
	134	compatible = "fsl,imx51-usb", "fsl,imx27-usb";
	135	reg = <0x73f80000 0x0200>;
	136	interrupts = <18>;
	137	status = "disabled";
	138	};
	139
	140	usb@73f80200 {
	141	compatible = "fsl,imx51-usb", "fsl,imx27-usb";
	142	reg = <0x73f80200 0x0200>;
	143	interrupts = <14>;
	144	status = "disabled";
	145	};
	146
	147	usb@73f80400 {
	148	compatible = "fsl,imx51-usb", "fsl,imx27-usb";
	149	reg = <0x73f80400 0x0200>;
	150	interrupts = <16>;
	151	status = "disabled";
	152	};
	153
	154	usb@73f80600 {
	155	compatible = "fsl,imx51-usb", "fsl,imx27-usb";
	156	reg = <0x73f80600 0x0200>;
	157	interrupts = <17>;
	158	status = "disabled";
	159	};
	160
4d191868	161	gpio1: gpio@73f84000 {
aeb27748	162	compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
9daaf31a SG	163	reg = <0x73f84000 0x4000>;
	164	interrupts = <50 51>;
	165	gpio-controller;
	166	#gpio-cells = <2>;
	167	interrupt-controller;
88cde8b7	168	#interrupt-cells = <2>;
9daaf31a SG	169	};
9daaf31a SG	170
4d191868	171	gpio2: gpio@73f88000 {
aeb27748	172	compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
9daaf31a SG	173	reg = <0x73f88000 0x4000>;
	174	interrupts = <52 53>;
	175	gpio-controller;
	176	#gpio-cells = <2>;
	177	interrupt-controller;
88cde8b7	178	#interrupt-cells = <2>;
9daaf31a SG	179	};
9daaf31a SG	180
4d191868	181	gpio3: gpio@73f8c000 {
aeb27748	182	compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
9daaf31a SG	183	reg = <0x73f8c000 0x4000>;
	184	interrupts = <54 55>;
	185	gpio-controller;
	186	#gpio-cells = <2>;
	187	interrupt-controller;
88cde8b7	188	#interrupt-cells = <2>;
9daaf31a SG	189	};
9daaf31a SG	190
4d191868	191	gpio4: gpio@73f90000 {
aeb27748	192	compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
9daaf31a SG	193	reg = <0x73f90000 0x4000>;
	194	interrupts = <56 57>;
	195	gpio-controller;
	196	#gpio-cells = <2>;
	197	interrupt-controller;
88cde8b7	198	#interrupt-cells = <2>;
9daaf31a SG	199	};
	200
	201	wdog@73f98000 { /* WDOG1 */
	202	compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
	203	reg = <0x73f98000 0x4000>;
	204	interrupts = <58>;
9daaf31a SG	205	};
	206
	207	wdog@73f9c000 { /* WDOG2 */
	208	compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
	209	reg = <0x73f9c000 0x4000>;
	210	interrupts = <59>;
	211	status = "disabled";
	212	};
	213
b72cf105 SG	214	iomuxc@73fa8000 {
	215	compatible = "fsl,imx51-iomuxc";
	216	reg = <0x73fa8000 0x4000>;
	217
	218	audmux {
	219	pinctrl_audmux_1: audmuxgrp-1 {
	220	fsl,pins = <
	221	384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
	222	386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
	223	389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
	224	391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
	225	>;
	226	};
	227	};
	228
	229	fec {
	230	pinctrl_fec_1: fecgrp-1 {
	231	fsl,pins = <
	232	128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
	233	134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
	234	146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
	235	152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
	236	158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
	237	165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
	238	206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
	239	213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
	240	293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
	241	298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
	242	225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
	243	231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
	244	237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
	245	243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
	246	250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
	247	255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
	248	260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
	249	>;
	250	};
	251	};
	252
	253	ecspi1 {
	254	pinctrl_ecspi1_1: ecspi1grp-1 {
	255	fsl,pins = <
	256	398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
	257	394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
	258	409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
	259	>;
	260	};
	261	};
	262
	263	esdhc1 {
	264	pinctrl_esdhc1_1: esdhc1grp-1 {
	265	fsl,pins = <
	266	666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
	267	669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
	268	672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
	269	678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
	270	684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
	271	691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
	272	>;
	273	};
	274	};
	275
	276	esdhc2 {
	277	pinctrl_esdhc2_1: esdhc2grp-1 {
278	fsl,pins = <
279	704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
280	707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
281	710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
282	712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
283	715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
284	719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
285	>;
286	};
287	};
288
289	i2c2 {
290	pinctrl_i2c2_1: i2c2grp-1 {
291	fsl,pins = <
292	449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
293	454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
294	>;
295	};
296	};
297
298	uart1 {
299	pinctrl_uart1_1: uart1grp-1 {
300	fsl,pins = <
301	413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
302	416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
303	418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
304	420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
305	>;
306	};
307	};
308
309	uart2 {
310	pinctrl_uart2_1: uart2grp-1 {
311	fsl,pins = <
312	423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
313	426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
314	>;
315	};
316	};
317
318	uart3 {
319	pinctrl_uart3_1: uart3grp-1 {
320	fsl,pins = <
321	54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
322	59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
323	65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
324	49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
325	>;
326	};
327	};
328	};
329
0c456cfa	330	uart1: serial@73fbc000 {
9daaf31a SG	331	compatible = "fsl,imx51-uart", "fsl,imx21-uart";
	332	reg = <0x73fbc000 0x4000>;
	333	interrupts = <31>;
	334	status = "disabled";
	335	};
	336
0c456cfa	337	uart2: serial@73fc0000 {
9daaf31a SG	338	compatible = "fsl,imx51-uart", "fsl,imx21-uart";
	339	reg = <0x73fc0000 0x4000>;
	340	interrupts = <32>;
	341	status = "disabled";
	342	};
	343	};
	344
	345	aips@80000000 { /* AIPS2 */
	346	compatible = "fsl,aips-bus", "simple-bus";
	347	#address-cells = <1>;
	348	#size-cells = <1>;
	349	reg = <0x80000000 0x10000000>;
	350	ranges;
	351
	352	ecspi@83fac000 { /* ECSPI2 */
	353	#address-cells = <1>;
	354	#size-cells = <0>;
	355	compatible = "fsl,imx51-ecspi";
	356	reg = <0x83fac000 0x4000>;
	357	interrupts = <37>;
	358	status = "disabled";
	359	};
	360
	361	sdma@83fb0000 {
	362	compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
	363	reg = <0x83fb0000 0x4000>;
	364	interrupts = <6>;
7e4f0365	365	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
9daaf31a SG	366	};
	367
	368	cspi@83fc0000 {
	369	#address-cells = <1>;
	370	#size-cells = <0>;
	371	compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
	372	reg = <0x83fc0000 0x4000>;
	373	interrupts = <38>;
	374	status = "disabled";
	375	};
	376
	377	i2c@83fc4000 { /* I2C2 */
	378	#address-cells = <1>;
	379	#size-cells = <0>;
	380	compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
	381	reg = <0x83fc4000 0x4000>;
	382	interrupts = <63>;
	383	status = "disabled";
	384	};
	385
	386	i2c@83fc8000 { /* I2C1 */
	387	#address-cells = <1>;
	388	#size-cells = <0>;
	389	compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
	390	reg = <0x83fc8000 0x4000>;
	391	interrupts = <62>;
	392	status = "disabled";
	393	};
	394
a15d9f89 SG	395	ssi1: ssi@83fcc000 {
	396	compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
	397	reg = <0x83fcc000 0x4000>;
	398	interrupts = <29>;
	399	fsl,fifo-depth = <15>;
	400	fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
	401	status = "disabled";
	402	};
	403
	404	audmux@83fd0000 {
	405	compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
	406	reg = <0x83fd0000 0x4000>;
	407	status = "disabled";
	408	};
	409
	410	ssi3: ssi@83fe8000 {
	411	compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
	412	reg = <0x83fe8000 0x4000>;
	413	interrupts = <96>;
	414	fsl,fifo-depth = <15>;
	415	fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
	416	status = "disabled";
	417	};
	418
0c456cfa	419	ethernet@83fec000 {
9daaf31a SG	420	compatible = "fsl,imx51-fec", "fsl,imx27-fec";
	421	reg = <0x83fec000 0x4000>;
	422	interrupts = <87>;
	423	status = "disabled";
	424	};
	425	};
	426	};
	427	};