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be3a568d ST |
1 | /* |
2 | * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | |
3 | * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | /dts-v1/; | |
36dffd8f | 14 | #include "imx53-tqma53.dtsi" |
be3a568d ST |
15 | |
16 | / { | |
17 | model = "TQ MBa53 starter kit"; | |
18 | compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; | |
4fa8cf79 | 19 | |
4fa8cf79 SH |
20 | backlight { |
21 | compatible = "pwm-backlight"; | |
15968f1b | 22 | pwms = <&pwm2 0 50000>; |
4fa8cf79 SH |
23 | brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>; |
24 | default-brightness-level = <10>; | |
25 | enable-gpios = <&gpio7 7 0>; | |
26 | power-supply = <®_backlight>; | |
27 | }; | |
28 | ||
29 | disp1: display@disp1 { | |
30 | compatible = "fsl,imx-parallel-display"; | |
31 | pinctrl-names = "default"; | |
32 | pinctrl-0 = <&pinctrl_disp1_1>; | |
33 | crtcs = <&ipu 1>; | |
34 | interface-pix-fmt = "rgb24"; | |
35 | status = "disabled"; | |
36 | }; | |
eefb8008 | 37 | |
a4a2aa9b SG |
38 | regulators { |
39 | compatible = "simple-bus"; | |
352d318c SG |
40 | #address-cells = <1>; |
41 | #size-cells = <0>; | |
a4a2aa9b | 42 | |
352d318c | 43 | reg_backlight: regulator@0 { |
a4a2aa9b | 44 | compatible = "regulator-fixed"; |
352d318c | 45 | reg = <0>; |
a4a2aa9b SG |
46 | regulator-name = "lcd-supply"; |
47 | gpio = <&gpio2 5 0>; | |
48 | startup-delay-us = <5000>; | |
49 | enable-active-low; | |
50 | }; | |
51 | ||
352d318c | 52 | reg_3p2v: regulator@1 { |
a4a2aa9b | 53 | compatible = "regulator-fixed"; |
352d318c | 54 | reg = <1>; |
a4a2aa9b SG |
55 | regulator-name = "3P2V"; |
56 | regulator-min-microvolt = <3200000>; | |
57 | regulator-max-microvolt = <3200000>; | |
58 | regulator-always-on; | |
59 | }; | |
eefb8008 MN |
60 | }; |
61 | ||
62 | sound { | |
63 | compatible = "tq,imx53-mba53-sgtl5000", | |
64 | "fsl,imx-audio-sgtl5000"; | |
65 | model = "imx53-mba53-sgtl5000"; | |
66 | ssi-controller = <&ssi2>; | |
67 | audio-codec = <&codec>; | |
68 | audio-routing = | |
69 | "MIC_IN", "Mic Jack", | |
70 | "Mic Jack", "Mic Bias", | |
71 | "Headphone Jack", "HP_OUT"; | |
72 | mux-int-port = <2>; | |
73 | mux-ext-port = <5>; | |
74 | }; | |
4fa8cf79 SH |
75 | }; |
76 | ||
77 | &ldb { | |
78 | pinctrl-names = "default"; | |
79 | pinctrl-0 = <&pinctrl_lvds1_1>; | |
80 | status = "disabled"; | |
be3a568d ST |
81 | }; |
82 | ||
83 | &iomuxc { | |
84 | lvds1 { | |
85 | pinctrl_lvds1_1: lvds1-grp1 { | |
e1641531 | 86 | fsl,pins = < |
188e97db ST |
87 | MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 |
88 | MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 | |
89 | MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 | |
90 | MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 | |
91 | MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 | |
e1641531 | 92 | >; |
be3a568d ST |
93 | }; |
94 | ||
95 | pinctrl_lvds1_2: lvds1-grp2 { | |
e1641531 | 96 | fsl,pins = < |
188e97db ST |
97 | MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 |
98 | MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 | |
99 | MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 | |
100 | MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 | |
101 | MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 | |
e1641531 | 102 | >; |
be3a568d ST |
103 | }; |
104 | }; | |
105 | ||
106 | disp1 { | |
107 | pinctrl_disp1_1: disp1-grp1 { | |
e1641531 | 108 | fsl,pins = < |
81b8a3cd | 109 | MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */ |
188e97db ST |
110 | MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */ |
111 | MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */ | |
112 | MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */ | |
113 | MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000 | |
114 | MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000 | |
115 | MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000 | |
116 | MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000 | |
117 | MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000 | |
118 | MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000 | |
119 | MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000 | |
120 | MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000 | |
121 | MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000 | |
122 | MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000 | |
123 | MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000 | |
124 | MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000 | |
125 | MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000 | |
126 | MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000 | |
127 | MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000 | |
128 | MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000 | |
129 | MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000 | |
130 | MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000 | |
131 | MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000 | |
132 | MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000 | |
133 | MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000 | |
134 | MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000 | |
135 | MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000 | |
136 | MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000 | |
e1641531 | 137 | >; |
be3a568d ST |
138 | }; |
139 | }; | |
d7db5392 PZ |
140 | |
141 | tve { | |
142 | pinctrl_vga_sync_1: vgasync-grp1 { | |
143 | fsl,pins = < | |
144 | /* VGA_VSYNC, HSYNC with max drive strength */ | |
145 | MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6 | |
146 | MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6 | |
147 | >; | |
148 | }; | |
149 | }; | |
be3a568d ST |
150 | }; |
151 | ||
152 | &cspi { | |
153 | status = "okay"; | |
154 | }; | |
155 | ||
eefb8008 MN |
156 | &audmux { |
157 | status = "okay"; | |
158 | pinctrl-names = "default"; | |
7ac0f700 | 159 | pinctrl-0 = <&pinctrl_audmux>; |
eefb8008 MN |
160 | }; |
161 | ||
be3a568d ST |
162 | &i2c2 { |
163 | codec: sgtl5000@a { | |
164 | compatible = "fsl,sgtl5000"; | |
165 | reg = <0x0a>; | |
eefb8008 MN |
166 | clocks = <&clks 150>; |
167 | VDDA-supply = <®_3p2v>; | |
168 | VDDIO-supply = <®_3p2v>; | |
be3a568d ST |
169 | }; |
170 | ||
171 | expander: pca9554@20 { | |
172 | compatible = "pca9554"; | |
173 | reg = <0x20>; | |
174 | interrupts = <109>; | |
74154be0 MN |
175 | #gpio-cells = <2>; |
176 | gpio-controller; | |
be3a568d ST |
177 | }; |
178 | ||
179 | sensor2: lm75@49 { | |
180 | compatible = "lm75"; | |
181 | reg = <0x49>; | |
182 | }; | |
183 | }; | |
184 | ||
185 | &fec { | |
deb19eb7 | 186 | phy-reset-gpios = <&gpio7 6 0>; |
be3a568d ST |
187 | status = "okay"; |
188 | }; | |
189 | ||
190 | &esdhc2 { | |
191 | status = "okay"; | |
192 | }; | |
193 | ||
194 | &uart3 { | |
195 | status = "okay"; | |
196 | }; | |
197 | ||
198 | &ecspi1 { | |
199 | status = "okay"; | |
200 | }; | |
201 | ||
3b1a0f23 MO |
202 | &usbotg { |
203 | dr_mode = "host"; | |
204 | status = "okay"; | |
205 | }; | |
206 | ||
207 | &usbh1 { | |
208 | status = "okay"; | |
209 | }; | |
210 | ||
be3a568d ST |
211 | &uart1 { |
212 | status = "okay"; | |
213 | }; | |
214 | ||
eefb8008 MN |
215 | &ssi2 { |
216 | fsl,mode = "i2s-slave"; | |
217 | status = "okay"; | |
218 | }; | |
219 | ||
be3a568d ST |
220 | &uart2 { |
221 | status = "okay"; | |
222 | }; | |
223 | ||
224 | &can1 { | |
225 | status = "okay"; | |
226 | }; | |
227 | ||
228 | &can2 { | |
229 | status = "okay"; | |
230 | }; | |
231 | ||
232 | &i2c3 { | |
233 | status = "okay"; | |
234 | }; | |
d7db5392 PZ |
235 | |
236 | &tve { | |
237 | pinctrl-names = "default"; | |
238 | pinctrl-0 = <&pinctrl_vga_sync_1>; | |
239 | ddc = <&i2c3>; | |
240 | fsl,tve-mode = "vga"; | |
241 | fsl,hsync-pin = <4>; | |
242 | fsl,vsync-pin = <6>; | |
243 | status = "okay"; | |
244 | }; |