projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 73d2b4cd SG |
1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
| 3 | * Copyright 2011 Linaro Ltd. | |
| 4 | * | |
| 5 | * The code contained herein is licensed under the GNU General Public | |
| 6 | * License. You may obtain a copy of the GNU General Public License | |
| 7 | * Version 2 or later at the following locations: | |
| 8 | * | |
| 9 | * http://www.opensource.org/licenses/gpl-license.html | |
| 10 | * http://www.gnu.org/copyleft/gpl.html | |
| 11 | */ | |
| 12 | ||
| 36dffd8f | 13 | #include "skeleton.dtsi" |
| e1641531 | 14 | #include "imx53-pinfunc.h" |
| 564695dd | 15 | #include <dt-bindings/clock/imx5-clock.h> |
| 4e05a7af DC |
16 | #include <dt-bindings/gpio/gpio.h> |
| 17 | #include <dt-bindings/input/input.h> | |
| 73d2b4cd SG |
18 | |
| 19 | / { | |
| 20 | aliases { | |
| 5230f8fe SG |
21 | gpio0 = &gpio1; |
| 22 | gpio1 = &gpio2; | |
| 23 | gpio2 = &gpio3; | |
| 24 | gpio3 = &gpio4; | |
| 25 | gpio4 = &gpio5; | |
| 26 | gpio5 = &gpio6; | |
| 27 | gpio6 = &gpio7; | |
| c60dc1d1 PZ |
28 | i2c0 = &i2c1; |
| 29 | i2c1 = &i2c2; | |
| 30 | i2c2 = &i2c3; | |
| c63d06de SH |
31 | mmc0 = &esdhc1; |
| 32 | mmc1 = &esdhc2; | |
| 33 | mmc2 = &esdhc3; | |
| 34 | mmc3 = &esdhc4; | |
| cf4e577e SH |
35 | serial0 = &uart1; |
| 36 | serial1 = &uart2; | |
| 37 | serial2 = &uart3; | |
| 38 | serial3 = &uart4; | |
| 39 | serial4 = &uart5; | |
| 40 | spi0 = &ecspi1; | |
| 41 | spi1 = &ecspi2; | |
| 42 | spi2 = &cspi; | |
| 73d2b4cd SG |
43 | }; |
| 44 | ||
| 070bd7e4 FE |
45 | cpus { |
| 46 | #address-cells = <1>; | |
| 47 | #size-cells = <0>; | |
| 48 | cpu@0 { | |
| 49 | device_type = "cpu"; | |
| 50 | compatible = "arm,cortex-a8"; | |
| 51 | reg = <0x0>; | |
| 52 | }; | |
| 53 | }; | |
| 54 | ||
| e05c8c9a PZ |
55 | display-subsystem { |
| 56 | compatible = "fsl,imx-display-subsystem"; | |
| 57 | ports = <&ipu_di0>, <&ipu_di1>; | |
| 58 | }; | |
| 59 | ||
| 73d2b4cd SG |
60 | tzic: tz-interrupt-controller@0fffc000 { |
| 61 | compatible = "fsl,imx53-tzic", "fsl,tzic"; | |
| 62 | interrupt-controller; | |
| 63 | #interrupt-cells = <1>; | |
| 64 | reg = <0x0fffc000 0x4000>; | |
| 65 | }; | |
| 66 | ||
| 67 | clocks { | |
| 68 | #address-cells = <1>; | |
| 69 | #size-cells = <0>; | |
| 70 | ||
| 71 | ckil { | |
| 72 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
| 4b2b4043 | 73 | #clock-cells = <0>; |
| 73d2b4cd SG |
74 | clock-frequency = <32768>; |
| 75 | }; | |
| 76 | ||
| 77 | ckih1 { | |
| 78 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
| 4b2b4043 | 79 | #clock-cells = <0>; |
| 73d2b4cd SG |
80 | clock-frequency = <22579200>; |
| 81 | }; | |
| 82 | ||
| 83 | ckih2 { | |
| 84 | compatible = "fsl,imx-ckih2", "fixed-clock"; | |
| 4b2b4043 | 85 | #clock-cells = <0>; |
| 73d2b4cd SG |
86 | clock-frequency = <0>; |
| 87 | }; | |
| 88 | ||
| 89 | osc { | |
| 90 | compatible = "fsl,imx-osc", "fixed-clock"; | |
| 4b2b4043 | 91 | #clock-cells = <0>; |
| 73d2b4cd SG |
92 | clock-frequency = <24000000>; |
| 93 | }; | |
| 94 | }; | |
| 95 | ||
| 96 | soc { | |
| 97 | #address-cells = <1>; | |
| 98 | #size-cells = <1>; | |
| 99 | compatible = "simple-bus"; | |
| 100 | interrupt-parent = <&tzic>; | |
| 101 | ranges; | |
| 102 | ||
| 7affee43 MV |
103 | sata: sata@10000000 { |
| 104 | compatible = "fsl,imx53-ahci"; | |
| 105 | reg = <0x10000000 0x1000>; | |
| 106 | interrupts = <28>; | |
| 107 | clocks = <&clks IMX5_CLK_SATA_GATE>, | |
| 108 | <&clks IMX5_CLK_SATA_REF>, | |
| 109 | <&clks IMX5_CLK_AHB>; | |
| 110 | clock-names = "sata_gate", "sata_ref", "ahb"; | |
| 111 | status = "disabled"; | |
| 112 | }; | |
| 113 | ||
| abed9a6b | 114 | ipu: ipu@18000000 { |
| e05c8c9a PZ |
115 | #address-cells = <1>; |
| 116 | #size-cells = <0>; | |
| abed9a6b SH |
117 | compatible = "fsl,imx53-ipu"; |
| 118 | reg = <0x18000000 0x080000000>; | |
| 119 | interrupts = <11 10>; | |
| 564695dd LS |
120 | clocks = <&clks IMX5_CLK_IPU_GATE>, |
| 121 | <&clks IMX5_CLK_IPU_DI0_GATE>, | |
| 122 | <&clks IMX5_CLK_IPU_DI1_GATE>; | |
| 4438a6a1 | 123 | clock-names = "bus", "di0", "di1"; |
| 8d84c374 | 124 | resets = <&src 2>; |
| e05c8c9a PZ |
125 | |
| 126 | ipu_di0: port@2 { | |
| 127 | #address-cells = <1>; | |
| 128 | #size-cells = <0>; | |
| 129 | reg = <2>; | |
| 130 | ||
| 131 | ipu_di0_disp0: endpoint@0 { | |
| 132 | reg = <0>; | |
| 133 | }; | |
| 134 | ||
| 135 | ipu_di0_lvds0: endpoint@1 { | |
| 136 | reg = <1>; | |
| 137 | remote-endpoint = <&lvds0_in>; | |
| 138 | }; | |
| 139 | }; | |
| 140 | ||
| 141 | ipu_di1: port@3 { | |
| 142 | #address-cells = <1>; | |
| 143 | #size-cells = <0>; | |
| 144 | reg = <3>; | |
| 145 | ||
| 146 | ipu_di1_disp1: endpoint@0 { | |
| 147 | reg = <0>; | |
| 148 | }; | |
| 149 | ||
| 150 | ipu_di1_lvds1: endpoint@1 { | |
| 151 | reg = <1>; | |
| 152 | remote-endpoint = <&lvds1_in>; | |
| 153 | }; | |
| 154 | ||
| 155 | ipu_di1_tve: endpoint@2 { | |
| 156 | reg = <2>; | |
| 157 | remote-endpoint = <&tve_in>; | |
| 158 | }; | |
| 159 | }; | |
| abed9a6b SH |
160 | }; |
| 161 | ||
| 73d2b4cd SG |
162 | aips@50000000 { /* AIPS1 */ |
| 163 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 164 | #address-cells = <1>; | |
| 165 | #size-cells = <1>; | |
| 166 | reg = <0x50000000 0x10000000>; | |
| 167 | ranges; | |
| 168 | ||
| 169 | spba@50000000 { | |
| 170 | compatible = "fsl,spba-bus", "simple-bus"; | |
| 171 | #address-cells = <1>; | |
| 172 | #size-cells = <1>; | |
| 173 | reg = <0x50000000 0x40000>; | |
| 174 | ranges; | |
| 175 | ||
| 7b7d6727 | 176 | esdhc1: esdhc@50004000 { |
| 73d2b4cd SG |
177 | compatible = "fsl,imx53-esdhc"; |
| 178 | reg = <0x50004000 0x4000>; | |
| 179 | interrupts = <1>; | |
| 564695dd LS |
180 | clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, |
| 181 | <&clks IMX5_CLK_DUMMY>, | |
| 182 | <&clks IMX5_CLK_ESDHC1_PER_GATE>; | |
| f40f38d1 | 183 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 184 | bus-width = <4>; |
| 73d2b4cd SG |
185 | status = "disabled"; |
| 186 | }; | |
| 187 | ||
| 7b7d6727 | 188 | esdhc2: esdhc@50008000 { |
| 73d2b4cd SG |
189 | compatible = "fsl,imx53-esdhc"; |
| 190 | reg = <0x50008000 0x4000>; | |
| 191 | interrupts = <2>; | |
| 564695dd LS |
192 | clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, |
| 193 | <&clks IMX5_CLK_DUMMY>, | |
| 194 | <&clks IMX5_CLK_ESDHC2_PER_GATE>; | |
| f40f38d1 | 195 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 196 | bus-width = <4>; |
| 73d2b4cd SG |
197 | status = "disabled"; |
| 198 | }; | |
| 199 | ||
| 0c456cfa | 200 | uart3: serial@5000c000 { |
| 73d2b4cd SG |
201 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 202 | reg = <0x5000c000 0x4000>; | |
| 203 | interrupts = <33>; | |
| 564695dd LS |
204 | clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, |
| 205 | <&clks IMX5_CLK_UART3_PER_GATE>; | |
| f40f38d1 | 206 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
207 | status = "disabled"; |
| 208 | }; | |
| 209 | ||
| 7b7d6727 | 210 | ecspi1: ecspi@50010000 { |
| 73d2b4cd SG |
211 | #address-cells = <1>; |
| 212 | #size-cells = <0>; | |
| 213 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
| 214 | reg = <0x50010000 0x4000>; | |
| 215 | interrupts = <36>; | |
| 564695dd LS |
216 | clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, |
| 217 | <&clks IMX5_CLK_ECSPI1_PER_GATE>; | |
| f40f38d1 | 218 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
219 | status = "disabled"; |
| 220 | }; | |
| 221 | ||
| ffc505c0 | 222 | ssi2: ssi@50014000 { |
| 28f93d0b MP |
223 | compatible = "fsl,imx53-ssi", |
| 224 | "fsl,imx51-ssi", | |
| 225 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
226 | reg = <0x50014000 0x4000>; |
| 227 | interrupts = <30>; | |
| 564695dd | 228 | clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; |
| 5da826ab SG |
229 | dmas = <&sdma 24 1 0>, |
| 230 | <&sdma 25 1 0>; | |
| 231 | dma-names = "rx", "tx"; | |
| ffc505c0 SG |
232 | fsl,fifo-depth = <15>; |
| 233 | fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ | |
| 234 | status = "disabled"; | |
| 235 | }; | |
| 236 | ||
| 7b7d6727 | 237 | esdhc3: esdhc@50020000 { |
| 73d2b4cd SG |
238 | compatible = "fsl,imx53-esdhc"; |
| 239 | reg = <0x50020000 0x4000>; | |
| 240 | interrupts = <3>; | |
| 564695dd LS |
241 | clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, |
| 242 | <&clks IMX5_CLK_DUMMY>, | |
| 243 | <&clks IMX5_CLK_ESDHC3_PER_GATE>; | |
| f40f38d1 | 244 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 245 | bus-width = <4>; |
| 73d2b4cd SG |
246 | status = "disabled"; |
| 247 | }; | |
| 248 | ||
| 7b7d6727 | 249 | esdhc4: esdhc@50024000 { |
| 73d2b4cd SG |
250 | compatible = "fsl,imx53-esdhc"; |
| 251 | reg = <0x50024000 0x4000>; | |
| 252 | interrupts = <4>; | |
| 564695dd LS |
253 | clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, |
| 254 | <&clks IMX5_CLK_DUMMY>, | |
| 255 | <&clks IMX5_CLK_ESDHC4_PER_GATE>; | |
| f40f38d1 | 256 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 257 | bus-width = <4>; |
| 73d2b4cd SG |
258 | status = "disabled"; |
| 259 | }; | |
| 260 | }; | |
| 261 | ||
| a79025c4 MG |
262 | usbphy0: usbphy@0 { |
| 263 | compatible = "usb-nop-xceiv"; | |
| 564695dd | 264 | clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; |
| a79025c4 MG |
265 | clock-names = "main_clk"; |
| 266 | status = "okay"; | |
| 267 | }; | |
| 268 | ||
| 269 | usbphy1: usbphy@1 { | |
| 270 | compatible = "usb-nop-xceiv"; | |
| 564695dd | 271 | clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; |
| a79025c4 MG |
272 | clock-names = "main_clk"; |
| 273 | status = "okay"; | |
| 274 | }; | |
| 275 | ||
| 7b7d6727 | 276 | usbotg: usb@53f80000 { |
| 212d0b83 MG |
277 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 278 | reg = <0x53f80000 0x0200>; | |
| 279 | interrupts = <18>; | |
| 564695dd | 280 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 281 | fsl,usbmisc = <&usbmisc 0>; |
| a79025c4 | 282 | fsl,usbphy = <&usbphy0>; |
| 212d0b83 MG |
283 | status = "disabled"; |
| 284 | }; | |
| 285 | ||
| 7b7d6727 | 286 | usbh1: usb@53f80200 { |
| 212d0b83 MG |
287 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 288 | reg = <0x53f80200 0x0200>; | |
| 289 | interrupts = <14>; | |
| 564695dd | 290 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 291 | fsl,usbmisc = <&usbmisc 1>; |
| a79025c4 | 292 | fsl,usbphy = <&usbphy1>; |
| 212d0b83 MG |
293 | status = "disabled"; |
| 294 | }; | |
| 295 | ||
| 7b7d6727 | 296 | usbh2: usb@53f80400 { |
| 212d0b83 MG |
297 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 298 | reg = <0x53f80400 0x0200>; | |
| 299 | interrupts = <16>; | |
| 564695dd | 300 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 301 | fsl,usbmisc = <&usbmisc 2>; |
| 212d0b83 MG |
302 | status = "disabled"; |
| 303 | }; | |
| 304 | ||
| 7b7d6727 | 305 | usbh3: usb@53f80600 { |
| 212d0b83 MG |
306 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 307 | reg = <0x53f80600 0x0200>; | |
| 308 | interrupts = <17>; | |
| 564695dd | 309 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 310 | fsl,usbmisc = <&usbmisc 3>; |
| 212d0b83 MG |
311 | status = "disabled"; |
| 312 | }; | |
| 313 | ||
| a5735021 MG |
314 | usbmisc: usbmisc@53f80800 { |
| 315 | #index-cells = <1>; | |
| 316 | compatible = "fsl,imx53-usbmisc"; | |
| 317 | reg = <0x53f80800 0x200>; | |
| 564695dd | 318 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 MG |
319 | }; |
| 320 | ||
| 4d191868 | 321 | gpio1: gpio@53f84000 { |
| aeb27748 | 322 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
323 | reg = <0x53f84000 0x4000>; |
| 324 | interrupts = <50 51>; | |
| 325 | gpio-controller; | |
| 326 | #gpio-cells = <2>; | |
| 327 | interrupt-controller; | |
| 88cde8b7 | 328 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
329 | }; |
| 330 | ||
| 4d191868 | 331 | gpio2: gpio@53f88000 { |
| aeb27748 | 332 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
333 | reg = <0x53f88000 0x4000>; |
| 334 | interrupts = <52 53>; | |
| 335 | gpio-controller; | |
| 336 | #gpio-cells = <2>; | |
| 337 | interrupt-controller; | |
| 88cde8b7 | 338 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
339 | }; |
| 340 | ||
| 4d191868 | 341 | gpio3: gpio@53f8c000 { |
| aeb27748 | 342 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
343 | reg = <0x53f8c000 0x4000>; |
| 344 | interrupts = <54 55>; | |
| 345 | gpio-controller; | |
| 346 | #gpio-cells = <2>; | |
| 347 | interrupt-controller; | |
| 88cde8b7 | 348 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
349 | }; |
| 350 | ||
| 4d191868 | 351 | gpio4: gpio@53f90000 { |
| aeb27748 | 352 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
353 | reg = <0x53f90000 0x4000>; |
| 354 | interrupts = <56 57>; | |
| 355 | gpio-controller; | |
| 356 | #gpio-cells = <2>; | |
| 357 | interrupt-controller; | |
| 88cde8b7 | 358 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
359 | }; |
| 360 | ||
| 675e4d03 RL |
361 | kpp: kpp@53f94000 { |
| 362 | compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; | |
| 363 | reg = <0x53f94000 0x4000>; | |
| 364 | interrupts = <60>; | |
| 564695dd | 365 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 675e4d03 RL |
366 | status = "disabled"; |
| 367 | }; | |
| 368 | ||
| 7b7d6727 | 369 | wdog1: wdog@53f98000 { |
| 73d2b4cd SG |
370 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 371 | reg = <0x53f98000 0x4000>; | |
| 372 | interrupts = <58>; | |
| 564695dd | 373 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 73d2b4cd SG |
374 | }; |
| 375 | ||
| 7b7d6727 | 376 | wdog2: wdog@53f9c000 { |
| 73d2b4cd SG |
377 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 378 | reg = <0x53f9c000 0x4000>; | |
| 379 | interrupts = <59>; | |
| 564695dd | 380 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 73d2b4cd SG |
381 | status = "disabled"; |
| 382 | }; | |
| 383 | ||
| cc8aae9b SH |
384 | gpt: timer@53fa0000 { |
| 385 | compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; | |
| 386 | reg = <0x53fa0000 0x4000>; | |
| 387 | interrupts = <39>; | |
| 564695dd LS |
388 | clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, |
| 389 | <&clks IMX5_CLK_GPT_HF_GATE>; | |
| cc8aae9b SH |
390 | clock-names = "ipg", "per"; |
| 391 | }; | |
| 392 | ||
| 7b7d6727 | 393 | iomuxc: iomuxc@53fa8000 { |
| 5be03a7b SG |
394 | compatible = "fsl,imx53-iomuxc"; |
| 395 | reg = <0x53fa8000 0x4000>; | |
| 5be03a7b SG |
396 | }; |
| 397 | ||
| 5af9f143 PZ |
398 | gpr: iomuxc-gpr@53fa8000 { |
| 399 | compatible = "fsl,imx53-iomuxc-gpr", "syscon"; | |
| 400 | reg = <0x53fa8000 0xc>; | |
| 401 | }; | |
| 402 | ||
| 420714aa PZ |
403 | ldb: ldb@53fa8008 { |
| 404 | #address-cells = <1>; | |
| 405 | #size-cells = <0>; | |
| 406 | compatible = "fsl,imx53-ldb"; | |
| 407 | reg = <0x53fa8008 0x4>; | |
| 408 | gpr = <&gpr>; | |
| 564695dd LS |
409 | clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, |
| 410 | <&clks IMX5_CLK_LDB_DI1_SEL>, | |
| 411 | <&clks IMX5_CLK_IPU_DI0_SEL>, | |
| 412 | <&clks IMX5_CLK_IPU_DI1_SEL>, | |
| 413 | <&clks IMX5_CLK_LDB_DI0_GATE>, | |
| 414 | <&clks IMX5_CLK_LDB_DI1_GATE>; | |
| 420714aa PZ |
415 | clock-names = "di0_pll", "di1_pll", |
| 416 | "di0_sel", "di1_sel", | |
| 417 | "di0", "di1"; | |
| 418 | status = "disabled"; | |
| 419 | ||
| 420 | lvds-channel@0 { | |
| 421 | reg = <0>; | |
| 420714aa | 422 | status = "disabled"; |
| e05c8c9a PZ |
423 | |
| 424 | port { | |
| 425 | lvds0_in: endpoint { | |
| 426 | remote-endpoint = <&ipu_di0_lvds0>; | |
| 427 | }; | |
| 428 | }; | |
| 420714aa PZ |
429 | }; |
| 430 | ||
| 431 | lvds-channel@1 { | |
| 432 | reg = <1>; | |
| 420714aa | 433 | status = "disabled"; |
| e05c8c9a PZ |
434 | |
| 435 | port { | |
| 436 | lvds1_in: endpoint { | |
| fa1746ae | 437 | remote-endpoint = <&ipu_di1_lvds1>; |
| e05c8c9a PZ |
438 | }; |
| 439 | }; | |
| 420714aa PZ |
440 | }; |
| 441 | }; | |
| 442 | ||
| 9ae90afa SH |
443 | pwm1: pwm@53fb4000 { |
| 444 | #pwm-cells = <2>; | |
| 445 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
| 446 | reg = <0x53fb4000 0x4000>; | |
| 564695dd LS |
447 | clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, |
| 448 | <&clks IMX5_CLK_PWM1_HF_GATE>; | |
| 9ae90afa SH |
449 | clock-names = "ipg", "per"; |
| 450 | interrupts = <61>; | |
| 451 | }; | |
| 452 | ||
| 453 | pwm2: pwm@53fb8000 { | |
| 454 | #pwm-cells = <2>; | |
| 455 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
| 456 | reg = <0x53fb8000 0x4000>; | |
| 564695dd LS |
457 | clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, |
| 458 | <&clks IMX5_CLK_PWM2_HF_GATE>; | |
| 9ae90afa SH |
459 | clock-names = "ipg", "per"; |
| 460 | interrupts = <94>; | |
| 461 | }; | |
| 462 | ||
| 0c456cfa | 463 | uart1: serial@53fbc000 { |
| 73d2b4cd SG |
464 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 465 | reg = <0x53fbc000 0x4000>; | |
| 466 | interrupts = <31>; | |
| 564695dd LS |
467 | clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, |
| 468 | <&clks IMX5_CLK_UART1_PER_GATE>; | |
| f40f38d1 | 469 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
470 | status = "disabled"; |
| 471 | }; | |
| 472 | ||
| 0c456cfa | 473 | uart2: serial@53fc0000 { |
| 73d2b4cd SG |
474 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 475 | reg = <0x53fc0000 0x4000>; | |
| 476 | interrupts = <32>; | |
| 564695dd LS |
477 | clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, |
| 478 | <&clks IMX5_CLK_UART2_PER_GATE>; | |
| f40f38d1 | 479 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
480 | status = "disabled"; |
| 481 | }; | |
| 482 | ||
| a9d1f924 ST |
483 | can1: can@53fc8000 { |
| 484 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | |
| 485 | reg = <0x53fc8000 0x4000>; | |
| 486 | interrupts = <82>; | |
| 564695dd LS |
487 | clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, |
| 488 | <&clks IMX5_CLK_CAN1_SERIAL_GATE>; | |
| f40f38d1 | 489 | clock-names = "ipg", "per"; |
| a9d1f924 ST |
490 | status = "disabled"; |
| 491 | }; | |
| 492 | ||
| 493 | can2: can@53fcc000 { | |
| 494 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | |
| 495 | reg = <0x53fcc000 0x4000>; | |
| 496 | interrupts = <83>; | |
| 564695dd LS |
497 | clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, |
| 498 | <&clks IMX5_CLK_CAN2_SERIAL_GATE>; | |
| f40f38d1 | 499 | clock-names = "ipg", "per"; |
| a9d1f924 ST |
500 | status = "disabled"; |
| 501 | }; | |
| 502 | ||
| 8d84c374 PZ |
503 | src: src@53fd0000 { |
| 504 | compatible = "fsl,imx53-src", "fsl,imx51-src"; | |
| 505 | reg = <0x53fd0000 0x4000>; | |
| 506 | #reset-cells = <1>; | |
| 507 | }; | |
| 508 | ||
| f40f38d1 FE |
509 | clks: ccm@53fd4000{ |
| 510 | compatible = "fsl,imx53-ccm"; | |
| 511 | reg = <0x53fd4000 0x4000>; | |
| 512 | interrupts = <0 71 0x04 0 72 0x04>; | |
| 513 | #clock-cells = <1>; | |
| 514 | }; | |
| 515 | ||
| 4d191868 | 516 | gpio5: gpio@53fdc000 { |
| aeb27748 | 517 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
518 | reg = <0x53fdc000 0x4000>; |
| 519 | interrupts = <103 104>; | |
| 520 | gpio-controller; | |
| 521 | #gpio-cells = <2>; | |
| 522 | interrupt-controller; | |
| 88cde8b7 | 523 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
524 | }; |
| 525 | ||
| 4d191868 | 526 | gpio6: gpio@53fe0000 { |
| aeb27748 | 527 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
528 | reg = <0x53fe0000 0x4000>; |
| 529 | interrupts = <105 106>; | |
| 530 | gpio-controller; | |
| 531 | #gpio-cells = <2>; | |
| 532 | interrupt-controller; | |
| 88cde8b7 | 533 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
534 | }; |
| 535 | ||
| 4d191868 | 536 | gpio7: gpio@53fe4000 { |
| aeb27748 | 537 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
538 | reg = <0x53fe4000 0x4000>; |
| 539 | interrupts = <107 108>; | |
| 540 | gpio-controller; | |
| 541 | #gpio-cells = <2>; | |
| 542 | interrupt-controller; | |
| 88cde8b7 | 543 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
544 | }; |
| 545 | ||
| 7b7d6727 | 546 | i2c3: i2c@53fec000 { |
| 73d2b4cd SG |
547 | #address-cells = <1>; |
| 548 | #size-cells = <0>; | |
| 5bdfba29 | 549 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
550 | reg = <0x53fec000 0x4000>; |
| 551 | interrupts = <64>; | |
| 564695dd | 552 | clocks = <&clks IMX5_CLK_I2C3_GATE>; |
| 73d2b4cd SG |
553 | status = "disabled"; |
| 554 | }; | |
| 555 | ||
| 0c456cfa | 556 | uart4: serial@53ff0000 { |
| 73d2b4cd SG |
557 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 558 | reg = <0x53ff0000 0x4000>; | |
| 559 | interrupts = <13>; | |
| 564695dd LS |
560 | clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, |
| 561 | <&clks IMX5_CLK_UART4_PER_GATE>; | |
| f40f38d1 | 562 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
563 | status = "disabled"; |
| 564 | }; | |
| 565 | }; | |
| 566 | ||
| 567 | aips@60000000 { /* AIPS2 */ | |
| 568 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 569 | #address-cells = <1>; | |
| 570 | #size-cells = <1>; | |
| 571 | reg = <0x60000000 0x10000000>; | |
| 572 | ranges; | |
| 573 | ||
| 4f3b2a41 SH |
574 | iim: iim@63f98000 { |
| 575 | compatible = "fsl,imx53-iim", "fsl,imx27-iim"; | |
| 576 | reg = <0x63f98000 0x4000>; | |
| 577 | interrupts = <69>; | |
| 564695dd | 578 | clocks = <&clks IMX5_CLK_IIM_GATE>; |
| 4f3b2a41 SH |
579 | }; |
| 580 | ||
| 0c456cfa | 581 | uart5: serial@63f90000 { |
| 73d2b4cd SG |
582 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 583 | reg = <0x63f90000 0x4000>; | |
| 584 | interrupts = <86>; | |
| 564695dd LS |
585 | clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, |
| 586 | <&clks IMX5_CLK_UART5_PER_GATE>; | |
| f40f38d1 | 587 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
588 | status = "disabled"; |
| 589 | }; | |
| 590 | ||
| a82b7b9c MF |
591 | owire: owire@63fa4000 { |
| 592 | compatible = "fsl,imx53-owire", "fsl,imx21-owire"; | |
| 593 | reg = <0x63fa4000 0x4000>; | |
| 564695dd | 594 | clocks = <&clks IMX5_CLK_OWIRE_GATE>; |
| a82b7b9c MF |
595 | status = "disabled"; |
| 596 | }; | |
| 597 | ||
| 7b7d6727 | 598 | ecspi2: ecspi@63fac000 { |
| 73d2b4cd SG |
599 | #address-cells = <1>; |
| 600 | #size-cells = <0>; | |
| 601 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
| 602 | reg = <0x63fac000 0x4000>; | |
| 603 | interrupts = <37>; | |
| 564695dd LS |
604 | clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, |
| 605 | <&clks IMX5_CLK_ECSPI2_PER_GATE>; | |
| f40f38d1 | 606 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
607 | status = "disabled"; |
| 608 | }; | |
| 609 | ||
| 7b7d6727 | 610 | sdma: sdma@63fb0000 { |
| 73d2b4cd SG |
611 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; |
| 612 | reg = <0x63fb0000 0x4000>; | |
| 613 | interrupts = <6>; | |
| 564695dd LS |
614 | clocks = <&clks IMX5_CLK_SDMA_GATE>, |
| 615 | <&clks IMX5_CLK_SDMA_GATE>; | |
| f40f38d1 | 616 | clock-names = "ipg", "ahb"; |
| fb72bb21 | 617 | #dma-cells = <3>; |
| 7e4f0365 | 618 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; |
| 73d2b4cd SG |
619 | }; |
| 620 | ||
| 7b7d6727 | 621 | cspi: cspi@63fc0000 { |
| 73d2b4cd SG |
622 | #address-cells = <1>; |
| 623 | #size-cells = <0>; | |
| 624 | compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; | |
| 625 | reg = <0x63fc0000 0x4000>; | |
| 626 | interrupts = <38>; | |
| 564695dd LS |
627 | clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, |
| 628 | <&clks IMX5_CLK_CSPI_IPG_GATE>; | |
| f40f38d1 | 629 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
630 | status = "disabled"; |
| 631 | }; | |
| 632 | ||
| 7b7d6727 | 633 | i2c2: i2c@63fc4000 { |
| 73d2b4cd SG |
634 | #address-cells = <1>; |
| 635 | #size-cells = <0>; | |
| 5bdfba29 | 636 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
637 | reg = <0x63fc4000 0x4000>; |
| 638 | interrupts = <63>; | |
| 564695dd | 639 | clocks = <&clks IMX5_CLK_I2C2_GATE>; |
| 73d2b4cd SG |
640 | status = "disabled"; |
| 641 | }; | |
| 642 | ||
| 7b7d6727 | 643 | i2c1: i2c@63fc8000 { |
| 73d2b4cd SG |
644 | #address-cells = <1>; |
| 645 | #size-cells = <0>; | |
| 5bdfba29 | 646 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
647 | reg = <0x63fc8000 0x4000>; |
| 648 | interrupts = <62>; | |
| 564695dd | 649 | clocks = <&clks IMX5_CLK_I2C1_GATE>; |
| 73d2b4cd SG |
650 | status = "disabled"; |
| 651 | }; | |
| 652 | ||
| ffc505c0 | 653 | ssi1: ssi@63fcc000 { |
| 28f93d0b MP |
654 | compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", |
| 655 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
656 | reg = <0x63fcc000 0x4000>; |
| 657 | interrupts = <29>; | |
| 564695dd | 658 | clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; |
| 5da826ab SG |
659 | dmas = <&sdma 28 0 0>, |
| 660 | <&sdma 29 0 0>; | |
| 661 | dma-names = "rx", "tx"; | |
| ffc505c0 SG |
662 | fsl,fifo-depth = <15>; |
| 663 | fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ | |
| 664 | status = "disabled"; | |
| 665 | }; | |
| 666 | ||
| 7b7d6727 | 667 | audmux: audmux@63fd0000 { |
| ffc505c0 SG |
668 | compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; |
| 669 | reg = <0x63fd0000 0x4000>; | |
| 670 | status = "disabled"; | |
| 671 | }; | |
| 672 | ||
| 7b7d6727 | 673 | nfc: nand@63fdb000 { |
| 75453a08 SH |
674 | compatible = "fsl,imx53-nand"; |
| 675 | reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; | |
| 676 | interrupts = <8>; | |
| 564695dd | 677 | clocks = <&clks IMX5_CLK_NFC_GATE>; |
| 75453a08 SH |
678 | status = "disabled"; |
| 679 | }; | |
| 680 | ||
| ffc505c0 | 681 | ssi3: ssi@63fe8000 { |
| 28f93d0b MP |
682 | compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", |
| 683 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
684 | reg = <0x63fe8000 0x4000>; |
| 685 | interrupts = <96>; | |
| 564695dd | 686 | clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; |
| 5da826ab SG |
687 | dmas = <&sdma 46 0 0>, |
| 688 | <&sdma 47 0 0>; | |
| 689 | dma-names = "rx", "tx"; | |
| ffc505c0 SG |
690 | fsl,fifo-depth = <15>; |
| 691 | fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */ | |
| 692 | status = "disabled"; | |
| 693 | }; | |
| 694 | ||
| 7b7d6727 | 695 | fec: ethernet@63fec000 { |
| 73d2b4cd SG |
696 | compatible = "fsl,imx53-fec", "fsl,imx25-fec"; |
| 697 | reg = <0x63fec000 0x4000>; | |
| 698 | interrupts = <87>; | |
| 564695dd LS |
699 | clocks = <&clks IMX5_CLK_FEC_GATE>, |
| 700 | <&clks IMX5_CLK_FEC_GATE>, | |
| 701 | <&clks IMX5_CLK_FEC_GATE>; | |
| f40f38d1 | 702 | clock-names = "ipg", "ahb", "ptp"; |
| 73d2b4cd SG |
703 | status = "disabled"; |
| 704 | }; | |
| 19194c2b PZ |
705 | |
| 706 | tve: tve@63ff0000 { | |
| 707 | compatible = "fsl,imx53-tve"; | |
| 708 | reg = <0x63ff0000 0x1000>; | |
| 709 | interrupts = <92>; | |
| 564695dd LS |
710 | clocks = <&clks IMX5_CLK_TVE_GATE>, |
| 711 | <&clks IMX5_CLK_IPU_DI1_SEL>; | |
| 19194c2b | 712 | clock-names = "tve", "di_sel"; |
| 19194c2b | 713 | status = "disabled"; |
| e05c8c9a PZ |
714 | |
| 715 | port { | |
| 716 | tve_in: endpoint { | |
| 717 | remote-endpoint = <&ipu_di1_tve>; | |
| 718 | }; | |
| 719 | }; | |
| 19194c2b | 720 | }; |
| fbf970f6 FE |
721 | |
| 722 | vpu: vpu@63ff4000 { | |
| 723 | compatible = "fsl,imx53-vpu"; | |
| 724 | reg = <0x63ff4000 0x1000>; | |
| 725 | interrupts = <9>; | |
| 564695dd LS |
726 | clocks = <&clks IMX5_CLK_VPU_GATE>, |
| 727 | <&clks IMX5_CLK_VPU_GATE>; | |
| fbf970f6 FE |
728 | clock-names = "per", "ahb"; |
| 729 | iram = <&ocram>; | |
| 730 | status = "disabled"; | |
| 731 | }; | |
| 73d2b4cd | 732 | }; |
| 481fbe13 PZ |
733 | |
| 734 | ocram: sram@f8000000 { | |
| 735 | compatible = "mmio-sram"; | |
| 736 | reg = <0xf8000000 0x20000>; | |
| 564695dd | 737 | clocks = <&clks IMX5_CLK_OCRAM>; |
| 481fbe13 | 738 | }; |
| 73d2b4cd SG |
739 | }; |
| 740 | }; |