projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 73d2b4cd SG |
1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
| 3 | * Copyright 2011 Linaro Ltd. | |
| 4 | * | |
| 5 | * The code contained herein is licensed under the GNU General Public | |
| 6 | * License. You may obtain a copy of the GNU General Public License | |
| 7 | * Version 2 or later at the following locations: | |
| 8 | * | |
| 9 | * http://www.opensource.org/licenses/gpl-license.html | |
| 10 | * http://www.gnu.org/copyleft/gpl.html | |
| 11 | */ | |
| 12 | ||
| 36dffd8f | 13 | #include "skeleton.dtsi" |
| e1641531 | 14 | #include "imx53-pinfunc.h" |
| 564695dd | 15 | #include <dt-bindings/clock/imx5-clock.h> |
| 4e05a7af DC |
16 | #include <dt-bindings/gpio/gpio.h> |
| 17 | #include <dt-bindings/input/input.h> | |
| 73d2b4cd SG |
18 | |
| 19 | / { | |
| 20 | aliases { | |
| 22970070 | 21 | ethernet0 = &fec; |
| 5230f8fe SG |
22 | gpio0 = &gpio1; |
| 23 | gpio1 = &gpio2; | |
| 24 | gpio2 = &gpio3; | |
| 25 | gpio3 = &gpio4; | |
| 26 | gpio4 = &gpio5; | |
| 27 | gpio5 = &gpio6; | |
| 28 | gpio6 = &gpio7; | |
| c60dc1d1 PZ |
29 | i2c0 = &i2c1; |
| 30 | i2c1 = &i2c2; | |
| 31 | i2c2 = &i2c3; | |
| c63d06de SH |
32 | mmc0 = &esdhc1; |
| 33 | mmc1 = &esdhc2; | |
| 34 | mmc2 = &esdhc3; | |
| 35 | mmc3 = &esdhc4; | |
| cf4e577e SH |
36 | serial0 = &uart1; |
| 37 | serial1 = &uart2; | |
| 38 | serial2 = &uart3; | |
| 39 | serial3 = &uart4; | |
| 40 | serial4 = &uart5; | |
| 41 | spi0 = &ecspi1; | |
| 42 | spi1 = &ecspi2; | |
| 43 | spi2 = &cspi; | |
| 73d2b4cd SG |
44 | }; |
| 45 | ||
| 070bd7e4 FE |
46 | cpus { |
| 47 | #address-cells = <1>; | |
| 48 | #size-cells = <0>; | |
| 791f4166 | 49 | cpu0: cpu@0 { |
| 070bd7e4 FE |
50 | device_type = "cpu"; |
| 51 | compatible = "arm,cortex-a8"; | |
| 52 | reg = <0x0>; | |
| 791f4166 LS |
53 | clocks = <&clks IMX5_CLK_ARM>; |
| 54 | clock-latency = <61036>; | |
| 55 | voltage-tolerance = <5>; | |
| 56 | operating-points = < | |
| 57 | /* kHz */ | |
| 58 | 166666 850000 | |
| 59 | 400000 900000 | |
| 60 | 800000 1050000 | |
| 61 | 1000000 1200000 | |
| 62 | 1200000 1300000 | |
| 63 | >; | |
| 070bd7e4 FE |
64 | }; |
| 65 | }; | |
| 66 | ||
| e05c8c9a PZ |
67 | display-subsystem { |
| 68 | compatible = "fsl,imx-display-subsystem"; | |
| 69 | ports = <&ipu_di0>, <&ipu_di1>; | |
| 70 | }; | |
| 71 | ||
| 73d2b4cd SG |
72 | tzic: tz-interrupt-controller@0fffc000 { |
| 73 | compatible = "fsl,imx53-tzic", "fsl,tzic"; | |
| 74 | interrupt-controller; | |
| 75 | #interrupt-cells = <1>; | |
| 76 | reg = <0x0fffc000 0x4000>; | |
| 77 | }; | |
| 78 | ||
| 79 | clocks { | |
| 80 | #address-cells = <1>; | |
| 81 | #size-cells = <0>; | |
| 82 | ||
| 83 | ckil { | |
| 84 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
| 4b2b4043 | 85 | #clock-cells = <0>; |
| 73d2b4cd SG |
86 | clock-frequency = <32768>; |
| 87 | }; | |
| 88 | ||
| 89 | ckih1 { | |
| 90 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
| 4b2b4043 | 91 | #clock-cells = <0>; |
| 73d2b4cd SG |
92 | clock-frequency = <22579200>; |
| 93 | }; | |
| 94 | ||
| 95 | ckih2 { | |
| 96 | compatible = "fsl,imx-ckih2", "fixed-clock"; | |
| 4b2b4043 | 97 | #clock-cells = <0>; |
| 73d2b4cd SG |
98 | clock-frequency = <0>; |
| 99 | }; | |
| 100 | ||
| 101 | osc { | |
| 102 | compatible = "fsl,imx-osc", "fixed-clock"; | |
| 4b2b4043 | 103 | #clock-cells = <0>; |
| 73d2b4cd SG |
104 | clock-frequency = <24000000>; |
| 105 | }; | |
| 106 | }; | |
| 107 | ||
| 108 | soc { | |
| 109 | #address-cells = <1>; | |
| 110 | #size-cells = <1>; | |
| 111 | compatible = "simple-bus"; | |
| 112 | interrupt-parent = <&tzic>; | |
| 113 | ranges; | |
| 114 | ||
| 7affee43 MV |
115 | sata: sata@10000000 { |
| 116 | compatible = "fsl,imx53-ahci"; | |
| 117 | reg = <0x10000000 0x1000>; | |
| 118 | interrupts = <28>; | |
| 119 | clocks = <&clks IMX5_CLK_SATA_GATE>, | |
| 120 | <&clks IMX5_CLK_SATA_REF>, | |
| 121 | <&clks IMX5_CLK_AHB>; | |
| 02578153 | 122 | clock-names = "sata", "sata_ref", "ahb"; |
| 7affee43 MV |
123 | status = "disabled"; |
| 124 | }; | |
| 125 | ||
| abed9a6b | 126 | ipu: ipu@18000000 { |
| e05c8c9a PZ |
127 | #address-cells = <1>; |
| 128 | #size-cells = <0>; | |
| abed9a6b | 129 | compatible = "fsl,imx53-ipu"; |
| 6d66da89 | 130 | reg = <0x18000000 0x08000000>; |
| abed9a6b | 131 | interrupts = <11 10>; |
| 564695dd LS |
132 | clocks = <&clks IMX5_CLK_IPU_GATE>, |
| 133 | <&clks IMX5_CLK_IPU_DI0_GATE>, | |
| 134 | <&clks IMX5_CLK_IPU_DI1_GATE>; | |
| 4438a6a1 | 135 | clock-names = "bus", "di0", "di1"; |
| 8d84c374 | 136 | resets = <&src 2>; |
| e05c8c9a PZ |
137 | |
| 138 | ipu_di0: port@2 { | |
| 139 | #address-cells = <1>; | |
| 140 | #size-cells = <0>; | |
| 141 | reg = <2>; | |
| 142 | ||
| 143 | ipu_di0_disp0: endpoint@0 { | |
| 144 | reg = <0>; | |
| 145 | }; | |
| 146 | ||
| 147 | ipu_di0_lvds0: endpoint@1 { | |
| 148 | reg = <1>; | |
| 149 | remote-endpoint = <&lvds0_in>; | |
| 150 | }; | |
| 151 | }; | |
| 152 | ||
| 153 | ipu_di1: port@3 { | |
| 154 | #address-cells = <1>; | |
| 155 | #size-cells = <0>; | |
| 156 | reg = <3>; | |
| 157 | ||
| 158 | ipu_di1_disp1: endpoint@0 { | |
| 159 | reg = <0>; | |
| 160 | }; | |
| 161 | ||
| 162 | ipu_di1_lvds1: endpoint@1 { | |
| 163 | reg = <1>; | |
| 164 | remote-endpoint = <&lvds1_in>; | |
| 165 | }; | |
| 166 | ||
| 167 | ipu_di1_tve: endpoint@2 { | |
| 168 | reg = <2>; | |
| 169 | remote-endpoint = <&tve_in>; | |
| 170 | }; | |
| 171 | }; | |
| abed9a6b SH |
172 | }; |
| 173 | ||
| 73d2b4cd SG |
174 | aips@50000000 { /* AIPS1 */ |
| 175 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 176 | #address-cells = <1>; | |
| 177 | #size-cells = <1>; | |
| 178 | reg = <0x50000000 0x10000000>; | |
| 179 | ranges; | |
| 180 | ||
| 181 | spba@50000000 { | |
| 182 | compatible = "fsl,spba-bus", "simple-bus"; | |
| 183 | #address-cells = <1>; | |
| 184 | #size-cells = <1>; | |
| 185 | reg = <0x50000000 0x40000>; | |
| 186 | ranges; | |
| 187 | ||
| 7b7d6727 | 188 | esdhc1: esdhc@50004000 { |
| 73d2b4cd SG |
189 | compatible = "fsl,imx53-esdhc"; |
| 190 | reg = <0x50004000 0x4000>; | |
| 191 | interrupts = <1>; | |
| 564695dd LS |
192 | clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, |
| 193 | <&clks IMX5_CLK_DUMMY>, | |
| 194 | <&clks IMX5_CLK_ESDHC1_PER_GATE>; | |
| f40f38d1 | 195 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 196 | bus-width = <4>; |
| 73d2b4cd SG |
197 | status = "disabled"; |
| 198 | }; | |
| 199 | ||
| 7b7d6727 | 200 | esdhc2: esdhc@50008000 { |
| 73d2b4cd SG |
201 | compatible = "fsl,imx53-esdhc"; |
| 202 | reg = <0x50008000 0x4000>; | |
| 203 | interrupts = <2>; | |
| 564695dd LS |
204 | clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, |
| 205 | <&clks IMX5_CLK_DUMMY>, | |
| 206 | <&clks IMX5_CLK_ESDHC2_PER_GATE>; | |
| f40f38d1 | 207 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 208 | bus-width = <4>; |
| 73d2b4cd SG |
209 | status = "disabled"; |
| 210 | }; | |
| 211 | ||
| 0c456cfa | 212 | uart3: serial@5000c000 { |
| 73d2b4cd SG |
213 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 214 | reg = <0x5000c000 0x4000>; | |
| 215 | interrupts = <33>; | |
| 564695dd LS |
216 | clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, |
| 217 | <&clks IMX5_CLK_UART3_PER_GATE>; | |
| f40f38d1 | 218 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
219 | status = "disabled"; |
| 220 | }; | |
| 221 | ||
| 7b7d6727 | 222 | ecspi1: ecspi@50010000 { |
| 73d2b4cd SG |
223 | #address-cells = <1>; |
| 224 | #size-cells = <0>; | |
| 225 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
| 226 | reg = <0x50010000 0x4000>; | |
| 227 | interrupts = <36>; | |
| 564695dd LS |
228 | clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, |
| 229 | <&clks IMX5_CLK_ECSPI1_PER_GATE>; | |
| f40f38d1 | 230 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
231 | status = "disabled"; |
| 232 | }; | |
| 233 | ||
| ffc505c0 | 234 | ssi2: ssi@50014000 { |
| 6ff7f51e | 235 | #sound-dai-cells = <0>; |
| 28f93d0b MP |
236 | compatible = "fsl,imx53-ssi", |
| 237 | "fsl,imx51-ssi", | |
| 238 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
239 | reg = <0x50014000 0x4000>; |
| 240 | interrupts = <30>; | |
| 685570ab FE |
241 | clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, |
| 242 | <&clks IMX5_CLK_SSI2_ROOT_GATE>; | |
| 243 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
244 | dmas = <&sdma 24 1 0>, |
| 245 | <&sdma 25 1 0>; | |
| 246 | dma-names = "rx", "tx"; | |
| ffc505c0 | 247 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
248 | status = "disabled"; |
| 249 | }; | |
| 250 | ||
| 7b7d6727 | 251 | esdhc3: esdhc@50020000 { |
| 73d2b4cd SG |
252 | compatible = "fsl,imx53-esdhc"; |
| 253 | reg = <0x50020000 0x4000>; | |
| 254 | interrupts = <3>; | |
| 564695dd LS |
255 | clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, |
| 256 | <&clks IMX5_CLK_DUMMY>, | |
| 257 | <&clks IMX5_CLK_ESDHC3_PER_GATE>; | |
| f40f38d1 | 258 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 259 | bus-width = <4>; |
| 73d2b4cd SG |
260 | status = "disabled"; |
| 261 | }; | |
| 262 | ||
| 7b7d6727 | 263 | esdhc4: esdhc@50024000 { |
| 73d2b4cd SG |
264 | compatible = "fsl,imx53-esdhc"; |
| 265 | reg = <0x50024000 0x4000>; | |
| 266 | interrupts = <4>; | |
| 564695dd LS |
267 | clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, |
| 268 | <&clks IMX5_CLK_DUMMY>, | |
| 269 | <&clks IMX5_CLK_ESDHC4_PER_GATE>; | |
| f40f38d1 | 270 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 271 | bus-width = <4>; |
| 73d2b4cd SG |
272 | status = "disabled"; |
| 273 | }; | |
| 274 | }; | |
| 275 | ||
| ac08281e ST |
276 | aipstz1: bridge@53f00000 { |
| 277 | compatible = "fsl,imx53-aipstz"; | |
| 278 | reg = <0x53f00000 0x60>; | |
| 279 | }; | |
| 280 | ||
| a79025c4 MG |
281 | usbphy0: usbphy@0 { |
| 282 | compatible = "usb-nop-xceiv"; | |
| 564695dd | 283 | clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; |
| a79025c4 MG |
284 | clock-names = "main_clk"; |
| 285 | status = "okay"; | |
| 286 | }; | |
| 287 | ||
| 288 | usbphy1: usbphy@1 { | |
| 289 | compatible = "usb-nop-xceiv"; | |
| 564695dd | 290 | clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; |
| a79025c4 MG |
291 | clock-names = "main_clk"; |
| 292 | status = "okay"; | |
| 293 | }; | |
| 294 | ||
| 7b7d6727 | 295 | usbotg: usb@53f80000 { |
| 212d0b83 MG |
296 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 297 | reg = <0x53f80000 0x0200>; | |
| 298 | interrupts = <18>; | |
| 564695dd | 299 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 300 | fsl,usbmisc = <&usbmisc 0>; |
| a79025c4 | 301 | fsl,usbphy = <&usbphy0>; |
| 212d0b83 MG |
302 | status = "disabled"; |
| 303 | }; | |
| 304 | ||
| 7b7d6727 | 305 | usbh1: usb@53f80200 { |
| 212d0b83 MG |
306 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 307 | reg = <0x53f80200 0x0200>; | |
| 308 | interrupts = <14>; | |
| 564695dd | 309 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 310 | fsl,usbmisc = <&usbmisc 1>; |
| a79025c4 | 311 | fsl,usbphy = <&usbphy1>; |
| 3ec481ed | 312 | dr_mode = "host"; |
| 212d0b83 MG |
313 | status = "disabled"; |
| 314 | }; | |
| 315 | ||
| 7b7d6727 | 316 | usbh2: usb@53f80400 { |
| 212d0b83 MG |
317 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 318 | reg = <0x53f80400 0x0200>; | |
| 319 | interrupts = <16>; | |
| 564695dd | 320 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 321 | fsl,usbmisc = <&usbmisc 2>; |
| 3ec481ed | 322 | dr_mode = "host"; |
| 212d0b83 MG |
323 | status = "disabled"; |
| 324 | }; | |
| 325 | ||
| 7b7d6727 | 326 | usbh3: usb@53f80600 { |
| 212d0b83 MG |
327 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 328 | reg = <0x53f80600 0x0200>; | |
| 329 | interrupts = <17>; | |
| 564695dd | 330 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 331 | fsl,usbmisc = <&usbmisc 3>; |
| 3ec481ed | 332 | dr_mode = "host"; |
| 212d0b83 MG |
333 | status = "disabled"; |
| 334 | }; | |
| 335 | ||
| a5735021 MG |
336 | usbmisc: usbmisc@53f80800 { |
| 337 | #index-cells = <1>; | |
| 338 | compatible = "fsl,imx53-usbmisc"; | |
| 339 | reg = <0x53f80800 0x200>; | |
| 564695dd | 340 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 MG |
341 | }; |
| 342 | ||
| 4d191868 | 343 | gpio1: gpio@53f84000 { |
| aeb27748 | 344 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
345 | reg = <0x53f84000 0x4000>; |
| 346 | interrupts = <50 51>; | |
| 347 | gpio-controller; | |
| 348 | #gpio-cells = <2>; | |
| 349 | interrupt-controller; | |
| 88cde8b7 | 350 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
351 | }; |
| 352 | ||
| 4d191868 | 353 | gpio2: gpio@53f88000 { |
| aeb27748 | 354 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
355 | reg = <0x53f88000 0x4000>; |
| 356 | interrupts = <52 53>; | |
| 357 | gpio-controller; | |
| 358 | #gpio-cells = <2>; | |
| 359 | interrupt-controller; | |
| 88cde8b7 | 360 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
361 | }; |
| 362 | ||
| 4d191868 | 363 | gpio3: gpio@53f8c000 { |
| aeb27748 | 364 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
365 | reg = <0x53f8c000 0x4000>; |
| 366 | interrupts = <54 55>; | |
| 367 | gpio-controller; | |
| 368 | #gpio-cells = <2>; | |
| 369 | interrupt-controller; | |
| 88cde8b7 | 370 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
371 | }; |
| 372 | ||
| 4d191868 | 373 | gpio4: gpio@53f90000 { |
| aeb27748 | 374 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
375 | reg = <0x53f90000 0x4000>; |
| 376 | interrupts = <56 57>; | |
| 377 | gpio-controller; | |
| 378 | #gpio-cells = <2>; | |
| 379 | interrupt-controller; | |
| 88cde8b7 | 380 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
381 | }; |
| 382 | ||
| 675e4d03 RL |
383 | kpp: kpp@53f94000 { |
| 384 | compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; | |
| 385 | reg = <0x53f94000 0x4000>; | |
| 386 | interrupts = <60>; | |
| 564695dd | 387 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 675e4d03 RL |
388 | status = "disabled"; |
| 389 | }; | |
| 390 | ||
| 7b7d6727 | 391 | wdog1: wdog@53f98000 { |
| 73d2b4cd SG |
392 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 393 | reg = <0x53f98000 0x4000>; | |
| 394 | interrupts = <58>; | |
| 564695dd | 395 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 73d2b4cd SG |
396 | }; |
| 397 | ||
| 7b7d6727 | 398 | wdog2: wdog@53f9c000 { |
| 73d2b4cd SG |
399 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 400 | reg = <0x53f9c000 0x4000>; | |
| 401 | interrupts = <59>; | |
| 564695dd | 402 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 73d2b4cd SG |
403 | status = "disabled"; |
| 404 | }; | |
| 405 | ||
| cc8aae9b SH |
406 | gpt: timer@53fa0000 { |
| 407 | compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; | |
| 408 | reg = <0x53fa0000 0x4000>; | |
| 409 | interrupts = <39>; | |
| 564695dd LS |
410 | clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, |
| 411 | <&clks IMX5_CLK_GPT_HF_GATE>; | |
| cc8aae9b SH |
412 | clock-names = "ipg", "per"; |
| 413 | }; | |
| 414 | ||
| 7b7d6727 | 415 | iomuxc: iomuxc@53fa8000 { |
| 5be03a7b SG |
416 | compatible = "fsl,imx53-iomuxc"; |
| 417 | reg = <0x53fa8000 0x4000>; | |
| 5be03a7b SG |
418 | }; |
| 419 | ||
| 5af9f143 PZ |
420 | gpr: iomuxc-gpr@53fa8000 { |
| 421 | compatible = "fsl,imx53-iomuxc-gpr", "syscon"; | |
| 422 | reg = <0x53fa8000 0xc>; | |
| 423 | }; | |
| 424 | ||
| 420714aa PZ |
425 | ldb: ldb@53fa8008 { |
| 426 | #address-cells = <1>; | |
| 427 | #size-cells = <0>; | |
| 428 | compatible = "fsl,imx53-ldb"; | |
| 429 | reg = <0x53fa8008 0x4>; | |
| 430 | gpr = <&gpr>; | |
| 564695dd LS |
431 | clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, |
| 432 | <&clks IMX5_CLK_LDB_DI1_SEL>, | |
| 433 | <&clks IMX5_CLK_IPU_DI0_SEL>, | |
| 434 | <&clks IMX5_CLK_IPU_DI1_SEL>, | |
| 435 | <&clks IMX5_CLK_LDB_DI0_GATE>, | |
| 436 | <&clks IMX5_CLK_LDB_DI1_GATE>; | |
| 420714aa PZ |
437 | clock-names = "di0_pll", "di1_pll", |
| 438 | "di0_sel", "di1_sel", | |
| 439 | "di0", "di1"; | |
| 440 | status = "disabled"; | |
| 441 | ||
| 442 | lvds-channel@0 { | |
| 1b134c9c MN |
443 | #address-cells = <1>; |
| 444 | #size-cells = <0>; | |
| 420714aa | 445 | reg = <0>; |
| 420714aa | 446 | status = "disabled"; |
| e05c8c9a | 447 | |
| 1b134c9c MN |
448 | port@0 { |
| 449 | reg = <0>; | |
| 450 | ||
| e05c8c9a PZ |
451 | lvds0_in: endpoint { |
| 452 | remote-endpoint = <&ipu_di0_lvds0>; | |
| 453 | }; | |
| 454 | }; | |
| 420714aa PZ |
455 | }; |
| 456 | ||
| 457 | lvds-channel@1 { | |
| 1b134c9c MN |
458 | #address-cells = <1>; |
| 459 | #size-cells = <0>; | |
| 420714aa | 460 | reg = <1>; |
| 420714aa | 461 | status = "disabled"; |
| e05c8c9a | 462 | |
| 1b134c9c MN |
463 | port@1 { |
| 464 | reg = <1>; | |
| 465 | ||
| e05c8c9a | 466 | lvds1_in: endpoint { |
| fa1746ae | 467 | remote-endpoint = <&ipu_di1_lvds1>; |
| e05c8c9a PZ |
468 | }; |
| 469 | }; | |
| 420714aa PZ |
470 | }; |
| 471 | }; | |
| 472 | ||
| 9ae90afa SH |
473 | pwm1: pwm@53fb4000 { |
| 474 | #pwm-cells = <2>; | |
| 475 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
| 476 | reg = <0x53fb4000 0x4000>; | |
| 564695dd LS |
477 | clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, |
| 478 | <&clks IMX5_CLK_PWM1_HF_GATE>; | |
| 9ae90afa SH |
479 | clock-names = "ipg", "per"; |
| 480 | interrupts = <61>; | |
| 481 | }; | |
| 482 | ||
| 483 | pwm2: pwm@53fb8000 { | |
| 484 | #pwm-cells = <2>; | |
| 485 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
| 486 | reg = <0x53fb8000 0x4000>; | |
| 564695dd LS |
487 | clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, |
| 488 | <&clks IMX5_CLK_PWM2_HF_GATE>; | |
| 9ae90afa SH |
489 | clock-names = "ipg", "per"; |
| 490 | interrupts = <94>; | |
| 491 | }; | |
| 492 | ||
| 0c456cfa | 493 | uart1: serial@53fbc000 { |
| 73d2b4cd SG |
494 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 495 | reg = <0x53fbc000 0x4000>; | |
| 496 | interrupts = <31>; | |
| 564695dd LS |
497 | clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, |
| 498 | <&clks IMX5_CLK_UART1_PER_GATE>; | |
| f40f38d1 | 499 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
500 | status = "disabled"; |
| 501 | }; | |
| 502 | ||
| 0c456cfa | 503 | uart2: serial@53fc0000 { |
| 73d2b4cd SG |
504 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 505 | reg = <0x53fc0000 0x4000>; | |
| 506 | interrupts = <32>; | |
| 564695dd LS |
507 | clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, |
| 508 | <&clks IMX5_CLK_UART2_PER_GATE>; | |
| f40f38d1 | 509 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
510 | status = "disabled"; |
| 511 | }; | |
| 512 | ||
| a9d1f924 ST |
513 | can1: can@53fc8000 { |
| 514 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | |
| 515 | reg = <0x53fc8000 0x4000>; | |
| 516 | interrupts = <82>; | |
| 564695dd LS |
517 | clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, |
| 518 | <&clks IMX5_CLK_CAN1_SERIAL_GATE>; | |
| f40f38d1 | 519 | clock-names = "ipg", "per"; |
| a9d1f924 ST |
520 | status = "disabled"; |
| 521 | }; | |
| 522 | ||
| 523 | can2: can@53fcc000 { | |
| 524 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | |
| 525 | reg = <0x53fcc000 0x4000>; | |
| 526 | interrupts = <83>; | |
| 564695dd LS |
527 | clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, |
| 528 | <&clks IMX5_CLK_CAN2_SERIAL_GATE>; | |
| f40f38d1 | 529 | clock-names = "ipg", "per"; |
| a9d1f924 ST |
530 | status = "disabled"; |
| 531 | }; | |
| 532 | ||
| 8d84c374 PZ |
533 | src: src@53fd0000 { |
| 534 | compatible = "fsl,imx53-src", "fsl,imx51-src"; | |
| 535 | reg = <0x53fd0000 0x4000>; | |
| 536 | #reset-cells = <1>; | |
| 537 | }; | |
| 538 | ||
| f40f38d1 FE |
539 | clks: ccm@53fd4000{ |
| 540 | compatible = "fsl,imx53-ccm"; | |
| 541 | reg = <0x53fd4000 0x4000>; | |
| 542 | interrupts = <0 71 0x04 0 72 0x04>; | |
| 543 | #clock-cells = <1>; | |
| 544 | }; | |
| 545 | ||
| 4d191868 | 546 | gpio5: gpio@53fdc000 { |
| aeb27748 | 547 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
548 | reg = <0x53fdc000 0x4000>; |
| 549 | interrupts = <103 104>; | |
| 550 | gpio-controller; | |
| 551 | #gpio-cells = <2>; | |
| 552 | interrupt-controller; | |
| 88cde8b7 | 553 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
554 | }; |
| 555 | ||
| 4d191868 | 556 | gpio6: gpio@53fe0000 { |
| aeb27748 | 557 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
558 | reg = <0x53fe0000 0x4000>; |
| 559 | interrupts = <105 106>; | |
| 560 | gpio-controller; | |
| 561 | #gpio-cells = <2>; | |
| 562 | interrupt-controller; | |
| 88cde8b7 | 563 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
564 | }; |
| 565 | ||
| 4d191868 | 566 | gpio7: gpio@53fe4000 { |
| aeb27748 | 567 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
568 | reg = <0x53fe4000 0x4000>; |
| 569 | interrupts = <107 108>; | |
| 570 | gpio-controller; | |
| 571 | #gpio-cells = <2>; | |
| 572 | interrupt-controller; | |
| 88cde8b7 | 573 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
574 | }; |
| 575 | ||
| 7b7d6727 | 576 | i2c3: i2c@53fec000 { |
| 73d2b4cd SG |
577 | #address-cells = <1>; |
| 578 | #size-cells = <0>; | |
| 5bdfba29 | 579 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
580 | reg = <0x53fec000 0x4000>; |
| 581 | interrupts = <64>; | |
| 564695dd | 582 | clocks = <&clks IMX5_CLK_I2C3_GATE>; |
| 73d2b4cd SG |
583 | status = "disabled"; |
| 584 | }; | |
| 585 | ||
| 0c456cfa | 586 | uart4: serial@53ff0000 { |
| 73d2b4cd SG |
587 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 588 | reg = <0x53ff0000 0x4000>; | |
| 589 | interrupts = <13>; | |
| 564695dd LS |
590 | clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, |
| 591 | <&clks IMX5_CLK_UART4_PER_GATE>; | |
| f40f38d1 | 592 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
593 | status = "disabled"; |
| 594 | }; | |
| 595 | }; | |
| 596 | ||
| 597 | aips@60000000 { /* AIPS2 */ | |
| 598 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 599 | #address-cells = <1>; | |
| 600 | #size-cells = <1>; | |
| 601 | reg = <0x60000000 0x10000000>; | |
| 602 | ranges; | |
| 603 | ||
| ac08281e ST |
604 | aipstz2: bridge@63f00000 { |
| 605 | compatible = "fsl,imx53-aipstz"; | |
| 606 | reg = <0x63f00000 0x60>; | |
| 607 | }; | |
| 608 | ||
| 4f3b2a41 SH |
609 | iim: iim@63f98000 { |
| 610 | compatible = "fsl,imx53-iim", "fsl,imx27-iim"; | |
| 611 | reg = <0x63f98000 0x4000>; | |
| 612 | interrupts = <69>; | |
| 564695dd | 613 | clocks = <&clks IMX5_CLK_IIM_GATE>; |
| 4f3b2a41 SH |
614 | }; |
| 615 | ||
| 0c456cfa | 616 | uart5: serial@63f90000 { |
| 73d2b4cd SG |
617 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 618 | reg = <0x63f90000 0x4000>; | |
| 619 | interrupts = <86>; | |
| 564695dd LS |
620 | clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, |
| 621 | <&clks IMX5_CLK_UART5_PER_GATE>; | |
| f40f38d1 | 622 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
623 | status = "disabled"; |
| 624 | }; | |
| 625 | ||
| a82b7b9c MF |
626 | owire: owire@63fa4000 { |
| 627 | compatible = "fsl,imx53-owire", "fsl,imx21-owire"; | |
| 628 | reg = <0x63fa4000 0x4000>; | |
| 564695dd | 629 | clocks = <&clks IMX5_CLK_OWIRE_GATE>; |
| a82b7b9c MF |
630 | status = "disabled"; |
| 631 | }; | |
| 632 | ||
| 7b7d6727 | 633 | ecspi2: ecspi@63fac000 { |
| 73d2b4cd SG |
634 | #address-cells = <1>; |
| 635 | #size-cells = <0>; | |
| 636 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
| 637 | reg = <0x63fac000 0x4000>; | |
| 638 | interrupts = <37>; | |
| 564695dd LS |
639 | clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, |
| 640 | <&clks IMX5_CLK_ECSPI2_PER_GATE>; | |
| f40f38d1 | 641 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
642 | status = "disabled"; |
| 643 | }; | |
| 644 | ||
| 7b7d6727 | 645 | sdma: sdma@63fb0000 { |
| 73d2b4cd SG |
646 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; |
| 647 | reg = <0x63fb0000 0x4000>; | |
| 648 | interrupts = <6>; | |
| 564695dd LS |
649 | clocks = <&clks IMX5_CLK_SDMA_GATE>, |
| 650 | <&clks IMX5_CLK_SDMA_GATE>; | |
| f40f38d1 | 651 | clock-names = "ipg", "ahb"; |
| fb72bb21 | 652 | #dma-cells = <3>; |
| 7e4f0365 | 653 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; |
| 73d2b4cd SG |
654 | }; |
| 655 | ||
| 7b7d6727 | 656 | cspi: cspi@63fc0000 { |
| 73d2b4cd SG |
657 | #address-cells = <1>; |
| 658 | #size-cells = <0>; | |
| 659 | compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; | |
| 660 | reg = <0x63fc0000 0x4000>; | |
| 661 | interrupts = <38>; | |
| 564695dd LS |
662 | clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, |
| 663 | <&clks IMX5_CLK_CSPI_IPG_GATE>; | |
| f40f38d1 | 664 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
665 | status = "disabled"; |
| 666 | }; | |
| 667 | ||
| 7b7d6727 | 668 | i2c2: i2c@63fc4000 { |
| 73d2b4cd SG |
669 | #address-cells = <1>; |
| 670 | #size-cells = <0>; | |
| 5bdfba29 | 671 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
672 | reg = <0x63fc4000 0x4000>; |
| 673 | interrupts = <63>; | |
| 564695dd | 674 | clocks = <&clks IMX5_CLK_I2C2_GATE>; |
| 73d2b4cd SG |
675 | status = "disabled"; |
| 676 | }; | |
| 677 | ||
| 7b7d6727 | 678 | i2c1: i2c@63fc8000 { |
| 73d2b4cd SG |
679 | #address-cells = <1>; |
| 680 | #size-cells = <0>; | |
| 5bdfba29 | 681 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
682 | reg = <0x63fc8000 0x4000>; |
| 683 | interrupts = <62>; | |
| 564695dd | 684 | clocks = <&clks IMX5_CLK_I2C1_GATE>; |
| 73d2b4cd SG |
685 | status = "disabled"; |
| 686 | }; | |
| 687 | ||
| ffc505c0 | 688 | ssi1: ssi@63fcc000 { |
| 6ff7f51e | 689 | #sound-dai-cells = <0>; |
| 28f93d0b MP |
690 | compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", |
| 691 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
692 | reg = <0x63fcc000 0x4000>; |
| 693 | interrupts = <29>; | |
| 685570ab FE |
694 | clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, |
| 695 | <&clks IMX5_CLK_SSI1_ROOT_GATE>; | |
| 696 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
697 | dmas = <&sdma 28 0 0>, |
| 698 | <&sdma 29 0 0>; | |
| 699 | dma-names = "rx", "tx"; | |
| ffc505c0 | 700 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
701 | status = "disabled"; |
| 702 | }; | |
| 703 | ||
| 7b7d6727 | 704 | audmux: audmux@63fd0000 { |
| ffc505c0 SG |
705 | compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; |
| 706 | reg = <0x63fd0000 0x4000>; | |
| 707 | status = "disabled"; | |
| 708 | }; | |
| 709 | ||
| 7b7d6727 | 710 | nfc: nand@63fdb000 { |
| 75453a08 SH |
711 | compatible = "fsl,imx53-nand"; |
| 712 | reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; | |
| 713 | interrupts = <8>; | |
| 564695dd | 714 | clocks = <&clks IMX5_CLK_NFC_GATE>; |
| 75453a08 SH |
715 | status = "disabled"; |
| 716 | }; | |
| 717 | ||
| ffc505c0 | 718 | ssi3: ssi@63fe8000 { |
| 6ff7f51e | 719 | #sound-dai-cells = <0>; |
| 28f93d0b MP |
720 | compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", |
| 721 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
722 | reg = <0x63fe8000 0x4000>; |
| 723 | interrupts = <96>; | |
| 685570ab FE |
724 | clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, |
| 725 | <&clks IMX5_CLK_SSI3_ROOT_GATE>; | |
| 726 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
727 | dmas = <&sdma 46 0 0>, |
| 728 | <&sdma 47 0 0>; | |
| 729 | dma-names = "rx", "tx"; | |
| ffc505c0 | 730 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
731 | status = "disabled"; |
| 732 | }; | |
| 733 | ||
| 7b7d6727 | 734 | fec: ethernet@63fec000 { |
| 73d2b4cd SG |
735 | compatible = "fsl,imx53-fec", "fsl,imx25-fec"; |
| 736 | reg = <0x63fec000 0x4000>; | |
| 737 | interrupts = <87>; | |
| 564695dd LS |
738 | clocks = <&clks IMX5_CLK_FEC_GATE>, |
| 739 | <&clks IMX5_CLK_FEC_GATE>, | |
| 740 | <&clks IMX5_CLK_FEC_GATE>; | |
| f40f38d1 | 741 | clock-names = "ipg", "ahb", "ptp"; |
| 73d2b4cd SG |
742 | status = "disabled"; |
| 743 | }; | |
| 19194c2b PZ |
744 | |
| 745 | tve: tve@63ff0000 { | |
| 746 | compatible = "fsl,imx53-tve"; | |
| 747 | reg = <0x63ff0000 0x1000>; | |
| 748 | interrupts = <92>; | |
| 564695dd LS |
749 | clocks = <&clks IMX5_CLK_TVE_GATE>, |
| 750 | <&clks IMX5_CLK_IPU_DI1_SEL>; | |
| 19194c2b | 751 | clock-names = "tve", "di_sel"; |
| 19194c2b | 752 | status = "disabled"; |
| e05c8c9a PZ |
753 | |
| 754 | port { | |
| 755 | tve_in: endpoint { | |
| 756 | remote-endpoint = <&ipu_di1_tve>; | |
| 757 | }; | |
| 758 | }; | |
| 19194c2b | 759 | }; |
| fbf970f6 FE |
760 | |
| 761 | vpu: vpu@63ff4000 { | |
| 71946619 | 762 | compatible = "fsl,imx53-vpu", "cnm,coda7541"; |
| fbf970f6 FE |
763 | reg = <0x63ff4000 0x1000>; |
| 764 | interrupts = <9>; | |
| fa97d2f7 | 765 | clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, |
| 564695dd | 766 | <&clks IMX5_CLK_VPU_GATE>; |
| fbf970f6 | 767 | clock-names = "per", "ahb"; |
| b1e2e546 | 768 | resets = <&src 1>; |
| fbf970f6 | 769 | iram = <&ocram>; |
| fbf970f6 | 770 | }; |
| 60811cc2 ST |
771 | |
| 772 | sahara: crypto@63ff8000 { | |
| 773 | compatible = "fsl,imx53-sahara"; | |
| 774 | reg = <0x63ff8000 0x4000>; | |
| 775 | interrupts = <19 20>; | |
| 776 | clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, | |
| 777 | <&clks IMX5_CLK_SAHARA_IPG_GATE>; | |
| 778 | clock-names = "ipg", "ahb"; | |
| 779 | }; | |
| 73d2b4cd | 780 | }; |
| 481fbe13 PZ |
781 | |
| 782 | ocram: sram@f8000000 { | |
| 783 | compatible = "mmio-sram"; | |
| 784 | reg = <0xf8000000 0x20000>; | |
| 564695dd | 785 | clocks = <&clks IMX5_CLK_OCRAM>; |
| 481fbe13 | 786 | }; |
| 49bdf58e ST |
787 | |
| 788 | pmu { | |
| 789 | compatible = "arm,cortex-a8-pmu"; | |
| 790 | interrupts = <77>; | |
| 791 | }; | |
| 73d2b4cd SG |
792 | }; |
| 793 | }; |