projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 73d2b4cd SG |
1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
| 3 | * Copyright 2011 Linaro Ltd. | |
| 4 | * | |
| 5 | * The code contained herein is licensed under the GNU General Public | |
| 6 | * License. You may obtain a copy of the GNU General Public License | |
| 7 | * Version 2 or later at the following locations: | |
| 8 | * | |
| 9 | * http://www.opensource.org/licenses/gpl-license.html | |
| 10 | * http://www.gnu.org/copyleft/gpl.html | |
| 11 | */ | |
| 12 | ||
| e1641531 | 13 | #include "imx53-pinfunc.h" |
| 564695dd | 14 | #include <dt-bindings/clock/imx5-clock.h> |
| 4e05a7af DC |
15 | #include <dt-bindings/gpio/gpio.h> |
| 16 | #include <dt-bindings/input/input.h> | |
| 34adba71 | 17 | #include <dt-bindings/interrupt-controller/irq.h> |
| 73d2b4cd SG |
18 | |
| 19 | / { | |
| 7f107887 FE |
20 | #address-cells = <1>; |
| 21 | #size-cells = <1>; | |
| 22 | ||
| 73d2b4cd | 23 | aliases { |
| 22970070 | 24 | ethernet0 = &fec; |
| 5230f8fe SG |
25 | gpio0 = &gpio1; |
| 26 | gpio1 = &gpio2; | |
| 27 | gpio2 = &gpio3; | |
| 28 | gpio3 = &gpio4; | |
| 29 | gpio4 = &gpio5; | |
| 30 | gpio5 = &gpio6; | |
| 31 | gpio6 = &gpio7; | |
| c60dc1d1 PZ |
32 | i2c0 = &i2c1; |
| 33 | i2c1 = &i2c2; | |
| 34 | i2c2 = &i2c3; | |
| c63d06de SH |
35 | mmc0 = &esdhc1; |
| 36 | mmc1 = &esdhc2; | |
| 37 | mmc2 = &esdhc3; | |
| 38 | mmc3 = &esdhc4; | |
| cf4e577e SH |
39 | serial0 = &uart1; |
| 40 | serial1 = &uart2; | |
| 41 | serial2 = &uart3; | |
| 42 | serial3 = &uart4; | |
| 43 | serial4 = &uart5; | |
| 44 | spi0 = &ecspi1; | |
| 45 | spi1 = &ecspi2; | |
| 46 | spi2 = &cspi; | |
| 73d2b4cd SG |
47 | }; |
| 48 | ||
| 070bd7e4 FE |
49 | cpus { |
| 50 | #address-cells = <1>; | |
| 51 | #size-cells = <0>; | |
| 791f4166 | 52 | cpu0: cpu@0 { |
| 070bd7e4 FE |
53 | device_type = "cpu"; |
| 54 | compatible = "arm,cortex-a8"; | |
| 55 | reg = <0x0>; | |
| 791f4166 LS |
56 | clocks = <&clks IMX5_CLK_ARM>; |
| 57 | clock-latency = <61036>; | |
| 58 | voltage-tolerance = <5>; | |
| 59 | operating-points = < | |
| 60 | /* kHz */ | |
| 61 | 166666 850000 | |
| 62 | 400000 900000 | |
| 63 | 800000 1050000 | |
| 64 | 1000000 1200000 | |
| 65 | 1200000 1300000 | |
| 66 | >; | |
| 070bd7e4 FE |
67 | }; |
| 68 | }; | |
| 69 | ||
| e05c8c9a PZ |
70 | display-subsystem { |
| 71 | compatible = "fsl,imx-display-subsystem"; | |
| 72 | ports = <&ipu_di0>, <&ipu_di1>; | |
| 73 | }; | |
| 74 | ||
| 73d2b4cd SG |
75 | tzic: tz-interrupt-controller@0fffc000 { |
| 76 | compatible = "fsl,imx53-tzic", "fsl,tzic"; | |
| 77 | interrupt-controller; | |
| 78 | #interrupt-cells = <1>; | |
| 79 | reg = <0x0fffc000 0x4000>; | |
| 80 | }; | |
| 81 | ||
| 82 | clocks { | |
| 83 | #address-cells = <1>; | |
| 84 | #size-cells = <0>; | |
| 85 | ||
| 86 | ckil { | |
| 87 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
| 4b2b4043 | 88 | #clock-cells = <0>; |
| 73d2b4cd SG |
89 | clock-frequency = <32768>; |
| 90 | }; | |
| 91 | ||
| 92 | ckih1 { | |
| 93 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
| 4b2b4043 | 94 | #clock-cells = <0>; |
| 73d2b4cd SG |
95 | clock-frequency = <22579200>; |
| 96 | }; | |
| 97 | ||
| 98 | ckih2 { | |
| 99 | compatible = "fsl,imx-ckih2", "fixed-clock"; | |
| 4b2b4043 | 100 | #clock-cells = <0>; |
| 73d2b4cd SG |
101 | clock-frequency = <0>; |
| 102 | }; | |
| 103 | ||
| 104 | osc { | |
| 105 | compatible = "fsl,imx-osc", "fixed-clock"; | |
| 4b2b4043 | 106 | #clock-cells = <0>; |
| 73d2b4cd SG |
107 | clock-frequency = <24000000>; |
| 108 | }; | |
| 109 | }; | |
| 110 | ||
| 111 | soc { | |
| 112 | #address-cells = <1>; | |
| 113 | #size-cells = <1>; | |
| 114 | compatible = "simple-bus"; | |
| 115 | interrupt-parent = <&tzic>; | |
| 116 | ranges; | |
| 117 | ||
| 7affee43 MV |
118 | sata: sata@10000000 { |
| 119 | compatible = "fsl,imx53-ahci"; | |
| 120 | reg = <0x10000000 0x1000>; | |
| 121 | interrupts = <28>; | |
| 122 | clocks = <&clks IMX5_CLK_SATA_GATE>, | |
| 123 | <&clks IMX5_CLK_SATA_REF>, | |
| 124 | <&clks IMX5_CLK_AHB>; | |
| 02578153 | 125 | clock-names = "sata", "sata_ref", "ahb"; |
| 7affee43 MV |
126 | status = "disabled"; |
| 127 | }; | |
| 128 | ||
| abed9a6b | 129 | ipu: ipu@18000000 { |
| e05c8c9a PZ |
130 | #address-cells = <1>; |
| 131 | #size-cells = <0>; | |
| abed9a6b | 132 | compatible = "fsl,imx53-ipu"; |
| 6d66da89 | 133 | reg = <0x18000000 0x08000000>; |
| abed9a6b | 134 | interrupts = <11 10>; |
| 564695dd | 135 | clocks = <&clks IMX5_CLK_IPU_GATE>, |
| 46311707 JT |
136 | <&clks IMX5_CLK_IPU_DI0_GATE>, |
| 137 | <&clks IMX5_CLK_IPU_DI1_GATE>; | |
| 4438a6a1 | 138 | clock-names = "bus", "di0", "di1"; |
| 8d84c374 | 139 | resets = <&src 2>; |
| e05c8c9a | 140 | |
| 2a8e583c FL |
141 | ipu_csi0: port@0 { |
| 142 | reg = <0>; | |
| 143 | }; | |
| 144 | ||
| 145 | ipu_csi1: port@1 { | |
| 146 | reg = <1>; | |
| 147 | }; | |
| 148 | ||
| e05c8c9a PZ |
149 | ipu_di0: port@2 { |
| 150 | #address-cells = <1>; | |
| 151 | #size-cells = <0>; | |
| 152 | reg = <2>; | |
| 153 | ||
| 154 | ipu_di0_disp0: endpoint@0 { | |
| 155 | reg = <0>; | |
| 156 | }; | |
| 157 | ||
| 158 | ipu_di0_lvds0: endpoint@1 { | |
| 159 | reg = <1>; | |
| 160 | remote-endpoint = <&lvds0_in>; | |
| 161 | }; | |
| 162 | }; | |
| 163 | ||
| 164 | ipu_di1: port@3 { | |
| 165 | #address-cells = <1>; | |
| 166 | #size-cells = <0>; | |
| 167 | reg = <3>; | |
| 168 | ||
| 169 | ipu_di1_disp1: endpoint@0 { | |
| 170 | reg = <0>; | |
| 171 | }; | |
| 172 | ||
| 173 | ipu_di1_lvds1: endpoint@1 { | |
| 174 | reg = <1>; | |
| 175 | remote-endpoint = <&lvds1_in>; | |
| 176 | }; | |
| 177 | ||
| 178 | ipu_di1_tve: endpoint@2 { | |
| 179 | reg = <2>; | |
| 180 | remote-endpoint = <&tve_in>; | |
| 181 | }; | |
| 182 | }; | |
| abed9a6b SH |
183 | }; |
| 184 | ||
| 73d2b4cd SG |
185 | aips@50000000 { /* AIPS1 */ |
| 186 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 187 | #address-cells = <1>; | |
| 188 | #size-cells = <1>; | |
| 189 | reg = <0x50000000 0x10000000>; | |
| 190 | ranges; | |
| 191 | ||
| 192 | spba@50000000 { | |
| 193 | compatible = "fsl,spba-bus", "simple-bus"; | |
| 194 | #address-cells = <1>; | |
| 195 | #size-cells = <1>; | |
| 196 | reg = <0x50000000 0x40000>; | |
| 197 | ranges; | |
| 198 | ||
| 7b7d6727 | 199 | esdhc1: esdhc@50004000 { |
| 73d2b4cd SG |
200 | compatible = "fsl,imx53-esdhc"; |
| 201 | reg = <0x50004000 0x4000>; | |
| 202 | interrupts = <1>; | |
| 564695dd | 203 | clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, |
| 46311707 JT |
204 | <&clks IMX5_CLK_DUMMY>, |
| 205 | <&clks IMX5_CLK_ESDHC1_PER_GATE>; | |
| f40f38d1 | 206 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 207 | bus-width = <4>; |
| 73d2b4cd SG |
208 | status = "disabled"; |
| 209 | }; | |
| 210 | ||
| 7b7d6727 | 211 | esdhc2: esdhc@50008000 { |
| 73d2b4cd SG |
212 | compatible = "fsl,imx53-esdhc"; |
| 213 | reg = <0x50008000 0x4000>; | |
| 214 | interrupts = <2>; | |
| 564695dd | 215 | clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, |
| 46311707 JT |
216 | <&clks IMX5_CLK_DUMMY>, |
| 217 | <&clks IMX5_CLK_ESDHC2_PER_GATE>; | |
| f40f38d1 | 218 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 219 | bus-width = <4>; |
| 73d2b4cd SG |
220 | status = "disabled"; |
| 221 | }; | |
| 222 | ||
| 0c456cfa | 223 | uart3: serial@5000c000 { |
| 73d2b4cd SG |
224 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 225 | reg = <0x5000c000 0x4000>; | |
| 226 | interrupts = <33>; | |
| 564695dd | 227 | clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, |
| 46311707 | 228 | <&clks IMX5_CLK_UART3_PER_GATE>; |
| f40f38d1 | 229 | clock-names = "ipg", "per"; |
| d04eba90 FL |
230 | dmas = <&sdma 42 4 0>, <&sdma 43 4 0>; |
| 231 | dma-names = "rx", "tx"; | |
| 73d2b4cd SG |
232 | status = "disabled"; |
| 233 | }; | |
| 234 | ||
| 7b7d6727 | 235 | ecspi1: ecspi@50010000 { |
| 73d2b4cd SG |
236 | #address-cells = <1>; |
| 237 | #size-cells = <0>; | |
| 238 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
| 239 | reg = <0x50010000 0x4000>; | |
| 240 | interrupts = <36>; | |
| 564695dd | 241 | clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, |
| 46311707 | 242 | <&clks IMX5_CLK_ECSPI1_PER_GATE>; |
| f40f38d1 | 243 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
244 | status = "disabled"; |
| 245 | }; | |
| 246 | ||
| ffc505c0 | 247 | ssi2: ssi@50014000 { |
| 6ff7f51e | 248 | #sound-dai-cells = <0>; |
| 28f93d0b MP |
249 | compatible = "fsl,imx53-ssi", |
| 250 | "fsl,imx51-ssi", | |
| 251 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
252 | reg = <0x50014000 0x4000>; |
| 253 | interrupts = <30>; | |
| 685570ab FE |
254 | clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, |
| 255 | <&clks IMX5_CLK_SSI2_ROOT_GATE>; | |
| 256 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
257 | dmas = <&sdma 24 1 0>, |
| 258 | <&sdma 25 1 0>; | |
| 259 | dma-names = "rx", "tx"; | |
| ffc505c0 | 260 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
261 | status = "disabled"; |
| 262 | }; | |
| 263 | ||
| 7b7d6727 | 264 | esdhc3: esdhc@50020000 { |
| 73d2b4cd SG |
265 | compatible = "fsl,imx53-esdhc"; |
| 266 | reg = <0x50020000 0x4000>; | |
| 267 | interrupts = <3>; | |
| 564695dd | 268 | clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, |
| 46311707 JT |
269 | <&clks IMX5_CLK_DUMMY>, |
| 270 | <&clks IMX5_CLK_ESDHC3_PER_GATE>; | |
| f40f38d1 | 271 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 272 | bus-width = <4>; |
| 73d2b4cd SG |
273 | status = "disabled"; |
| 274 | }; | |
| 275 | ||
| 7b7d6727 | 276 | esdhc4: esdhc@50024000 { |
| 73d2b4cd SG |
277 | compatible = "fsl,imx53-esdhc"; |
| 278 | reg = <0x50024000 0x4000>; | |
| 279 | interrupts = <4>; | |
| 564695dd | 280 | clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, |
| 46311707 JT |
281 | <&clks IMX5_CLK_DUMMY>, |
| 282 | <&clks IMX5_CLK_ESDHC4_PER_GATE>; | |
| f40f38d1 | 283 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 284 | bus-width = <4>; |
| 73d2b4cd SG |
285 | status = "disabled"; |
| 286 | }; | |
| 287 | }; | |
| 288 | ||
| ac08281e ST |
289 | aipstz1: bridge@53f00000 { |
| 290 | compatible = "fsl,imx53-aipstz"; | |
| 291 | reg = <0x53f00000 0x60>; | |
| 292 | }; | |
| 293 | ||
| a79025c4 MG |
294 | usbphy0: usbphy@0 { |
| 295 | compatible = "usb-nop-xceiv"; | |
| 564695dd | 296 | clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; |
| a79025c4 MG |
297 | clock-names = "main_clk"; |
| 298 | status = "okay"; | |
| 299 | }; | |
| 300 | ||
| 301 | usbphy1: usbphy@1 { | |
| 302 | compatible = "usb-nop-xceiv"; | |
| 564695dd | 303 | clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; |
| a79025c4 MG |
304 | clock-names = "main_clk"; |
| 305 | status = "okay"; | |
| 306 | }; | |
| 307 | ||
| 7b7d6727 | 308 | usbotg: usb@53f80000 { |
| 212d0b83 MG |
309 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 310 | reg = <0x53f80000 0x0200>; | |
| 311 | interrupts = <18>; | |
| 564695dd | 312 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 313 | fsl,usbmisc = <&usbmisc 0>; |
| a79025c4 | 314 | fsl,usbphy = <&usbphy0>; |
| 212d0b83 MG |
315 | status = "disabled"; |
| 316 | }; | |
| 317 | ||
| 7b7d6727 | 318 | usbh1: usb@53f80200 { |
| 212d0b83 MG |
319 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 320 | reg = <0x53f80200 0x0200>; | |
| 321 | interrupts = <14>; | |
| 564695dd | 322 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 323 | fsl,usbmisc = <&usbmisc 1>; |
| a79025c4 | 324 | fsl,usbphy = <&usbphy1>; |
| 3ec481ed | 325 | dr_mode = "host"; |
| 212d0b83 MG |
326 | status = "disabled"; |
| 327 | }; | |
| 328 | ||
| 7b7d6727 | 329 | usbh2: usb@53f80400 { |
| 212d0b83 MG |
330 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 331 | reg = <0x53f80400 0x0200>; | |
| 332 | interrupts = <16>; | |
| 564695dd | 333 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 334 | fsl,usbmisc = <&usbmisc 2>; |
| 3ec481ed | 335 | dr_mode = "host"; |
| 212d0b83 MG |
336 | status = "disabled"; |
| 337 | }; | |
| 338 | ||
| 7b7d6727 | 339 | usbh3: usb@53f80600 { |
| 212d0b83 MG |
340 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 341 | reg = <0x53f80600 0x0200>; | |
| 342 | interrupts = <17>; | |
| 564695dd | 343 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 344 | fsl,usbmisc = <&usbmisc 3>; |
| 3ec481ed | 345 | dr_mode = "host"; |
| 212d0b83 MG |
346 | status = "disabled"; |
| 347 | }; | |
| 348 | ||
| a5735021 MG |
349 | usbmisc: usbmisc@53f80800 { |
| 350 | #index-cells = <1>; | |
| 351 | compatible = "fsl,imx53-usbmisc"; | |
| 352 | reg = <0x53f80800 0x200>; | |
| 564695dd | 353 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 MG |
354 | }; |
| 355 | ||
| 4d191868 | 356 | gpio1: gpio@53f84000 { |
| aeb27748 | 357 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
358 | reg = <0x53f84000 0x4000>; |
| 359 | interrupts = <50 51>; | |
| 360 | gpio-controller; | |
| 361 | #gpio-cells = <2>; | |
| 362 | interrupt-controller; | |
| 88cde8b7 | 363 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
364 | }; |
| 365 | ||
| 4d191868 | 366 | gpio2: gpio@53f88000 { |
| aeb27748 | 367 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
368 | reg = <0x53f88000 0x4000>; |
| 369 | interrupts = <52 53>; | |
| 370 | gpio-controller; | |
| 371 | #gpio-cells = <2>; | |
| 372 | interrupt-controller; | |
| 88cde8b7 | 373 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
374 | }; |
| 375 | ||
| 4d191868 | 376 | gpio3: gpio@53f8c000 { |
| aeb27748 | 377 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
378 | reg = <0x53f8c000 0x4000>; |
| 379 | interrupts = <54 55>; | |
| 380 | gpio-controller; | |
| 381 | #gpio-cells = <2>; | |
| 382 | interrupt-controller; | |
| 88cde8b7 | 383 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
384 | }; |
| 385 | ||
| 4d191868 | 386 | gpio4: gpio@53f90000 { |
| aeb27748 | 387 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
388 | reg = <0x53f90000 0x4000>; |
| 389 | interrupts = <56 57>; | |
| 390 | gpio-controller; | |
| 391 | #gpio-cells = <2>; | |
| 392 | interrupt-controller; | |
| 88cde8b7 | 393 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
394 | }; |
| 395 | ||
| 675e4d03 RL |
396 | kpp: kpp@53f94000 { |
| 397 | compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; | |
| 398 | reg = <0x53f94000 0x4000>; | |
| 399 | interrupts = <60>; | |
| 564695dd | 400 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 675e4d03 RL |
401 | status = "disabled"; |
| 402 | }; | |
| 403 | ||
| 7b7d6727 | 404 | wdog1: wdog@53f98000 { |
| 73d2b4cd SG |
405 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 406 | reg = <0x53f98000 0x4000>; | |
| 407 | interrupts = <58>; | |
| 564695dd | 408 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 73d2b4cd SG |
409 | }; |
| 410 | ||
| 7b7d6727 | 411 | wdog2: wdog@53f9c000 { |
| 73d2b4cd SG |
412 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 413 | reg = <0x53f9c000 0x4000>; | |
| 414 | interrupts = <59>; | |
| 564695dd | 415 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 73d2b4cd SG |
416 | status = "disabled"; |
| 417 | }; | |
| 418 | ||
| cc8aae9b SH |
419 | gpt: timer@53fa0000 { |
| 420 | compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; | |
| 421 | reg = <0x53fa0000 0x4000>; | |
| 422 | interrupts = <39>; | |
| 564695dd | 423 | clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, |
| 46311707 | 424 | <&clks IMX5_CLK_GPT_HF_GATE>; |
| cc8aae9b SH |
425 | clock-names = "ipg", "per"; |
| 426 | }; | |
| 427 | ||
| 7b7d6727 | 428 | iomuxc: iomuxc@53fa8000 { |
| 5be03a7b SG |
429 | compatible = "fsl,imx53-iomuxc"; |
| 430 | reg = <0x53fa8000 0x4000>; | |
| 5be03a7b SG |
431 | }; |
| 432 | ||
| 5af9f143 PZ |
433 | gpr: iomuxc-gpr@53fa8000 { |
| 434 | compatible = "fsl,imx53-iomuxc-gpr", "syscon"; | |
| 435 | reg = <0x53fa8000 0xc>; | |
| 436 | }; | |
| 437 | ||
| 420714aa PZ |
438 | ldb: ldb@53fa8008 { |
| 439 | #address-cells = <1>; | |
| 440 | #size-cells = <0>; | |
| 441 | compatible = "fsl,imx53-ldb"; | |
| 442 | reg = <0x53fa8008 0x4>; | |
| 443 | gpr = <&gpr>; | |
| 564695dd | 444 | clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, |
| 46311707 JT |
445 | <&clks IMX5_CLK_LDB_DI1_SEL>, |
| 446 | <&clks IMX5_CLK_IPU_DI0_SEL>, | |
| 447 | <&clks IMX5_CLK_IPU_DI1_SEL>, | |
| 448 | <&clks IMX5_CLK_LDB_DI0_GATE>, | |
| 449 | <&clks IMX5_CLK_LDB_DI1_GATE>; | |
| 420714aa PZ |
450 | clock-names = "di0_pll", "di1_pll", |
| 451 | "di0_sel", "di1_sel", | |
| 452 | "di0", "di1"; | |
| 453 | status = "disabled"; | |
| 454 | ||
| 455 | lvds-channel@0 { | |
| 1b134c9c MN |
456 | #address-cells = <1>; |
| 457 | #size-cells = <0>; | |
| 420714aa | 458 | reg = <0>; |
| 420714aa | 459 | status = "disabled"; |
| e05c8c9a | 460 | |
| 1b134c9c MN |
461 | port@0 { |
| 462 | reg = <0>; | |
| 463 | ||
| e05c8c9a PZ |
464 | lvds0_in: endpoint { |
| 465 | remote-endpoint = <&ipu_di0_lvds0>; | |
| 466 | }; | |
| 467 | }; | |
| 420714aa PZ |
468 | }; |
| 469 | ||
| 470 | lvds-channel@1 { | |
| 1b134c9c MN |
471 | #address-cells = <1>; |
| 472 | #size-cells = <0>; | |
| 420714aa | 473 | reg = <1>; |
| 420714aa | 474 | status = "disabled"; |
| e05c8c9a | 475 | |
| 1b134c9c MN |
476 | port@1 { |
| 477 | reg = <1>; | |
| 478 | ||
| e05c8c9a | 479 | lvds1_in: endpoint { |
| fa1746ae | 480 | remote-endpoint = <&ipu_di1_lvds1>; |
| e05c8c9a PZ |
481 | }; |
| 482 | }; | |
| 420714aa PZ |
483 | }; |
| 484 | }; | |
| 485 | ||
| 9ae90afa SH |
486 | pwm1: pwm@53fb4000 { |
| 487 | #pwm-cells = <2>; | |
| 488 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
| 489 | reg = <0x53fb4000 0x4000>; | |
| 564695dd | 490 | clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, |
| 46311707 | 491 | <&clks IMX5_CLK_PWM1_HF_GATE>; |
| 9ae90afa SH |
492 | clock-names = "ipg", "per"; |
| 493 | interrupts = <61>; | |
| 494 | }; | |
| 495 | ||
| 496 | pwm2: pwm@53fb8000 { | |
| 497 | #pwm-cells = <2>; | |
| 498 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
| 499 | reg = <0x53fb8000 0x4000>; | |
| 564695dd | 500 | clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, |
| 46311707 | 501 | <&clks IMX5_CLK_PWM2_HF_GATE>; |
| 9ae90afa SH |
502 | clock-names = "ipg", "per"; |
| 503 | interrupts = <94>; | |
| 504 | }; | |
| 505 | ||
| 0c456cfa | 506 | uart1: serial@53fbc000 { |
| 73d2b4cd SG |
507 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 508 | reg = <0x53fbc000 0x4000>; | |
| 509 | interrupts = <31>; | |
| 564695dd | 510 | clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, |
| 46311707 | 511 | <&clks IMX5_CLK_UART1_PER_GATE>; |
| f40f38d1 | 512 | clock-names = "ipg", "per"; |
| d04eba90 FL |
513 | dmas = <&sdma 18 4 0>, <&sdma 19 4 0>; |
| 514 | dma-names = "rx", "tx"; | |
| 73d2b4cd SG |
515 | status = "disabled"; |
| 516 | }; | |
| 517 | ||
| 0c456cfa | 518 | uart2: serial@53fc0000 { |
| 73d2b4cd SG |
519 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 520 | reg = <0x53fc0000 0x4000>; | |
| 521 | interrupts = <32>; | |
| 564695dd | 522 | clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, |
| 46311707 | 523 | <&clks IMX5_CLK_UART2_PER_GATE>; |
| f40f38d1 | 524 | clock-names = "ipg", "per"; |
| d04eba90 FL |
525 | dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; |
| 526 | dma-names = "rx", "tx"; | |
| 73d2b4cd SG |
527 | status = "disabled"; |
| 528 | }; | |
| 529 | ||
| a9d1f924 ST |
530 | can1: can@53fc8000 { |
| 531 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | |
| 532 | reg = <0x53fc8000 0x4000>; | |
| 533 | interrupts = <82>; | |
| 564695dd | 534 | clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, |
| 46311707 | 535 | <&clks IMX5_CLK_CAN1_SERIAL_GATE>; |
| f40f38d1 | 536 | clock-names = "ipg", "per"; |
| a9d1f924 ST |
537 | status = "disabled"; |
| 538 | }; | |
| 539 | ||
| 540 | can2: can@53fcc000 { | |
| 541 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | |
| 542 | reg = <0x53fcc000 0x4000>; | |
| 543 | interrupts = <83>; | |
| 564695dd | 544 | clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, |
| 46311707 | 545 | <&clks IMX5_CLK_CAN2_SERIAL_GATE>; |
| f40f38d1 | 546 | clock-names = "ipg", "per"; |
| a9d1f924 ST |
547 | status = "disabled"; |
| 548 | }; | |
| 549 | ||
| 8d84c374 PZ |
550 | src: src@53fd0000 { |
| 551 | compatible = "fsl,imx53-src", "fsl,imx51-src"; | |
| 552 | reg = <0x53fd0000 0x4000>; | |
| 553 | #reset-cells = <1>; | |
| 554 | }; | |
| 555 | ||
| f40f38d1 FE |
556 | clks: ccm@53fd4000{ |
| 557 | compatible = "fsl,imx53-ccm"; | |
| 558 | reg = <0x53fd4000 0x4000>; | |
| 559 | interrupts = <0 71 0x04 0 72 0x04>; | |
| 560 | #clock-cells = <1>; | |
| 561 | }; | |
| 562 | ||
| 4d191868 | 563 | gpio5: gpio@53fdc000 { |
| aeb27748 | 564 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
565 | reg = <0x53fdc000 0x4000>; |
| 566 | interrupts = <103 104>; | |
| 567 | gpio-controller; | |
| 568 | #gpio-cells = <2>; | |
| 569 | interrupt-controller; | |
| 88cde8b7 | 570 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
571 | }; |
| 572 | ||
| 4d191868 | 573 | gpio6: gpio@53fe0000 { |
| aeb27748 | 574 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
575 | reg = <0x53fe0000 0x4000>; |
| 576 | interrupts = <105 106>; | |
| 577 | gpio-controller; | |
| 578 | #gpio-cells = <2>; | |
| 579 | interrupt-controller; | |
| 88cde8b7 | 580 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
581 | }; |
| 582 | ||
| 4d191868 | 583 | gpio7: gpio@53fe4000 { |
| aeb27748 | 584 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
585 | reg = <0x53fe4000 0x4000>; |
| 586 | interrupts = <107 108>; | |
| 587 | gpio-controller; | |
| 588 | #gpio-cells = <2>; | |
| 589 | interrupt-controller; | |
| 88cde8b7 | 590 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
591 | }; |
| 592 | ||
| 7b7d6727 | 593 | i2c3: i2c@53fec000 { |
| 73d2b4cd SG |
594 | #address-cells = <1>; |
| 595 | #size-cells = <0>; | |
| 5bdfba29 | 596 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
597 | reg = <0x53fec000 0x4000>; |
| 598 | interrupts = <64>; | |
| 564695dd | 599 | clocks = <&clks IMX5_CLK_I2C3_GATE>; |
| 73d2b4cd SG |
600 | status = "disabled"; |
| 601 | }; | |
| 602 | ||
| 0c456cfa | 603 | uart4: serial@53ff0000 { |
| 73d2b4cd SG |
604 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 605 | reg = <0x53ff0000 0x4000>; | |
| 606 | interrupts = <13>; | |
| 564695dd | 607 | clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, |
| 46311707 | 608 | <&clks IMX5_CLK_UART4_PER_GATE>; |
| f40f38d1 | 609 | clock-names = "ipg", "per"; |
| d04eba90 FL |
610 | dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; |
| 611 | dma-names = "rx", "tx"; | |
| 73d2b4cd SG |
612 | status = "disabled"; |
| 613 | }; | |
| 614 | }; | |
| 615 | ||
| 616 | aips@60000000 { /* AIPS2 */ | |
| 617 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 618 | #address-cells = <1>; | |
| 619 | #size-cells = <1>; | |
| 620 | reg = <0x60000000 0x10000000>; | |
| 621 | ranges; | |
| 622 | ||
| ac08281e ST |
623 | aipstz2: bridge@63f00000 { |
| 624 | compatible = "fsl,imx53-aipstz"; | |
| 625 | reg = <0x63f00000 0x60>; | |
| 626 | }; | |
| 627 | ||
| 4f3b2a41 SH |
628 | iim: iim@63f98000 { |
| 629 | compatible = "fsl,imx53-iim", "fsl,imx27-iim"; | |
| 630 | reg = <0x63f98000 0x4000>; | |
| 631 | interrupts = <69>; | |
| 564695dd | 632 | clocks = <&clks IMX5_CLK_IIM_GATE>; |
| 4f3b2a41 SH |
633 | }; |
| 634 | ||
| 0c456cfa | 635 | uart5: serial@63f90000 { |
| 73d2b4cd SG |
636 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 637 | reg = <0x63f90000 0x4000>; | |
| 638 | interrupts = <86>; | |
| 564695dd | 639 | clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, |
| 46311707 | 640 | <&clks IMX5_CLK_UART5_PER_GATE>; |
| f40f38d1 | 641 | clock-names = "ipg", "per"; |
| d04eba90 FL |
642 | dmas = <&sdma 16 4 0>, <&sdma 17 4 0>; |
| 643 | dma-names = "rx", "tx"; | |
| 73d2b4cd SG |
644 | status = "disabled"; |
| 645 | }; | |
| 646 | ||
| a82b7b9c MF |
647 | owire: owire@63fa4000 { |
| 648 | compatible = "fsl,imx53-owire", "fsl,imx21-owire"; | |
| 649 | reg = <0x63fa4000 0x4000>; | |
| 564695dd | 650 | clocks = <&clks IMX5_CLK_OWIRE_GATE>; |
| a82b7b9c MF |
651 | status = "disabled"; |
| 652 | }; | |
| 653 | ||
| 7b7d6727 | 654 | ecspi2: ecspi@63fac000 { |
| 73d2b4cd SG |
655 | #address-cells = <1>; |
| 656 | #size-cells = <0>; | |
| 657 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
| 658 | reg = <0x63fac000 0x4000>; | |
| 659 | interrupts = <37>; | |
| 564695dd | 660 | clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, |
| 46311707 | 661 | <&clks IMX5_CLK_ECSPI2_PER_GATE>; |
| f40f38d1 | 662 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
663 | status = "disabled"; |
| 664 | }; | |
| 665 | ||
| 7b7d6727 | 666 | sdma: sdma@63fb0000 { |
| 73d2b4cd SG |
667 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; |
| 668 | reg = <0x63fb0000 0x4000>; | |
| 669 | interrupts = <6>; | |
| 564695dd | 670 | clocks = <&clks IMX5_CLK_SDMA_GATE>, |
| 46311707 | 671 | <&clks IMX5_CLK_SDMA_GATE>; |
| f40f38d1 | 672 | clock-names = "ipg", "ahb"; |
| fb72bb21 | 673 | #dma-cells = <3>; |
| 7e4f0365 | 674 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; |
| 73d2b4cd SG |
675 | }; |
| 676 | ||
| 7b7d6727 | 677 | cspi: cspi@63fc0000 { |
| 73d2b4cd SG |
678 | #address-cells = <1>; |
| 679 | #size-cells = <0>; | |
| 680 | compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; | |
| 681 | reg = <0x63fc0000 0x4000>; | |
| 682 | interrupts = <38>; | |
| 564695dd | 683 | clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, |
| 46311707 | 684 | <&clks IMX5_CLK_CSPI_IPG_GATE>; |
| f40f38d1 | 685 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
686 | status = "disabled"; |
| 687 | }; | |
| 688 | ||
| 7b7d6727 | 689 | i2c2: i2c@63fc4000 { |
| 73d2b4cd SG |
690 | #address-cells = <1>; |
| 691 | #size-cells = <0>; | |
| 5bdfba29 | 692 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
693 | reg = <0x63fc4000 0x4000>; |
| 694 | interrupts = <63>; | |
| 564695dd | 695 | clocks = <&clks IMX5_CLK_I2C2_GATE>; |
| 73d2b4cd SG |
696 | status = "disabled"; |
| 697 | }; | |
| 698 | ||
| 7b7d6727 | 699 | i2c1: i2c@63fc8000 { |
| 73d2b4cd SG |
700 | #address-cells = <1>; |
| 701 | #size-cells = <0>; | |
| 5bdfba29 | 702 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
703 | reg = <0x63fc8000 0x4000>; |
| 704 | interrupts = <62>; | |
| 564695dd | 705 | clocks = <&clks IMX5_CLK_I2C1_GATE>; |
| 73d2b4cd SG |
706 | status = "disabled"; |
| 707 | }; | |
| 708 | ||
| ffc505c0 | 709 | ssi1: ssi@63fcc000 { |
| 6ff7f51e | 710 | #sound-dai-cells = <0>; |
| 28f93d0b MP |
711 | compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", |
| 712 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
713 | reg = <0x63fcc000 0x4000>; |
| 714 | interrupts = <29>; | |
| 685570ab FE |
715 | clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, |
| 716 | <&clks IMX5_CLK_SSI1_ROOT_GATE>; | |
| 717 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
718 | dmas = <&sdma 28 0 0>, |
| 719 | <&sdma 29 0 0>; | |
| 720 | dma-names = "rx", "tx"; | |
| ffc505c0 | 721 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
722 | status = "disabled"; |
| 723 | }; | |
| 724 | ||
| 7b7d6727 | 725 | audmux: audmux@63fd0000 { |
| ffc505c0 SG |
726 | compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; |
| 727 | reg = <0x63fd0000 0x4000>; | |
| 728 | status = "disabled"; | |
| 729 | }; | |
| 730 | ||
| 7b7d6727 | 731 | nfc: nand@63fdb000 { |
| 75453a08 SH |
732 | compatible = "fsl,imx53-nand"; |
| 733 | reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; | |
| 734 | interrupts = <8>; | |
| 564695dd | 735 | clocks = <&clks IMX5_CLK_NFC_GATE>; |
| 75453a08 SH |
736 | status = "disabled"; |
| 737 | }; | |
| 738 | ||
| ffc505c0 | 739 | ssi3: ssi@63fe8000 { |
| 6ff7f51e | 740 | #sound-dai-cells = <0>; |
| 28f93d0b MP |
741 | compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", |
| 742 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
743 | reg = <0x63fe8000 0x4000>; |
| 744 | interrupts = <96>; | |
| 685570ab FE |
745 | clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, |
| 746 | <&clks IMX5_CLK_SSI3_ROOT_GATE>; | |
| 747 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
748 | dmas = <&sdma 46 0 0>, |
| 749 | <&sdma 47 0 0>; | |
| 750 | dma-names = "rx", "tx"; | |
| ffc505c0 | 751 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
752 | status = "disabled"; |
| 753 | }; | |
| 754 | ||
| 7b7d6727 | 755 | fec: ethernet@63fec000 { |
| 73d2b4cd SG |
756 | compatible = "fsl,imx53-fec", "fsl,imx25-fec"; |
| 757 | reg = <0x63fec000 0x4000>; | |
| 758 | interrupts = <87>; | |
| 564695dd | 759 | clocks = <&clks IMX5_CLK_FEC_GATE>, |
| 46311707 JT |
760 | <&clks IMX5_CLK_FEC_GATE>, |
| 761 | <&clks IMX5_CLK_FEC_GATE>; | |
| f40f38d1 | 762 | clock-names = "ipg", "ahb", "ptp"; |
| 73d2b4cd SG |
763 | status = "disabled"; |
| 764 | }; | |
| 19194c2b PZ |
765 | |
| 766 | tve: tve@63ff0000 { | |
| 767 | compatible = "fsl,imx53-tve"; | |
| 768 | reg = <0x63ff0000 0x1000>; | |
| 769 | interrupts = <92>; | |
| 564695dd | 770 | clocks = <&clks IMX5_CLK_TVE_GATE>, |
| 46311707 | 771 | <&clks IMX5_CLK_IPU_DI1_SEL>; |
| 19194c2b | 772 | clock-names = "tve", "di_sel"; |
| 19194c2b | 773 | status = "disabled"; |
| e05c8c9a PZ |
774 | |
| 775 | port { | |
| 776 | tve_in: endpoint { | |
| 777 | remote-endpoint = <&ipu_di1_tve>; | |
| 778 | }; | |
| 779 | }; | |
| 19194c2b | 780 | }; |
| fbf970f6 FE |
781 | |
| 782 | vpu: vpu@63ff4000 { | |
| 71946619 | 783 | compatible = "fsl,imx53-vpu", "cnm,coda7541"; |
| fbf970f6 FE |
784 | reg = <0x63ff4000 0x1000>; |
| 785 | interrupts = <9>; | |
| fa97d2f7 | 786 | clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, |
| 46311707 | 787 | <&clks IMX5_CLK_VPU_GATE>; |
| fbf970f6 | 788 | clock-names = "per", "ahb"; |
| b1e2e546 | 789 | resets = <&src 1>; |
| fbf970f6 | 790 | iram = <&ocram>; |
| fbf970f6 | 791 | }; |
| 60811cc2 ST |
792 | |
| 793 | sahara: crypto@63ff8000 { | |
| 794 | compatible = "fsl,imx53-sahara"; | |
| 795 | reg = <0x63ff8000 0x4000>; | |
| 796 | interrupts = <19 20>; | |
| 797 | clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, | |
| 46311707 | 798 | <&clks IMX5_CLK_SAHARA_IPG_GATE>; |
| 60811cc2 ST |
799 | clock-names = "ipg", "ahb"; |
| 800 | }; | |
| 73d2b4cd | 801 | }; |
| 481fbe13 PZ |
802 | |
| 803 | ocram: sram@f8000000 { | |
| 804 | compatible = "mmio-sram"; | |
| 805 | reg = <0xf8000000 0x20000>; | |
| 564695dd | 806 | clocks = <&clks IMX5_CLK_OCRAM>; |
| 481fbe13 | 807 | }; |
| 49bdf58e ST |
808 | |
| 809 | pmu { | |
| 810 | compatible = "arm,cortex-a8-pmu"; | |
| 811 | interrupts = <77>; | |
| 812 | }; | |
| 73d2b4cd SG |
813 | }; |
| 814 | }; |