projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 73d2b4cd SG |
1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
| 3 | * Copyright 2011 Linaro Ltd. | |
| 4 | * | |
| 5 | * The code contained herein is licensed under the GNU General Public | |
| 6 | * License. You may obtain a copy of the GNU General Public License | |
| 7 | * Version 2 or later at the following locations: | |
| 8 | * | |
| 9 | * http://www.opensource.org/licenses/gpl-license.html | |
| 10 | * http://www.gnu.org/copyleft/gpl.html | |
| 11 | */ | |
| 12 | ||
| 36dffd8f | 13 | #include "skeleton.dtsi" |
| e1641531 | 14 | #include "imx53-pinfunc.h" |
| 564695dd | 15 | #include <dt-bindings/clock/imx5-clock.h> |
| 4e05a7af DC |
16 | #include <dt-bindings/gpio/gpio.h> |
| 17 | #include <dt-bindings/input/input.h> | |
| 73d2b4cd SG |
18 | |
| 19 | / { | |
| 20 | aliases { | |
| 22970070 | 21 | ethernet0 = &fec; |
| 5230f8fe SG |
22 | gpio0 = &gpio1; |
| 23 | gpio1 = &gpio2; | |
| 24 | gpio2 = &gpio3; | |
| 25 | gpio3 = &gpio4; | |
| 26 | gpio4 = &gpio5; | |
| 27 | gpio5 = &gpio6; | |
| 28 | gpio6 = &gpio7; | |
| c60dc1d1 PZ |
29 | i2c0 = &i2c1; |
| 30 | i2c1 = &i2c2; | |
| 31 | i2c2 = &i2c3; | |
| c63d06de SH |
32 | mmc0 = &esdhc1; |
| 33 | mmc1 = &esdhc2; | |
| 34 | mmc2 = &esdhc3; | |
| 35 | mmc3 = &esdhc4; | |
| cf4e577e SH |
36 | serial0 = &uart1; |
| 37 | serial1 = &uart2; | |
| 38 | serial2 = &uart3; | |
| 39 | serial3 = &uart4; | |
| 40 | serial4 = &uart5; | |
| 41 | spi0 = &ecspi1; | |
| 42 | spi1 = &ecspi2; | |
| 43 | spi2 = &cspi; | |
| 73d2b4cd SG |
44 | }; |
| 45 | ||
| 070bd7e4 FE |
46 | cpus { |
| 47 | #address-cells = <1>; | |
| 48 | #size-cells = <0>; | |
| 49 | cpu@0 { | |
| 50 | device_type = "cpu"; | |
| 51 | compatible = "arm,cortex-a8"; | |
| 52 | reg = <0x0>; | |
| 53 | }; | |
| 54 | }; | |
| 55 | ||
| e05c8c9a PZ |
56 | display-subsystem { |
| 57 | compatible = "fsl,imx-display-subsystem"; | |
| 58 | ports = <&ipu_di0>, <&ipu_di1>; | |
| 59 | }; | |
| 60 | ||
| 73d2b4cd SG |
61 | tzic: tz-interrupt-controller@0fffc000 { |
| 62 | compatible = "fsl,imx53-tzic", "fsl,tzic"; | |
| 63 | interrupt-controller; | |
| 64 | #interrupt-cells = <1>; | |
| 65 | reg = <0x0fffc000 0x4000>; | |
| 66 | }; | |
| 67 | ||
| 68 | clocks { | |
| 69 | #address-cells = <1>; | |
| 70 | #size-cells = <0>; | |
| 71 | ||
| 72 | ckil { | |
| 73 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
| 4b2b4043 | 74 | #clock-cells = <0>; |
| 73d2b4cd SG |
75 | clock-frequency = <32768>; |
| 76 | }; | |
| 77 | ||
| 78 | ckih1 { | |
| 79 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
| 4b2b4043 | 80 | #clock-cells = <0>; |
| 73d2b4cd SG |
81 | clock-frequency = <22579200>; |
| 82 | }; | |
| 83 | ||
| 84 | ckih2 { | |
| 85 | compatible = "fsl,imx-ckih2", "fixed-clock"; | |
| 4b2b4043 | 86 | #clock-cells = <0>; |
| 73d2b4cd SG |
87 | clock-frequency = <0>; |
| 88 | }; | |
| 89 | ||
| 90 | osc { | |
| 91 | compatible = "fsl,imx-osc", "fixed-clock"; | |
| 4b2b4043 | 92 | #clock-cells = <0>; |
| 73d2b4cd SG |
93 | clock-frequency = <24000000>; |
| 94 | }; | |
| 95 | }; | |
| 96 | ||
| 97 | soc { | |
| 98 | #address-cells = <1>; | |
| 99 | #size-cells = <1>; | |
| 100 | compatible = "simple-bus"; | |
| 101 | interrupt-parent = <&tzic>; | |
| 102 | ranges; | |
| 103 | ||
| 7affee43 MV |
104 | sata: sata@10000000 { |
| 105 | compatible = "fsl,imx53-ahci"; | |
| 106 | reg = <0x10000000 0x1000>; | |
| 107 | interrupts = <28>; | |
| 108 | clocks = <&clks IMX5_CLK_SATA_GATE>, | |
| 109 | <&clks IMX5_CLK_SATA_REF>, | |
| 110 | <&clks IMX5_CLK_AHB>; | |
| 02578153 | 111 | clock-names = "sata", "sata_ref", "ahb"; |
| 7affee43 MV |
112 | status = "disabled"; |
| 113 | }; | |
| 114 | ||
| abed9a6b | 115 | ipu: ipu@18000000 { |
| e05c8c9a PZ |
116 | #address-cells = <1>; |
| 117 | #size-cells = <0>; | |
| abed9a6b | 118 | compatible = "fsl,imx53-ipu"; |
| 6d66da89 | 119 | reg = <0x18000000 0x08000000>; |
| abed9a6b | 120 | interrupts = <11 10>; |
| 564695dd LS |
121 | clocks = <&clks IMX5_CLK_IPU_GATE>, |
| 122 | <&clks IMX5_CLK_IPU_DI0_GATE>, | |
| 123 | <&clks IMX5_CLK_IPU_DI1_GATE>; | |
| 4438a6a1 | 124 | clock-names = "bus", "di0", "di1"; |
| 8d84c374 | 125 | resets = <&src 2>; |
| e05c8c9a PZ |
126 | |
| 127 | ipu_di0: port@2 { | |
| 128 | #address-cells = <1>; | |
| 129 | #size-cells = <0>; | |
| 130 | reg = <2>; | |
| 131 | ||
| 132 | ipu_di0_disp0: endpoint@0 { | |
| 133 | reg = <0>; | |
| 134 | }; | |
| 135 | ||
| 136 | ipu_di0_lvds0: endpoint@1 { | |
| 137 | reg = <1>; | |
| 138 | remote-endpoint = <&lvds0_in>; | |
| 139 | }; | |
| 140 | }; | |
| 141 | ||
| 142 | ipu_di1: port@3 { | |
| 143 | #address-cells = <1>; | |
| 144 | #size-cells = <0>; | |
| 145 | reg = <3>; | |
| 146 | ||
| 147 | ipu_di1_disp1: endpoint@0 { | |
| 148 | reg = <0>; | |
| 149 | }; | |
| 150 | ||
| 151 | ipu_di1_lvds1: endpoint@1 { | |
| 152 | reg = <1>; | |
| 153 | remote-endpoint = <&lvds1_in>; | |
| 154 | }; | |
| 155 | ||
| 156 | ipu_di1_tve: endpoint@2 { | |
| 157 | reg = <2>; | |
| 158 | remote-endpoint = <&tve_in>; | |
| 159 | }; | |
| 160 | }; | |
| abed9a6b SH |
161 | }; |
| 162 | ||
| 73d2b4cd SG |
163 | aips@50000000 { /* AIPS1 */ |
| 164 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 165 | #address-cells = <1>; | |
| 166 | #size-cells = <1>; | |
| 167 | reg = <0x50000000 0x10000000>; | |
| 168 | ranges; | |
| 169 | ||
| 170 | spba@50000000 { | |
| 171 | compatible = "fsl,spba-bus", "simple-bus"; | |
| 172 | #address-cells = <1>; | |
| 173 | #size-cells = <1>; | |
| 174 | reg = <0x50000000 0x40000>; | |
| 175 | ranges; | |
| 176 | ||
| 7b7d6727 | 177 | esdhc1: esdhc@50004000 { |
| 73d2b4cd SG |
178 | compatible = "fsl,imx53-esdhc"; |
| 179 | reg = <0x50004000 0x4000>; | |
| 180 | interrupts = <1>; | |
| 564695dd LS |
181 | clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, |
| 182 | <&clks IMX5_CLK_DUMMY>, | |
| 183 | <&clks IMX5_CLK_ESDHC1_PER_GATE>; | |
| f40f38d1 | 184 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 185 | bus-width = <4>; |
| 73d2b4cd SG |
186 | status = "disabled"; |
| 187 | }; | |
| 188 | ||
| 7b7d6727 | 189 | esdhc2: esdhc@50008000 { |
| 73d2b4cd SG |
190 | compatible = "fsl,imx53-esdhc"; |
| 191 | reg = <0x50008000 0x4000>; | |
| 192 | interrupts = <2>; | |
| 564695dd LS |
193 | clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, |
| 194 | <&clks IMX5_CLK_DUMMY>, | |
| 195 | <&clks IMX5_CLK_ESDHC2_PER_GATE>; | |
| f40f38d1 | 196 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 197 | bus-width = <4>; |
| 73d2b4cd SG |
198 | status = "disabled"; |
| 199 | }; | |
| 200 | ||
| 0c456cfa | 201 | uart3: serial@5000c000 { |
| 73d2b4cd SG |
202 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 203 | reg = <0x5000c000 0x4000>; | |
| 204 | interrupts = <33>; | |
| 564695dd LS |
205 | clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, |
| 206 | <&clks IMX5_CLK_UART3_PER_GATE>; | |
| f40f38d1 | 207 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
208 | status = "disabled"; |
| 209 | }; | |
| 210 | ||
| 7b7d6727 | 211 | ecspi1: ecspi@50010000 { |
| 73d2b4cd SG |
212 | #address-cells = <1>; |
| 213 | #size-cells = <0>; | |
| 214 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
| 215 | reg = <0x50010000 0x4000>; | |
| 216 | interrupts = <36>; | |
| 564695dd LS |
217 | clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, |
| 218 | <&clks IMX5_CLK_ECSPI1_PER_GATE>; | |
| f40f38d1 | 219 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
220 | status = "disabled"; |
| 221 | }; | |
| 222 | ||
| ffc505c0 | 223 | ssi2: ssi@50014000 { |
| 28f93d0b MP |
224 | compatible = "fsl,imx53-ssi", |
| 225 | "fsl,imx51-ssi", | |
| 226 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
227 | reg = <0x50014000 0x4000>; |
| 228 | interrupts = <30>; | |
| 564695dd | 229 | clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; |
| 5da826ab SG |
230 | dmas = <&sdma 24 1 0>, |
| 231 | <&sdma 25 1 0>; | |
| 232 | dma-names = "rx", "tx"; | |
| ffc505c0 | 233 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
234 | status = "disabled"; |
| 235 | }; | |
| 236 | ||
| 7b7d6727 | 237 | esdhc3: esdhc@50020000 { |
| 73d2b4cd SG |
238 | compatible = "fsl,imx53-esdhc"; |
| 239 | reg = <0x50020000 0x4000>; | |
| 240 | interrupts = <3>; | |
| 564695dd LS |
241 | clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, |
| 242 | <&clks IMX5_CLK_DUMMY>, | |
| 243 | <&clks IMX5_CLK_ESDHC3_PER_GATE>; | |
| f40f38d1 | 244 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 245 | bus-width = <4>; |
| 73d2b4cd SG |
246 | status = "disabled"; |
| 247 | }; | |
| 248 | ||
| 7b7d6727 | 249 | esdhc4: esdhc@50024000 { |
| 73d2b4cd SG |
250 | compatible = "fsl,imx53-esdhc"; |
| 251 | reg = <0x50024000 0x4000>; | |
| 252 | interrupts = <4>; | |
| 564695dd LS |
253 | clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, |
| 254 | <&clks IMX5_CLK_DUMMY>, | |
| 255 | <&clks IMX5_CLK_ESDHC4_PER_GATE>; | |
| f40f38d1 | 256 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 257 | bus-width = <4>; |
| 73d2b4cd SG |
258 | status = "disabled"; |
| 259 | }; | |
| 260 | }; | |
| 261 | ||
| ac08281e ST |
262 | aipstz1: bridge@53f00000 { |
| 263 | compatible = "fsl,imx53-aipstz"; | |
| 264 | reg = <0x53f00000 0x60>; | |
| 265 | }; | |
| 266 | ||
| a79025c4 MG |
267 | usbphy0: usbphy@0 { |
| 268 | compatible = "usb-nop-xceiv"; | |
| 564695dd | 269 | clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; |
| a79025c4 MG |
270 | clock-names = "main_clk"; |
| 271 | status = "okay"; | |
| 272 | }; | |
| 273 | ||
| 274 | usbphy1: usbphy@1 { | |
| 275 | compatible = "usb-nop-xceiv"; | |
| 564695dd | 276 | clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; |
| a79025c4 MG |
277 | clock-names = "main_clk"; |
| 278 | status = "okay"; | |
| 279 | }; | |
| 280 | ||
| 7b7d6727 | 281 | usbotg: usb@53f80000 { |
| 212d0b83 MG |
282 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 283 | reg = <0x53f80000 0x0200>; | |
| 284 | interrupts = <18>; | |
| 564695dd | 285 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 286 | fsl,usbmisc = <&usbmisc 0>; |
| a79025c4 | 287 | fsl,usbphy = <&usbphy0>; |
| 212d0b83 MG |
288 | status = "disabled"; |
| 289 | }; | |
| 290 | ||
| 7b7d6727 | 291 | usbh1: usb@53f80200 { |
| 212d0b83 MG |
292 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 293 | reg = <0x53f80200 0x0200>; | |
| 294 | interrupts = <14>; | |
| 564695dd | 295 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 296 | fsl,usbmisc = <&usbmisc 1>; |
| a79025c4 | 297 | fsl,usbphy = <&usbphy1>; |
| 212d0b83 MG |
298 | status = "disabled"; |
| 299 | }; | |
| 300 | ||
| 7b7d6727 | 301 | usbh2: usb@53f80400 { |
| 212d0b83 MG |
302 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 303 | reg = <0x53f80400 0x0200>; | |
| 304 | interrupts = <16>; | |
| 564695dd | 305 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 306 | fsl,usbmisc = <&usbmisc 2>; |
| 212d0b83 MG |
307 | status = "disabled"; |
| 308 | }; | |
| 309 | ||
| 7b7d6727 | 310 | usbh3: usb@53f80600 { |
| 212d0b83 MG |
311 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 312 | reg = <0x53f80600 0x0200>; | |
| 313 | interrupts = <17>; | |
| 564695dd | 314 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 315 | fsl,usbmisc = <&usbmisc 3>; |
| 212d0b83 MG |
316 | status = "disabled"; |
| 317 | }; | |
| 318 | ||
| a5735021 MG |
319 | usbmisc: usbmisc@53f80800 { |
| 320 | #index-cells = <1>; | |
| 321 | compatible = "fsl,imx53-usbmisc"; | |
| 322 | reg = <0x53f80800 0x200>; | |
| 564695dd | 323 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 MG |
324 | }; |
| 325 | ||
| 4d191868 | 326 | gpio1: gpio@53f84000 { |
| aeb27748 | 327 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
328 | reg = <0x53f84000 0x4000>; |
| 329 | interrupts = <50 51>; | |
| 330 | gpio-controller; | |
| 331 | #gpio-cells = <2>; | |
| 332 | interrupt-controller; | |
| 88cde8b7 | 333 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
334 | }; |
| 335 | ||
| 4d191868 | 336 | gpio2: gpio@53f88000 { |
| aeb27748 | 337 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
338 | reg = <0x53f88000 0x4000>; |
| 339 | interrupts = <52 53>; | |
| 340 | gpio-controller; | |
| 341 | #gpio-cells = <2>; | |
| 342 | interrupt-controller; | |
| 88cde8b7 | 343 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
344 | }; |
| 345 | ||
| 4d191868 | 346 | gpio3: gpio@53f8c000 { |
| aeb27748 | 347 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
348 | reg = <0x53f8c000 0x4000>; |
| 349 | interrupts = <54 55>; | |
| 350 | gpio-controller; | |
| 351 | #gpio-cells = <2>; | |
| 352 | interrupt-controller; | |
| 88cde8b7 | 353 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
354 | }; |
| 355 | ||
| 4d191868 | 356 | gpio4: gpio@53f90000 { |
| aeb27748 | 357 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
358 | reg = <0x53f90000 0x4000>; |
| 359 | interrupts = <56 57>; | |
| 360 | gpio-controller; | |
| 361 | #gpio-cells = <2>; | |
| 362 | interrupt-controller; | |
| 88cde8b7 | 363 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
364 | }; |
| 365 | ||
| 675e4d03 RL |
366 | kpp: kpp@53f94000 { |
| 367 | compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; | |
| 368 | reg = <0x53f94000 0x4000>; | |
| 369 | interrupts = <60>; | |
| 564695dd | 370 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 675e4d03 RL |
371 | status = "disabled"; |
| 372 | }; | |
| 373 | ||
| 7b7d6727 | 374 | wdog1: wdog@53f98000 { |
| 73d2b4cd SG |
375 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 376 | reg = <0x53f98000 0x4000>; | |
| 377 | interrupts = <58>; | |
| 564695dd | 378 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 73d2b4cd SG |
379 | }; |
| 380 | ||
| 7b7d6727 | 381 | wdog2: wdog@53f9c000 { |
| 73d2b4cd SG |
382 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 383 | reg = <0x53f9c000 0x4000>; | |
| 384 | interrupts = <59>; | |
| 564695dd | 385 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 73d2b4cd SG |
386 | status = "disabled"; |
| 387 | }; | |
| 388 | ||
| cc8aae9b SH |
389 | gpt: timer@53fa0000 { |
| 390 | compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; | |
| 391 | reg = <0x53fa0000 0x4000>; | |
| 392 | interrupts = <39>; | |
| 564695dd LS |
393 | clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, |
| 394 | <&clks IMX5_CLK_GPT_HF_GATE>; | |
| cc8aae9b SH |
395 | clock-names = "ipg", "per"; |
| 396 | }; | |
| 397 | ||
| 7b7d6727 | 398 | iomuxc: iomuxc@53fa8000 { |
| 5be03a7b SG |
399 | compatible = "fsl,imx53-iomuxc"; |
| 400 | reg = <0x53fa8000 0x4000>; | |
| 5be03a7b SG |
401 | }; |
| 402 | ||
| 5af9f143 PZ |
403 | gpr: iomuxc-gpr@53fa8000 { |
| 404 | compatible = "fsl,imx53-iomuxc-gpr", "syscon"; | |
| 405 | reg = <0x53fa8000 0xc>; | |
| 406 | }; | |
| 407 | ||
| 420714aa PZ |
408 | ldb: ldb@53fa8008 { |
| 409 | #address-cells = <1>; | |
| 410 | #size-cells = <0>; | |
| 411 | compatible = "fsl,imx53-ldb"; | |
| 412 | reg = <0x53fa8008 0x4>; | |
| 413 | gpr = <&gpr>; | |
| 564695dd LS |
414 | clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, |
| 415 | <&clks IMX5_CLK_LDB_DI1_SEL>, | |
| 416 | <&clks IMX5_CLK_IPU_DI0_SEL>, | |
| 417 | <&clks IMX5_CLK_IPU_DI1_SEL>, | |
| 418 | <&clks IMX5_CLK_LDB_DI0_GATE>, | |
| 419 | <&clks IMX5_CLK_LDB_DI1_GATE>; | |
| 420714aa PZ |
420 | clock-names = "di0_pll", "di1_pll", |
| 421 | "di0_sel", "di1_sel", | |
| 422 | "di0", "di1"; | |
| 423 | status = "disabled"; | |
| 424 | ||
| 425 | lvds-channel@0 { | |
| 426 | reg = <0>; | |
| 420714aa | 427 | status = "disabled"; |
| e05c8c9a PZ |
428 | |
| 429 | port { | |
| 430 | lvds0_in: endpoint { | |
| 431 | remote-endpoint = <&ipu_di0_lvds0>; | |
| 432 | }; | |
| 433 | }; | |
| 420714aa PZ |
434 | }; |
| 435 | ||
| 436 | lvds-channel@1 { | |
| 437 | reg = <1>; | |
| 420714aa | 438 | status = "disabled"; |
| e05c8c9a PZ |
439 | |
| 440 | port { | |
| 441 | lvds1_in: endpoint { | |
| fa1746ae | 442 | remote-endpoint = <&ipu_di1_lvds1>; |
| e05c8c9a PZ |
443 | }; |
| 444 | }; | |
| 420714aa PZ |
445 | }; |
| 446 | }; | |
| 447 | ||
| 9ae90afa SH |
448 | pwm1: pwm@53fb4000 { |
| 449 | #pwm-cells = <2>; | |
| 450 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
| 451 | reg = <0x53fb4000 0x4000>; | |
| 564695dd LS |
452 | clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, |
| 453 | <&clks IMX5_CLK_PWM1_HF_GATE>; | |
| 9ae90afa SH |
454 | clock-names = "ipg", "per"; |
| 455 | interrupts = <61>; | |
| 456 | }; | |
| 457 | ||
| 458 | pwm2: pwm@53fb8000 { | |
| 459 | #pwm-cells = <2>; | |
| 460 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
| 461 | reg = <0x53fb8000 0x4000>; | |
| 564695dd LS |
462 | clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, |
| 463 | <&clks IMX5_CLK_PWM2_HF_GATE>; | |
| 9ae90afa SH |
464 | clock-names = "ipg", "per"; |
| 465 | interrupts = <94>; | |
| 466 | }; | |
| 467 | ||
| 0c456cfa | 468 | uart1: serial@53fbc000 { |
| 73d2b4cd SG |
469 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 470 | reg = <0x53fbc000 0x4000>; | |
| 471 | interrupts = <31>; | |
| 564695dd LS |
472 | clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, |
| 473 | <&clks IMX5_CLK_UART1_PER_GATE>; | |
| f40f38d1 | 474 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
475 | status = "disabled"; |
| 476 | }; | |
| 477 | ||
| 0c456cfa | 478 | uart2: serial@53fc0000 { |
| 73d2b4cd SG |
479 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 480 | reg = <0x53fc0000 0x4000>; | |
| 481 | interrupts = <32>; | |
| 564695dd LS |
482 | clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, |
| 483 | <&clks IMX5_CLK_UART2_PER_GATE>; | |
| f40f38d1 | 484 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
485 | status = "disabled"; |
| 486 | }; | |
| 487 | ||
| a9d1f924 ST |
488 | can1: can@53fc8000 { |
| 489 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | |
| 490 | reg = <0x53fc8000 0x4000>; | |
| 491 | interrupts = <82>; | |
| 564695dd LS |
492 | clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, |
| 493 | <&clks IMX5_CLK_CAN1_SERIAL_GATE>; | |
| f40f38d1 | 494 | clock-names = "ipg", "per"; |
| a9d1f924 ST |
495 | status = "disabled"; |
| 496 | }; | |
| 497 | ||
| 498 | can2: can@53fcc000 { | |
| 499 | compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; | |
| 500 | reg = <0x53fcc000 0x4000>; | |
| 501 | interrupts = <83>; | |
| 564695dd LS |
502 | clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, |
| 503 | <&clks IMX5_CLK_CAN2_SERIAL_GATE>; | |
| f40f38d1 | 504 | clock-names = "ipg", "per"; |
| a9d1f924 ST |
505 | status = "disabled"; |
| 506 | }; | |
| 507 | ||
| 8d84c374 PZ |
508 | src: src@53fd0000 { |
| 509 | compatible = "fsl,imx53-src", "fsl,imx51-src"; | |
| 510 | reg = <0x53fd0000 0x4000>; | |
| 511 | #reset-cells = <1>; | |
| 512 | }; | |
| 513 | ||
| f40f38d1 FE |
514 | clks: ccm@53fd4000{ |
| 515 | compatible = "fsl,imx53-ccm"; | |
| 516 | reg = <0x53fd4000 0x4000>; | |
| 517 | interrupts = <0 71 0x04 0 72 0x04>; | |
| 518 | #clock-cells = <1>; | |
| 519 | }; | |
| 520 | ||
| 4d191868 | 521 | gpio5: gpio@53fdc000 { |
| aeb27748 | 522 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
523 | reg = <0x53fdc000 0x4000>; |
| 524 | interrupts = <103 104>; | |
| 525 | gpio-controller; | |
| 526 | #gpio-cells = <2>; | |
| 527 | interrupt-controller; | |
| 88cde8b7 | 528 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
529 | }; |
| 530 | ||
| 4d191868 | 531 | gpio6: gpio@53fe0000 { |
| aeb27748 | 532 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
533 | reg = <0x53fe0000 0x4000>; |
| 534 | interrupts = <105 106>; | |
| 535 | gpio-controller; | |
| 536 | #gpio-cells = <2>; | |
| 537 | interrupt-controller; | |
| 88cde8b7 | 538 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
539 | }; |
| 540 | ||
| 4d191868 | 541 | gpio7: gpio@53fe4000 { |
| aeb27748 | 542 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
543 | reg = <0x53fe4000 0x4000>; |
| 544 | interrupts = <107 108>; | |
| 545 | gpio-controller; | |
| 546 | #gpio-cells = <2>; | |
| 547 | interrupt-controller; | |
| 88cde8b7 | 548 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
549 | }; |
| 550 | ||
| 7b7d6727 | 551 | i2c3: i2c@53fec000 { |
| 73d2b4cd SG |
552 | #address-cells = <1>; |
| 553 | #size-cells = <0>; | |
| 5bdfba29 | 554 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
555 | reg = <0x53fec000 0x4000>; |
| 556 | interrupts = <64>; | |
| 564695dd | 557 | clocks = <&clks IMX5_CLK_I2C3_GATE>; |
| 73d2b4cd SG |
558 | status = "disabled"; |
| 559 | }; | |
| 560 | ||
| 0c456cfa | 561 | uart4: serial@53ff0000 { |
| 73d2b4cd SG |
562 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 563 | reg = <0x53ff0000 0x4000>; | |
| 564 | interrupts = <13>; | |
| 564695dd LS |
565 | clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, |
| 566 | <&clks IMX5_CLK_UART4_PER_GATE>; | |
| f40f38d1 | 567 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
568 | status = "disabled"; |
| 569 | }; | |
| 570 | }; | |
| 571 | ||
| 572 | aips@60000000 { /* AIPS2 */ | |
| 573 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 574 | #address-cells = <1>; | |
| 575 | #size-cells = <1>; | |
| 576 | reg = <0x60000000 0x10000000>; | |
| 577 | ranges; | |
| 578 | ||
| ac08281e ST |
579 | aipstz2: bridge@63f00000 { |
| 580 | compatible = "fsl,imx53-aipstz"; | |
| 581 | reg = <0x63f00000 0x60>; | |
| 582 | }; | |
| 583 | ||
| 4f3b2a41 SH |
584 | iim: iim@63f98000 { |
| 585 | compatible = "fsl,imx53-iim", "fsl,imx27-iim"; | |
| 586 | reg = <0x63f98000 0x4000>; | |
| 587 | interrupts = <69>; | |
| 564695dd | 588 | clocks = <&clks IMX5_CLK_IIM_GATE>; |
| 4f3b2a41 SH |
589 | }; |
| 590 | ||
| 0c456cfa | 591 | uart5: serial@63f90000 { |
| 73d2b4cd SG |
592 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 593 | reg = <0x63f90000 0x4000>; | |
| 594 | interrupts = <86>; | |
| 564695dd LS |
595 | clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, |
| 596 | <&clks IMX5_CLK_UART5_PER_GATE>; | |
| f40f38d1 | 597 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
598 | status = "disabled"; |
| 599 | }; | |
| 600 | ||
| a82b7b9c MF |
601 | owire: owire@63fa4000 { |
| 602 | compatible = "fsl,imx53-owire", "fsl,imx21-owire"; | |
| 603 | reg = <0x63fa4000 0x4000>; | |
| 564695dd | 604 | clocks = <&clks IMX5_CLK_OWIRE_GATE>; |
| a82b7b9c MF |
605 | status = "disabled"; |
| 606 | }; | |
| 607 | ||
| 7b7d6727 | 608 | ecspi2: ecspi@63fac000 { |
| 73d2b4cd SG |
609 | #address-cells = <1>; |
| 610 | #size-cells = <0>; | |
| 611 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
| 612 | reg = <0x63fac000 0x4000>; | |
| 613 | interrupts = <37>; | |
| 564695dd LS |
614 | clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, |
| 615 | <&clks IMX5_CLK_ECSPI2_PER_GATE>; | |
| f40f38d1 | 616 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
617 | status = "disabled"; |
| 618 | }; | |
| 619 | ||
| 7b7d6727 | 620 | sdma: sdma@63fb0000 { |
| 73d2b4cd SG |
621 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; |
| 622 | reg = <0x63fb0000 0x4000>; | |
| 623 | interrupts = <6>; | |
| 564695dd LS |
624 | clocks = <&clks IMX5_CLK_SDMA_GATE>, |
| 625 | <&clks IMX5_CLK_SDMA_GATE>; | |
| f40f38d1 | 626 | clock-names = "ipg", "ahb"; |
| fb72bb21 | 627 | #dma-cells = <3>; |
| 7e4f0365 | 628 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; |
| 73d2b4cd SG |
629 | }; |
| 630 | ||
| 7b7d6727 | 631 | cspi: cspi@63fc0000 { |
| 73d2b4cd SG |
632 | #address-cells = <1>; |
| 633 | #size-cells = <0>; | |
| 634 | compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; | |
| 635 | reg = <0x63fc0000 0x4000>; | |
| 636 | interrupts = <38>; | |
| 564695dd LS |
637 | clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, |
| 638 | <&clks IMX5_CLK_CSPI_IPG_GATE>; | |
| f40f38d1 | 639 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
640 | status = "disabled"; |
| 641 | }; | |
| 642 | ||
| 7b7d6727 | 643 | i2c2: i2c@63fc4000 { |
| 73d2b4cd SG |
644 | #address-cells = <1>; |
| 645 | #size-cells = <0>; | |
| 5bdfba29 | 646 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
647 | reg = <0x63fc4000 0x4000>; |
| 648 | interrupts = <63>; | |
| 564695dd | 649 | clocks = <&clks IMX5_CLK_I2C2_GATE>; |
| 73d2b4cd SG |
650 | status = "disabled"; |
| 651 | }; | |
| 652 | ||
| 7b7d6727 | 653 | i2c1: i2c@63fc8000 { |
| 73d2b4cd SG |
654 | #address-cells = <1>; |
| 655 | #size-cells = <0>; | |
| 5bdfba29 | 656 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
657 | reg = <0x63fc8000 0x4000>; |
| 658 | interrupts = <62>; | |
| 564695dd | 659 | clocks = <&clks IMX5_CLK_I2C1_GATE>; |
| 73d2b4cd SG |
660 | status = "disabled"; |
| 661 | }; | |
| 662 | ||
| ffc505c0 | 663 | ssi1: ssi@63fcc000 { |
| 28f93d0b MP |
664 | compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", |
| 665 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
666 | reg = <0x63fcc000 0x4000>; |
| 667 | interrupts = <29>; | |
| 564695dd | 668 | clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; |
| 5da826ab SG |
669 | dmas = <&sdma 28 0 0>, |
| 670 | <&sdma 29 0 0>; | |
| 671 | dma-names = "rx", "tx"; | |
| ffc505c0 | 672 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
673 | status = "disabled"; |
| 674 | }; | |
| 675 | ||
| 7b7d6727 | 676 | audmux: audmux@63fd0000 { |
| ffc505c0 SG |
677 | compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; |
| 678 | reg = <0x63fd0000 0x4000>; | |
| 679 | status = "disabled"; | |
| 680 | }; | |
| 681 | ||
| 7b7d6727 | 682 | nfc: nand@63fdb000 { |
| 75453a08 SH |
683 | compatible = "fsl,imx53-nand"; |
| 684 | reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; | |
| 685 | interrupts = <8>; | |
| 564695dd | 686 | clocks = <&clks IMX5_CLK_NFC_GATE>; |
| 75453a08 SH |
687 | status = "disabled"; |
| 688 | }; | |
| 689 | ||
| ffc505c0 | 690 | ssi3: ssi@63fe8000 { |
| 28f93d0b MP |
691 | compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", |
| 692 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
693 | reg = <0x63fe8000 0x4000>; |
| 694 | interrupts = <96>; | |
| 564695dd | 695 | clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; |
| 5da826ab SG |
696 | dmas = <&sdma 46 0 0>, |
| 697 | <&sdma 47 0 0>; | |
| 698 | dma-names = "rx", "tx"; | |
| ffc505c0 | 699 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
700 | status = "disabled"; |
| 701 | }; | |
| 702 | ||
| 7b7d6727 | 703 | fec: ethernet@63fec000 { |
| 73d2b4cd SG |
704 | compatible = "fsl,imx53-fec", "fsl,imx25-fec"; |
| 705 | reg = <0x63fec000 0x4000>; | |
| 706 | interrupts = <87>; | |
| 564695dd LS |
707 | clocks = <&clks IMX5_CLK_FEC_GATE>, |
| 708 | <&clks IMX5_CLK_FEC_GATE>, | |
| 709 | <&clks IMX5_CLK_FEC_GATE>; | |
| f40f38d1 | 710 | clock-names = "ipg", "ahb", "ptp"; |
| 73d2b4cd SG |
711 | status = "disabled"; |
| 712 | }; | |
| 19194c2b PZ |
713 | |
| 714 | tve: tve@63ff0000 { | |
| 715 | compatible = "fsl,imx53-tve"; | |
| 716 | reg = <0x63ff0000 0x1000>; | |
| 717 | interrupts = <92>; | |
| 564695dd LS |
718 | clocks = <&clks IMX5_CLK_TVE_GATE>, |
| 719 | <&clks IMX5_CLK_IPU_DI1_SEL>; | |
| 19194c2b | 720 | clock-names = "tve", "di_sel"; |
| 19194c2b | 721 | status = "disabled"; |
| e05c8c9a PZ |
722 | |
| 723 | port { | |
| 724 | tve_in: endpoint { | |
| 725 | remote-endpoint = <&ipu_di1_tve>; | |
| 726 | }; | |
| 727 | }; | |
| 19194c2b | 728 | }; |
| fbf970f6 FE |
729 | |
| 730 | vpu: vpu@63ff4000 { | |
| 731 | compatible = "fsl,imx53-vpu"; | |
| 732 | reg = <0x63ff4000 0x1000>; | |
| 733 | interrupts = <9>; | |
| 564695dd LS |
734 | clocks = <&clks IMX5_CLK_VPU_GATE>, |
| 735 | <&clks IMX5_CLK_VPU_GATE>; | |
| fbf970f6 | 736 | clock-names = "per", "ahb"; |
| b1e2e546 | 737 | resets = <&src 1>; |
| fbf970f6 | 738 | iram = <&ocram>; |
| fbf970f6 | 739 | }; |
| 73d2b4cd | 740 | }; |
| 481fbe13 PZ |
741 | |
| 742 | ocram: sram@f8000000 { | |
| 743 | compatible = "mmio-sram"; | |
| 744 | reg = <0xf8000000 0x20000>; | |
| 564695dd | 745 | clocks = <&clks IMX5_CLK_OCRAM>; |
| 481fbe13 | 746 | }; |
| 73d2b4cd SG |
747 | }; |
| 748 | }; |