projects / mirror_ubuntu-hirsute-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| f46af111 FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | // | |
| 3 | // Copyright 2011 Freescale Semiconductor, Inc. | |
| 4 | // Copyright 2011 Linaro Ltd. | |
| 73d2b4cd | 5 | |
| e1641531 | 6 | #include "imx53-pinfunc.h" |
| 564695dd | 7 | #include <dt-bindings/clock/imx5-clock.h> |
| 4e05a7af DC |
8 | #include <dt-bindings/gpio/gpio.h> |
| 9 | #include <dt-bindings/input/input.h> | |
| 34adba71 | 10 | #include <dt-bindings/interrupt-controller/irq.h> |
| 73d2b4cd SG |
11 | |
| 12 | / { | |
| 7f107887 FE |
13 | #address-cells = <1>; |
| 14 | #size-cells = <1>; | |
| a971c554 FE |
15 | /* |
| 16 | * The decompressor and also some bootloaders rely on a | |
| 17 | * pre-existing /chosen node to be available to insert the | |
| 18 | * command line and merge other ATAGS info. | |
| a971c554 FE |
19 | */ |
| 20 | chosen {}; | |
| 7f107887 | 21 | |
| 73d2b4cd | 22 | aliases { |
| 22970070 | 23 | ethernet0 = &fec; |
| 5230f8fe SG |
24 | gpio0 = &gpio1; |
| 25 | gpio1 = &gpio2; | |
| 26 | gpio2 = &gpio3; | |
| 27 | gpio3 = &gpio4; | |
| 28 | gpio4 = &gpio5; | |
| 29 | gpio5 = &gpio6; | |
| 30 | gpio6 = &gpio7; | |
| c60dc1d1 PZ |
31 | i2c0 = &i2c1; |
| 32 | i2c1 = &i2c2; | |
| 33 | i2c2 = &i2c3; | |
| c63d06de SH |
34 | mmc0 = &esdhc1; |
| 35 | mmc1 = &esdhc2; | |
| 36 | mmc2 = &esdhc3; | |
| 37 | mmc3 = &esdhc4; | |
| cf4e577e SH |
38 | serial0 = &uart1; |
| 39 | serial1 = &uart2; | |
| 40 | serial2 = &uart3; | |
| 41 | serial3 = &uart4; | |
| 42 | serial4 = &uart5; | |
| 43 | spi0 = &ecspi1; | |
| 44 | spi1 = &ecspi2; | |
| 45 | spi2 = &cspi; | |
| 73d2b4cd SG |
46 | }; |
| 47 | ||
| 070bd7e4 FE |
48 | cpus { |
| 49 | #address-cells = <1>; | |
| 50 | #size-cells = <0>; | |
| 791f4166 | 51 | cpu0: cpu@0 { |
| 070bd7e4 FE |
52 | device_type = "cpu"; |
| 53 | compatible = "arm,cortex-a8"; | |
| 54 | reg = <0x0>; | |
| 791f4166 LS |
55 | clocks = <&clks IMX5_CLK_ARM>; |
| 56 | clock-latency = <61036>; | |
| 57 | voltage-tolerance = <5>; | |
| 58 | operating-points = < | |
| 59 | /* kHz */ | |
| 60 | 166666 850000 | |
| 61 | 400000 900000 | |
| 62 | 800000 1050000 | |
| 63 | 1000000 1200000 | |
| 64 | 1200000 1300000 | |
| 65 | >; | |
| 070bd7e4 FE |
66 | }; |
| 67 | }; | |
| 68 | ||
| e05c8c9a PZ |
69 | display-subsystem { |
| 70 | compatible = "fsl,imx-display-subsystem"; | |
| 71 | ports = <&ipu_di0>, <&ipu_di1>; | |
| 72 | }; | |
| 73 | ||
| 8dccafaa | 74 | tzic: tz-interrupt-controller@fffc000 { |
| 73d2b4cd SG |
75 | compatible = "fsl,imx53-tzic", "fsl,tzic"; |
| 76 | interrupt-controller; | |
| 77 | #interrupt-cells = <1>; | |
| 78 | reg = <0x0fffc000 0x4000>; | |
| 79 | }; | |
| 80 | ||
| 81 | clocks { | |
| 73d2b4cd SG |
82 | ckil { |
| 83 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
| 4b2b4043 | 84 | #clock-cells = <0>; |
| 73d2b4cd SG |
85 | clock-frequency = <32768>; |
| 86 | }; | |
| 87 | ||
| 88 | ckih1 { | |
| 89 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
| 4b2b4043 | 90 | #clock-cells = <0>; |
| 73d2b4cd SG |
91 | clock-frequency = <22579200>; |
| 92 | }; | |
| 93 | ||
| 94 | ckih2 { | |
| 95 | compatible = "fsl,imx-ckih2", "fixed-clock"; | |
| 4b2b4043 | 96 | #clock-cells = <0>; |
| 73d2b4cd SG |
97 | clock-frequency = <0>; |
| 98 | }; | |
| 99 | ||
| 100 | osc { | |
| 101 | compatible = "fsl,imx-osc", "fixed-clock"; | |
| 4b2b4043 | 102 | #clock-cells = <0>; |
| 73d2b4cd SG |
103 | clock-frequency = <24000000>; |
| 104 | }; | |
| 105 | }; | |
| 106 | ||
| 4a2190aa | 107 | pmu: pmu { |
| 5b232744 FE |
108 | compatible = "arm,cortex-a8-pmu"; |
| 109 | interrupt-parent = <&tzic>; | |
| 110 | interrupts = <77>; | |
| 111 | }; | |
| 112 | ||
| 113 | usbphy0: usbphy-0 { | |
| 114 | compatible = "usb-nop-xceiv"; | |
| 115 | clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; | |
| 116 | clock-names = "main_clk"; | |
| 117 | #phy-cells = <0>; | |
| 118 | status = "okay"; | |
| 119 | }; | |
| 120 | ||
| 121 | usbphy1: usbphy-1 { | |
| 122 | compatible = "usb-nop-xceiv"; | |
| 123 | clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; | |
| 124 | clock-names = "main_clk"; | |
| 125 | #phy-cells = <0>; | |
| 126 | status = "okay"; | |
| 127 | }; | |
| 128 | ||
| 73d2b4cd SG |
129 | soc { |
| 130 | #address-cells = <1>; | |
| 131 | #size-cells = <1>; | |
| 132 | compatible = "simple-bus"; | |
| 133 | interrupt-parent = <&tzic>; | |
| 134 | ranges; | |
| 135 | ||
| 7affee43 MV |
136 | sata: sata@10000000 { |
| 137 | compatible = "fsl,imx53-ahci"; | |
| 138 | reg = <0x10000000 0x1000>; | |
| 139 | interrupts = <28>; | |
| 140 | clocks = <&clks IMX5_CLK_SATA_GATE>, | |
| 141 | <&clks IMX5_CLK_SATA_REF>, | |
| 142 | <&clks IMX5_CLK_AHB>; | |
| 02578153 | 143 | clock-names = "sata", "sata_ref", "ahb"; |
| 7affee43 MV |
144 | status = "disabled"; |
| 145 | }; | |
| 146 | ||
| abed9a6b | 147 | ipu: ipu@18000000 { |
| e05c8c9a PZ |
148 | #address-cells = <1>; |
| 149 | #size-cells = <0>; | |
| abed9a6b | 150 | compatible = "fsl,imx53-ipu"; |
| 6d66da89 | 151 | reg = <0x18000000 0x08000000>; |
| abed9a6b | 152 | interrupts = <11 10>; |
| 564695dd | 153 | clocks = <&clks IMX5_CLK_IPU_GATE>, |
| 46311707 JT |
154 | <&clks IMX5_CLK_IPU_DI0_GATE>, |
| 155 | <&clks IMX5_CLK_IPU_DI1_GATE>; | |
| 4438a6a1 | 156 | clock-names = "bus", "di0", "di1"; |
| 8d84c374 | 157 | resets = <&src 2>; |
| e05c8c9a | 158 | |
| 2a8e583c FL |
159 | ipu_csi0: port@0 { |
| 160 | reg = <0>; | |
| 161 | }; | |
| 162 | ||
| 163 | ipu_csi1: port@1 { | |
| 164 | reg = <1>; | |
| 165 | }; | |
| 166 | ||
| e05c8c9a PZ |
167 | ipu_di0: port@2 { |
| 168 | #address-cells = <1>; | |
| 169 | #size-cells = <0>; | |
| 170 | reg = <2>; | |
| 171 | ||
| 172 | ipu_di0_disp0: endpoint@0 { | |
| 173 | reg = <0>; | |
| 174 | }; | |
| 175 | ||
| 176 | ipu_di0_lvds0: endpoint@1 { | |
| 177 | reg = <1>; | |
| 178 | remote-endpoint = <&lvds0_in>; | |
| 179 | }; | |
| 180 | }; | |
| 181 | ||
| 182 | ipu_di1: port@3 { | |
| 183 | #address-cells = <1>; | |
| 184 | #size-cells = <0>; | |
| 185 | reg = <3>; | |
| 186 | ||
| 187 | ipu_di1_disp1: endpoint@0 { | |
| 188 | reg = <0>; | |
| 189 | }; | |
| 190 | ||
| 191 | ipu_di1_lvds1: endpoint@1 { | |
| 192 | reg = <1>; | |
| 193 | remote-endpoint = <&lvds1_in>; | |
| 194 | }; | |
| 195 | ||
| 196 | ipu_di1_tve: endpoint@2 { | |
| 197 | reg = <2>; | |
| 198 | remote-endpoint = <&tve_in>; | |
| 199 | }; | |
| 200 | }; | |
| abed9a6b SH |
201 | }; |
| 202 | ||
| 006303d6 JM |
203 | gpu: gpu@30000000 { |
| 204 | compatible = "amd,imageon-200.0", "amd,imageon"; | |
| 205 | reg = <0x30000000 0x20000>; | |
| 206 | reg-names = "kgsl_3d0_reg_memory"; | |
| 207 | interrupts = <12>; | |
| 208 | interrupt-names = "kgsl_3d0_irq"; | |
| 209 | clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; | |
| 210 | clock-names = "core_clk", "mem_iface_clk"; | |
| 211 | }; | |
| 212 | ||
| 73d2b4cd SG |
213 | aips@50000000 { /* AIPS1 */ |
| 214 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 215 | #address-cells = <1>; | |
| 216 | #size-cells = <1>; | |
| 217 | reg = <0x50000000 0x10000000>; | |
| 218 | ranges; | |
| 219 | ||
| 220 | spba@50000000 { | |
| 221 | compatible = "fsl,spba-bus", "simple-bus"; | |
| 222 | #address-cells = <1>; | |
| 223 | #size-cells = <1>; | |
| 224 | reg = <0x50000000 0x40000>; | |
| 225 | ranges; | |
| 226 | ||
| 7b7d6727 | 227 | esdhc1: esdhc@50004000 { |
| 73d2b4cd SG |
228 | compatible = "fsl,imx53-esdhc"; |
| 229 | reg = <0x50004000 0x4000>; | |
| 230 | interrupts = <1>; | |
| 564695dd | 231 | clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, |
| 46311707 JT |
232 | <&clks IMX5_CLK_DUMMY>, |
| 233 | <&clks IMX5_CLK_ESDHC1_PER_GATE>; | |
| f40f38d1 | 234 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 235 | bus-width = <4>; |
| 73d2b4cd SG |
236 | status = "disabled"; |
| 237 | }; | |
| 238 | ||
| 7b7d6727 | 239 | esdhc2: esdhc@50008000 { |
| 73d2b4cd SG |
240 | compatible = "fsl,imx53-esdhc"; |
| 241 | reg = <0x50008000 0x4000>; | |
| 242 | interrupts = <2>; | |
| 564695dd | 243 | clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, |
| 46311707 JT |
244 | <&clks IMX5_CLK_DUMMY>, |
| 245 | <&clks IMX5_CLK_ESDHC2_PER_GATE>; | |
| f40f38d1 | 246 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 247 | bus-width = <4>; |
| 73d2b4cd SG |
248 | status = "disabled"; |
| 249 | }; | |
| 250 | ||
| 0c456cfa | 251 | uart3: serial@5000c000 { |
| 73d2b4cd SG |
252 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 253 | reg = <0x5000c000 0x4000>; | |
| 254 | interrupts = <33>; | |
| 564695dd | 255 | clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, |
| 46311707 | 256 | <&clks IMX5_CLK_UART3_PER_GATE>; |
| f40f38d1 | 257 | clock-names = "ipg", "per"; |
| d04eba90 FL |
258 | dmas = <&sdma 42 4 0>, <&sdma 43 4 0>; |
| 259 | dma-names = "rx", "tx"; | |
| 73d2b4cd SG |
260 | status = "disabled"; |
| 261 | }; | |
| 262 | ||
| 5a2ecf0d | 263 | ecspi1: spi@50010000 { |
| 73d2b4cd SG |
264 | #address-cells = <1>; |
| 265 | #size-cells = <0>; | |
| 266 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
| 267 | reg = <0x50010000 0x4000>; | |
| 268 | interrupts = <36>; | |
| 564695dd | 269 | clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, |
| 46311707 | 270 | <&clks IMX5_CLK_ECSPI1_PER_GATE>; |
| f40f38d1 | 271 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
272 | status = "disabled"; |
| 273 | }; | |
| 274 | ||
| ffc505c0 | 275 | ssi2: ssi@50014000 { |
| 6ff7f51e | 276 | #sound-dai-cells = <0>; |
| 28f93d0b MP |
277 | compatible = "fsl,imx53-ssi", |
| 278 | "fsl,imx51-ssi", | |
| 279 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
280 | reg = <0x50014000 0x4000>; |
| 281 | interrupts = <30>; | |
| 685570ab FE |
282 | clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, |
| 283 | <&clks IMX5_CLK_SSI2_ROOT_GATE>; | |
| 284 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
285 | dmas = <&sdma 24 1 0>, |
| 286 | <&sdma 25 1 0>; | |
| 287 | dma-names = "rx", "tx"; | |
| ffc505c0 | 288 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
289 | status = "disabled"; |
| 290 | }; | |
| 291 | ||
| 7b7d6727 | 292 | esdhc3: esdhc@50020000 { |
| 73d2b4cd SG |
293 | compatible = "fsl,imx53-esdhc"; |
| 294 | reg = <0x50020000 0x4000>; | |
| 295 | interrupts = <3>; | |
| 564695dd | 296 | clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, |
| 46311707 JT |
297 | <&clks IMX5_CLK_DUMMY>, |
| 298 | <&clks IMX5_CLK_ESDHC3_PER_GATE>; | |
| f40f38d1 | 299 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 300 | bus-width = <4>; |
| 73d2b4cd SG |
301 | status = "disabled"; |
| 302 | }; | |
| 303 | ||
| 7b7d6727 | 304 | esdhc4: esdhc@50024000 { |
| 73d2b4cd SG |
305 | compatible = "fsl,imx53-esdhc"; |
| 306 | reg = <0x50024000 0x4000>; | |
| 307 | interrupts = <4>; | |
| 564695dd | 308 | clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, |
| 46311707 JT |
309 | <&clks IMX5_CLK_DUMMY>, |
| 310 | <&clks IMX5_CLK_ESDHC4_PER_GATE>; | |
| f40f38d1 | 311 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 312 | bus-width = <4>; |
| 73d2b4cd SG |
313 | status = "disabled"; |
| 314 | }; | |
| 315 | }; | |
| 316 | ||
| ac08281e ST |
317 | aipstz1: bridge@53f00000 { |
| 318 | compatible = "fsl,imx53-aipstz"; | |
| 319 | reg = <0x53f00000 0x60>; | |
| 320 | }; | |
| 321 | ||
| 7b7d6727 | 322 | usbotg: usb@53f80000 { |
| 212d0b83 MG |
323 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 324 | reg = <0x53f80000 0x0200>; | |
| 325 | interrupts = <18>; | |
| 564695dd | 326 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 327 | fsl,usbmisc = <&usbmisc 0>; |
| a79025c4 | 328 | fsl,usbphy = <&usbphy0>; |
| 212d0b83 MG |
329 | status = "disabled"; |
| 330 | }; | |
| 331 | ||
| 7b7d6727 | 332 | usbh1: usb@53f80200 { |
| 212d0b83 MG |
333 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 334 | reg = <0x53f80200 0x0200>; | |
| 335 | interrupts = <14>; | |
| 564695dd | 336 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 337 | fsl,usbmisc = <&usbmisc 1>; |
| a79025c4 | 338 | fsl,usbphy = <&usbphy1>; |
| 3ec481ed | 339 | dr_mode = "host"; |
| 212d0b83 MG |
340 | status = "disabled"; |
| 341 | }; | |
| 342 | ||
| 7b7d6727 | 343 | usbh2: usb@53f80400 { |
| 212d0b83 MG |
344 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 345 | reg = <0x53f80400 0x0200>; | |
| 346 | interrupts = <16>; | |
| 564695dd | 347 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 348 | fsl,usbmisc = <&usbmisc 2>; |
| 3ec481ed | 349 | dr_mode = "host"; |
| 212d0b83 MG |
350 | status = "disabled"; |
| 351 | }; | |
| 352 | ||
| 7b7d6727 | 353 | usbh3: usb@53f80600 { |
| 212d0b83 MG |
354 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 355 | reg = <0x53f80600 0x0200>; | |
| 356 | interrupts = <17>; | |
| 564695dd | 357 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 358 | fsl,usbmisc = <&usbmisc 3>; |
| 3ec481ed | 359 | dr_mode = "host"; |
| 212d0b83 MG |
360 | status = "disabled"; |
| 361 | }; | |
| 362 | ||
| a5735021 MG |
363 | usbmisc: usbmisc@53f80800 { |
| 364 | #index-cells = <1>; | |
| 365 | compatible = "fsl,imx53-usbmisc"; | |
| 366 | reg = <0x53f80800 0x200>; | |
| 564695dd | 367 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 MG |
368 | }; |
| 369 | ||
| 4d191868 | 370 | gpio1: gpio@53f84000 { |
| aeb27748 | 371 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
372 | reg = <0x53f84000 0x4000>; |
| 373 | interrupts = <50 51>; | |
| 374 | gpio-controller; | |
| 375 | #gpio-cells = <2>; | |
| 376 | interrupt-controller; | |
| 88cde8b7 | 377 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
378 | }; |
| 379 | ||
| 4d191868 | 380 | gpio2: gpio@53f88000 { |
| aeb27748 | 381 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
382 | reg = <0x53f88000 0x4000>; |
| 383 | interrupts = <52 53>; | |
| 384 | gpio-controller; | |
| 385 | #gpio-cells = <2>; | |
| 386 | interrupt-controller; | |
| 88cde8b7 | 387 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
388 | }; |
| 389 | ||
| 4d191868 | 390 | gpio3: gpio@53f8c000 { |
| aeb27748 | 391 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
392 | reg = <0x53f8c000 0x4000>; |
| 393 | interrupts = <54 55>; | |
| 394 | gpio-controller; | |
| 395 | #gpio-cells = <2>; | |
| 396 | interrupt-controller; | |
| 88cde8b7 | 397 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
398 | }; |
| 399 | ||
| 4d191868 | 400 | gpio4: gpio@53f90000 { |
| aeb27748 | 401 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
402 | reg = <0x53f90000 0x4000>; |
| 403 | interrupts = <56 57>; | |
| 404 | gpio-controller; | |
| 405 | #gpio-cells = <2>; | |
| 406 | interrupt-controller; | |
| 88cde8b7 | 407 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
408 | }; |
| 409 | ||
| 675e4d03 RL |
410 | kpp: kpp@53f94000 { |
| 411 | compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; | |
| 412 | reg = <0x53f94000 0x4000>; | |
| 413 | interrupts = <60>; | |
| 564695dd | 414 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 675e4d03 RL |
415 | status = "disabled"; |
| 416 | }; | |
| 417 | ||
| 7b7d6727 | 418 | wdog1: wdog@53f98000 { |
| 73d2b4cd SG |
419 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 420 | reg = <0x53f98000 0x4000>; | |
| 421 | interrupts = <58>; | |
| 564695dd | 422 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 73d2b4cd SG |
423 | }; |
| 424 | ||
| 7b7d6727 | 425 | wdog2: wdog@53f9c000 { |
| 73d2b4cd SG |
426 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 427 | reg = <0x53f9c000 0x4000>; | |
| 428 | interrupts = <59>; | |
| 564695dd | 429 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 73d2b4cd SG |
430 | status = "disabled"; |
| 431 | }; | |
| 432 | ||
| cc8aae9b SH |
433 | gpt: timer@53fa0000 { |
| 434 | compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; | |
| 435 | reg = <0x53fa0000 0x4000>; | |
| 436 | interrupts = <39>; | |
| 564695dd | 437 | clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, |
| 46311707 | 438 | <&clks IMX5_CLK_GPT_HF_GATE>; |
| cc8aae9b SH |
439 | clock-names = "ipg", "per"; |
| 440 | }; | |
| 441 | ||
| 3473a3a1 PB |
442 | srtc: rtc@53fa4000 { |
| 443 | compatible = "fsl,imx53-rtc"; | |
| 444 | reg = <0x53fa4000 0x4000>; | |
| 445 | interrupts = <24>; | |
| 446 | clocks = <&clks IMX5_CLK_SRTC_GATE>; | |
| 447 | }; | |
| 448 | ||
| 7b7d6727 | 449 | iomuxc: iomuxc@53fa8000 { |
| 5be03a7b SG |
450 | compatible = "fsl,imx53-iomuxc"; |
| 451 | reg = <0x53fa8000 0x4000>; | |
| 5be03a7b SG |
452 | }; |
| 453 | ||
| 5af9f143 PZ |
454 | gpr: iomuxc-gpr@53fa8000 { |
| 455 | compatible = "fsl,imx53-iomuxc-gpr", "syscon"; | |
| 456 | reg = <0x53fa8000 0xc>; | |
| 457 | }; | |
| 458 | ||
| 420714aa PZ |
459 | ldb: ldb@53fa8008 { |
| 460 | #address-cells = <1>; | |
| 461 | #size-cells = <0>; | |
| 462 | compatible = "fsl,imx53-ldb"; | |
| 463 | reg = <0x53fa8008 0x4>; | |
| 464 | gpr = <&gpr>; | |
| 564695dd | 465 | clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, |
| 46311707 JT |
466 | <&clks IMX5_CLK_LDB_DI1_SEL>, |
| 467 | <&clks IMX5_CLK_IPU_DI0_SEL>, | |
| 468 | <&clks IMX5_CLK_IPU_DI1_SEL>, | |
| 469 | <&clks IMX5_CLK_LDB_DI0_GATE>, | |
| 470 | <&clks IMX5_CLK_LDB_DI1_GATE>; | |
| 420714aa PZ |
471 | clock-names = "di0_pll", "di1_pll", |
| 472 | "di0_sel", "di1_sel", | |
| 473 | "di0", "di1"; | |
| 474 | status = "disabled"; | |
| 475 | ||
| 476 | lvds-channel@0 { | |
| 1b134c9c MN |
477 | #address-cells = <1>; |
| 478 | #size-cells = <0>; | |
| 420714aa | 479 | reg = <0>; |
| 420714aa | 480 | status = "disabled"; |
| e05c8c9a | 481 | |
| 1b134c9c MN |
482 | port@0 { |
| 483 | reg = <0>; | |
| 484 | ||
| e05c8c9a PZ |
485 | lvds0_in: endpoint { |
| 486 | remote-endpoint = <&ipu_di0_lvds0>; | |
| 487 | }; | |
| 488 | }; | |
| 77dd4bd0 RH |
489 | |
| 490 | port@2 { | |
| 491 | reg = <2>; | |
| 492 | }; | |
| 420714aa PZ |
493 | }; |
| 494 | ||
| 495 | lvds-channel@1 { | |
| 1b134c9c MN |
496 | #address-cells = <1>; |
| 497 | #size-cells = <0>; | |
| 420714aa | 498 | reg = <1>; |
| 420714aa | 499 | status = "disabled"; |
| e05c8c9a | 500 | |
| 1b134c9c MN |
501 | port@1 { |
| 502 | reg = <1>; | |
| 503 | ||
| e05c8c9a | 504 | lvds1_in: endpoint { |
| fa1746ae | 505 | remote-endpoint = <&ipu_di1_lvds1>; |
| e05c8c9a PZ |
506 | }; |
| 507 | }; | |
| 77dd4bd0 RH |
508 | |
| 509 | port@2 { | |
| 510 | reg = <2>; | |
| 511 | }; | |
| 420714aa PZ |
512 | }; |
| 513 | }; | |
| 514 | ||
| 9ae90afa SH |
515 | pwm1: pwm@53fb4000 { |
| 516 | #pwm-cells = <2>; | |
| 517 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
| 518 | reg = <0x53fb4000 0x4000>; | |
| 564695dd | 519 | clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, |
| 46311707 | 520 | <&clks IMX5_CLK_PWM1_HF_GATE>; |
| 9ae90afa SH |
521 | clock-names = "ipg", "per"; |
| 522 | interrupts = <61>; | |
| 523 | }; | |
| 524 | ||
| 525 | pwm2: pwm@53fb8000 { | |
| 526 | #pwm-cells = <2>; | |
| 527 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
| 528 | reg = <0x53fb8000 0x4000>; | |
| 564695dd | 529 | clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, |
| 46311707 | 530 | <&clks IMX5_CLK_PWM2_HF_GATE>; |
| 9ae90afa SH |
531 | clock-names = "ipg", "per"; |
| 532 | interrupts = <94>; | |
| 533 | }; | |
| 534 | ||
| 0c456cfa | 535 | uart1: serial@53fbc000 { |
| 73d2b4cd SG |
536 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 537 | reg = <0x53fbc000 0x4000>; | |
| 538 | interrupts = <31>; | |
| 564695dd | 539 | clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, |
| 46311707 | 540 | <&clks IMX5_CLK_UART1_PER_GATE>; |
| f40f38d1 | 541 | clock-names = "ipg", "per"; |
| d04eba90 FL |
542 | dmas = <&sdma 18 4 0>, <&sdma 19 4 0>; |
| 543 | dma-names = "rx", "tx"; | |
| 73d2b4cd SG |
544 | status = "disabled"; |
| 545 | }; | |
| 546 | ||
| 0c456cfa | 547 | uart2: serial@53fc0000 { |
| 73d2b4cd SG |
548 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 549 | reg = <0x53fc0000 0x4000>; | |
| 550 | interrupts = <32>; | |
| 564695dd | 551 | clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, |
| 46311707 | 552 | <&clks IMX5_CLK_UART2_PER_GATE>; |
| f40f38d1 | 553 | clock-names = "ipg", "per"; |
| d04eba90 FL |
554 | dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; |
| 555 | dma-names = "rx", "tx"; | |
| 73d2b4cd SG |
556 | status = "disabled"; |
| 557 | }; | |
| 558 | ||
| a9d1f924 | 559 | can1: can@53fc8000 { |
| 9a62dcf4 | 560 | compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; |
| a9d1f924 ST |
561 | reg = <0x53fc8000 0x4000>; |
| 562 | interrupts = <82>; | |
| 564695dd | 563 | clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, |
| 46311707 | 564 | <&clks IMX5_CLK_CAN1_SERIAL_GATE>; |
| f40f38d1 | 565 | clock-names = "ipg", "per"; |
| a9d1f924 ST |
566 | status = "disabled"; |
| 567 | }; | |
| 568 | ||
| 569 | can2: can@53fcc000 { | |
| 9a62dcf4 | 570 | compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; |
| a9d1f924 ST |
571 | reg = <0x53fcc000 0x4000>; |
| 572 | interrupts = <83>; | |
| 564695dd | 573 | clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, |
| 46311707 | 574 | <&clks IMX5_CLK_CAN2_SERIAL_GATE>; |
| f40f38d1 | 575 | clock-names = "ipg", "per"; |
| a9d1f924 ST |
576 | status = "disabled"; |
| 577 | }; | |
| 578 | ||
| 8d84c374 PZ |
579 | src: src@53fd0000 { |
| 580 | compatible = "fsl,imx53-src", "fsl,imx51-src"; | |
| 581 | reg = <0x53fd0000 0x4000>; | |
| 582 | #reset-cells = <1>; | |
| 583 | }; | |
| 584 | ||
| f40f38d1 FE |
585 | clks: ccm@53fd4000{ |
| 586 | compatible = "fsl,imx53-ccm"; | |
| 587 | reg = <0x53fd4000 0x4000>; | |
| 588 | interrupts = <0 71 0x04 0 72 0x04>; | |
| 589 | #clock-cells = <1>; | |
| 590 | }; | |
| 591 | ||
| 4d191868 | 592 | gpio5: gpio@53fdc000 { |
| aeb27748 | 593 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
594 | reg = <0x53fdc000 0x4000>; |
| 595 | interrupts = <103 104>; | |
| 596 | gpio-controller; | |
| 597 | #gpio-cells = <2>; | |
| 598 | interrupt-controller; | |
| 88cde8b7 | 599 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
600 | }; |
| 601 | ||
| 4d191868 | 602 | gpio6: gpio@53fe0000 { |
| aeb27748 | 603 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
604 | reg = <0x53fe0000 0x4000>; |
| 605 | interrupts = <105 106>; | |
| 606 | gpio-controller; | |
| 607 | #gpio-cells = <2>; | |
| 608 | interrupt-controller; | |
| 88cde8b7 | 609 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
610 | }; |
| 611 | ||
| 4d191868 | 612 | gpio7: gpio@53fe4000 { |
| aeb27748 | 613 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
614 | reg = <0x53fe4000 0x4000>; |
| 615 | interrupts = <107 108>; | |
| 616 | gpio-controller; | |
| 617 | #gpio-cells = <2>; | |
| 618 | interrupt-controller; | |
| 88cde8b7 | 619 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
620 | }; |
| 621 | ||
| 7b7d6727 | 622 | i2c3: i2c@53fec000 { |
| 73d2b4cd SG |
623 | #address-cells = <1>; |
| 624 | #size-cells = <0>; | |
| 5bdfba29 | 625 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
626 | reg = <0x53fec000 0x4000>; |
| 627 | interrupts = <64>; | |
| 564695dd | 628 | clocks = <&clks IMX5_CLK_I2C3_GATE>; |
| 73d2b4cd SG |
629 | status = "disabled"; |
| 630 | }; | |
| 631 | ||
| 0c456cfa | 632 | uart4: serial@53ff0000 { |
| 73d2b4cd SG |
633 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 634 | reg = <0x53ff0000 0x4000>; | |
| 635 | interrupts = <13>; | |
| 564695dd | 636 | clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, |
| 46311707 | 637 | <&clks IMX5_CLK_UART4_PER_GATE>; |
| f40f38d1 | 638 | clock-names = "ipg", "per"; |
| d04eba90 FL |
639 | dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; |
| 640 | dma-names = "rx", "tx"; | |
| 73d2b4cd SG |
641 | status = "disabled"; |
| 642 | }; | |
| 643 | }; | |
| 644 | ||
| 645 | aips@60000000 { /* AIPS2 */ | |
| 646 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 647 | #address-cells = <1>; | |
| 648 | #size-cells = <1>; | |
| 649 | reg = <0x60000000 0x10000000>; | |
| 650 | ranges; | |
| 651 | ||
| ac08281e ST |
652 | aipstz2: bridge@63f00000 { |
| 653 | compatible = "fsl,imx53-aipstz"; | |
| 654 | reg = <0x63f00000 0x60>; | |
| 655 | }; | |
| 656 | ||
| 4f3b2a41 SH |
657 | iim: iim@63f98000 { |
| 658 | compatible = "fsl,imx53-iim", "fsl,imx27-iim"; | |
| 659 | reg = <0x63f98000 0x4000>; | |
| 660 | interrupts = <69>; | |
| 564695dd | 661 | clocks = <&clks IMX5_CLK_IIM_GATE>; |
| 4f3b2a41 SH |
662 | }; |
| 663 | ||
| 0c456cfa | 664 | uart5: serial@63f90000 { |
| 73d2b4cd SG |
665 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 666 | reg = <0x63f90000 0x4000>; | |
| 667 | interrupts = <86>; | |
| 564695dd | 668 | clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, |
| 46311707 | 669 | <&clks IMX5_CLK_UART5_PER_GATE>; |
| f40f38d1 | 670 | clock-names = "ipg", "per"; |
| d04eba90 FL |
671 | dmas = <&sdma 16 4 0>, <&sdma 17 4 0>; |
| 672 | dma-names = "rx", "tx"; | |
| 73d2b4cd SG |
673 | status = "disabled"; |
| 674 | }; | |
| 675 | ||
| e548eac2 FE |
676 | tigerp: tigerp@63fa0000 { |
| 677 | compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp"; | |
| 678 | reg = <0x63fa0000 0x28>; | |
| 679 | }; | |
| 680 | ||
| a82b7b9c MF |
681 | owire: owire@63fa4000 { |
| 682 | compatible = "fsl,imx53-owire", "fsl,imx21-owire"; | |
| 683 | reg = <0x63fa4000 0x4000>; | |
| 564695dd | 684 | clocks = <&clks IMX5_CLK_OWIRE_GATE>; |
| a82b7b9c MF |
685 | status = "disabled"; |
| 686 | }; | |
| 687 | ||
| 5a2ecf0d | 688 | ecspi2: spi@63fac000 { |
| 73d2b4cd SG |
689 | #address-cells = <1>; |
| 690 | #size-cells = <0>; | |
| 691 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
| 692 | reg = <0x63fac000 0x4000>; | |
| 693 | interrupts = <37>; | |
| 564695dd | 694 | clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, |
| 46311707 | 695 | <&clks IMX5_CLK_ECSPI2_PER_GATE>; |
| f40f38d1 | 696 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
697 | status = "disabled"; |
| 698 | }; | |
| 699 | ||
| 7b7d6727 | 700 | sdma: sdma@63fb0000 { |
| 73d2b4cd SG |
701 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; |
| 702 | reg = <0x63fb0000 0x4000>; | |
| 703 | interrupts = <6>; | |
| 564695dd | 704 | clocks = <&clks IMX5_CLK_SDMA_GATE>, |
| 28c16801 | 705 | <&clks IMX5_CLK_AHB>; |
| f40f38d1 | 706 | clock-names = "ipg", "ahb"; |
| fb72bb21 | 707 | #dma-cells = <3>; |
| 7e4f0365 | 708 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; |
| 73d2b4cd SG |
709 | }; |
| 710 | ||
| 5a2ecf0d | 711 | cspi: spi@63fc0000 { |
| 73d2b4cd SG |
712 | #address-cells = <1>; |
| 713 | #size-cells = <0>; | |
| 714 | compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; | |
| 715 | reg = <0x63fc0000 0x4000>; | |
| 716 | interrupts = <38>; | |
| 564695dd | 717 | clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, |
| 46311707 | 718 | <&clks IMX5_CLK_CSPI_IPG_GATE>; |
| f40f38d1 | 719 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
720 | status = "disabled"; |
| 721 | }; | |
| 722 | ||
| 7b7d6727 | 723 | i2c2: i2c@63fc4000 { |
| 73d2b4cd SG |
724 | #address-cells = <1>; |
| 725 | #size-cells = <0>; | |
| 5bdfba29 | 726 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
727 | reg = <0x63fc4000 0x4000>; |
| 728 | interrupts = <63>; | |
| 564695dd | 729 | clocks = <&clks IMX5_CLK_I2C2_GATE>; |
| 73d2b4cd SG |
730 | status = "disabled"; |
| 731 | }; | |
| 732 | ||
| 7b7d6727 | 733 | i2c1: i2c@63fc8000 { |
| 73d2b4cd SG |
734 | #address-cells = <1>; |
| 735 | #size-cells = <0>; | |
| 5bdfba29 | 736 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
737 | reg = <0x63fc8000 0x4000>; |
| 738 | interrupts = <62>; | |
| 564695dd | 739 | clocks = <&clks IMX5_CLK_I2C1_GATE>; |
| 73d2b4cd SG |
740 | status = "disabled"; |
| 741 | }; | |
| 742 | ||
| ffc505c0 | 743 | ssi1: ssi@63fcc000 { |
| 6ff7f51e | 744 | #sound-dai-cells = <0>; |
| 28f93d0b MP |
745 | compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", |
| 746 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
747 | reg = <0x63fcc000 0x4000>; |
| 748 | interrupts = <29>; | |
| 685570ab FE |
749 | clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, |
| 750 | <&clks IMX5_CLK_SSI1_ROOT_GATE>; | |
| 751 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
752 | dmas = <&sdma 28 0 0>, |
| 753 | <&sdma 29 0 0>; | |
| 754 | dma-names = "rx", "tx"; | |
| ffc505c0 | 755 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
756 | status = "disabled"; |
| 757 | }; | |
| 758 | ||
| 7b7d6727 | 759 | audmux: audmux@63fd0000 { |
| ffc505c0 SG |
760 | compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; |
| 761 | reg = <0x63fd0000 0x4000>; | |
| 762 | status = "disabled"; | |
| 763 | }; | |
| 764 | ||
| 7b7d6727 | 765 | nfc: nand@63fdb000 { |
| 75453a08 SH |
766 | compatible = "fsl,imx53-nand"; |
| 767 | reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; | |
| 768 | interrupts = <8>; | |
| 564695dd | 769 | clocks = <&clks IMX5_CLK_NFC_GATE>; |
| 75453a08 SH |
770 | status = "disabled"; |
| 771 | }; | |
| 772 | ||
| ffc505c0 | 773 | ssi3: ssi@63fe8000 { |
| 6ff7f51e | 774 | #sound-dai-cells = <0>; |
| 28f93d0b MP |
775 | compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", |
| 776 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
777 | reg = <0x63fe8000 0x4000>; |
| 778 | interrupts = <96>; | |
| 685570ab FE |
779 | clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, |
| 780 | <&clks IMX5_CLK_SSI3_ROOT_GATE>; | |
| 781 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
782 | dmas = <&sdma 46 0 0>, |
| 783 | <&sdma 47 0 0>; | |
| 784 | dma-names = "rx", "tx"; | |
| ffc505c0 | 785 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
786 | status = "disabled"; |
| 787 | }; | |
| 788 | ||
| 7b7d6727 | 789 | fec: ethernet@63fec000 { |
| 73d2b4cd SG |
790 | compatible = "fsl,imx53-fec", "fsl,imx25-fec"; |
| 791 | reg = <0x63fec000 0x4000>; | |
| 792 | interrupts = <87>; | |
| 564695dd | 793 | clocks = <&clks IMX5_CLK_FEC_GATE>, |
| 46311707 JT |
794 | <&clks IMX5_CLK_FEC_GATE>, |
| 795 | <&clks IMX5_CLK_FEC_GATE>; | |
| f40f38d1 | 796 | clock-names = "ipg", "ahb", "ptp"; |
| 73d2b4cd SG |
797 | status = "disabled"; |
| 798 | }; | |
| 19194c2b PZ |
799 | |
| 800 | tve: tve@63ff0000 { | |
| 801 | compatible = "fsl,imx53-tve"; | |
| 802 | reg = <0x63ff0000 0x1000>; | |
| 803 | interrupts = <92>; | |
| 564695dd | 804 | clocks = <&clks IMX5_CLK_TVE_GATE>, |
| 46311707 | 805 | <&clks IMX5_CLK_IPU_DI1_SEL>; |
| 19194c2b | 806 | clock-names = "tve", "di_sel"; |
| 19194c2b | 807 | status = "disabled"; |
| e05c8c9a PZ |
808 | |
| 809 | port { | |
| 810 | tve_in: endpoint { | |
| 811 | remote-endpoint = <&ipu_di1_tve>; | |
| 812 | }; | |
| 813 | }; | |
| 19194c2b | 814 | }; |
| fbf970f6 FE |
815 | |
| 816 | vpu: vpu@63ff4000 { | |
| 71946619 | 817 | compatible = "fsl,imx53-vpu", "cnm,coda7541"; |
| fbf970f6 FE |
818 | reg = <0x63ff4000 0x1000>; |
| 819 | interrupts = <9>; | |
| fa97d2f7 | 820 | clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, |
| 46311707 | 821 | <&clks IMX5_CLK_VPU_GATE>; |
| fbf970f6 | 822 | clock-names = "per", "ahb"; |
| b1e2e546 | 823 | resets = <&src 1>; |
| fbf970f6 | 824 | iram = <&ocram>; |
| fbf970f6 | 825 | }; |
| 60811cc2 ST |
826 | |
| 827 | sahara: crypto@63ff8000 { | |
| 828 | compatible = "fsl,imx53-sahara"; | |
| 829 | reg = <0x63ff8000 0x4000>; | |
| 830 | interrupts = <19 20>; | |
| 831 | clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, | |
| 46311707 | 832 | <&clks IMX5_CLK_SAHARA_IPG_GATE>; |
| 60811cc2 ST |
833 | clock-names = "ipg", "ahb"; |
| 834 | }; | |
| 73d2b4cd | 835 | }; |
| 481fbe13 PZ |
836 | |
| 837 | ocram: sram@f8000000 { | |
| 838 | compatible = "mmio-sram"; | |
| 839 | reg = <0xf8000000 0x20000>; | |
| 564695dd | 840 | clocks = <&clks IMX5_CLK_OCRAM>; |
| 481fbe13 | 841 | }; |
| 73d2b4cd SG |
842 | }; |
| 843 | }; |