[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / imx53.dtsi

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "skeleton.dtsi"
#include "imx53-pinfunc.h"

/ {
	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		gpio6 = &gpio7;
	};

	tzic: tz-interrupt-controller@0fffc000 {
		compatible = "fsl,imx53-tzic", "fsl,tzic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x0fffc000 0x4000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		ckil {
			compatible = "fsl,imx-ckil", "fixed-clock";
			clock-frequency = <32768>;
		};

		ckih1 {
			compatible = "fsl,imx-ckih1", "fixed-clock";
			clock-frequency = <22579200>;
		};

		ckih2 {
			compatible = "fsl,imx-ckih2", "fixed-clock";
			clock-frequency = <0>;
		};

		osc {
			compatible = "fsl,imx-osc", "fixed-clock";
			clock-frequency = <24000000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&tzic>;
		ranges;

		ipu: ipu@18000000 {
			#crtc-cells = <1>;
			compatible = "fsl,imx53-ipu";
			reg = <0x18000000 0x080000000>;
			interrupts = <11 10>;
		};

		aips@50000000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x50000000 0x10000000>;
			ranges;

			spba@50000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x50000000 0x40000>;
				ranges;

				esdhc1: esdhc@50004000 {
					compatible = "fsl,imx53-esdhc";
					reg = <0x50004000 0x4000>;
					interrupts = <1>;
					clocks = <&clks 44>, <&clks 0>, <&clks 71>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				esdhc2: esdhc@50008000 {
					compatible = "fsl,imx53-esdhc";
					reg = <0x50008000 0x4000>;
					interrupts = <2>;
					clocks = <&clks 45>, <&clks 0>, <&clks 72>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				uart3: serial@5000c000 {
					compatible = "fsl,imx53-uart", "fsl,imx21-uart";
					reg = <0x5000c000 0x4000>;
					interrupts = <33>;
					clocks = <&clks 32>, <&clks 33>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi1: ecspi@50010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
					reg = <0x50010000 0x4000>;
					interrupts = <36>;
					clocks = <&clks 51>, <&clks 52>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ssi2: ssi@50014000 {
					compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
					reg = <0x50014000 0x4000>;
					interrupts = <30>;
					clocks = <&clks 49>;
					fsl,fifo-depth = <15>;
					fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
					status = "disabled";
				};

				esdhc3: esdhc@50020000 {
					compatible = "fsl,imx53-esdhc";
					reg = <0x50020000 0x4000>;
					interrupts = <3>;
					clocks = <&clks 46>, <&clks 0>, <&clks 73>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				esdhc4: esdhc@50024000 {
					compatible = "fsl,imx53-esdhc";
					reg = <0x50024000 0x4000>;
					interrupts = <4>;
					clocks = <&clks 47>, <&clks 0>, <&clks 74>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};
			};

			usbotg: usb@53f80000 {
				compatible = "fsl,imx53-usb", "fsl,imx27-usb";
				reg = <0x53f80000 0x0200>;
				interrupts = <18>;
				status = "disabled";
			};

			usbh1: usb@53f80200 {
				compatible = "fsl,imx53-usb", "fsl,imx27-usb";
				reg = <0x53f80200 0x0200>;
				interrupts = <14>;
				status = "disabled";
			};

			usbh2: usb@53f80400 {
				compatible = "fsl,imx53-usb", "fsl,imx27-usb";
				reg = <0x53f80400 0x0200>;
				interrupts = <16>;
				status = "disabled";
			};

			usbh3: usb@53f80600 {
				compatible = "fsl,imx53-usb", "fsl,imx27-usb";
				reg = <0x53f80600 0x0200>;
				interrupts = <17>;
				status = "disabled";
			};

			gpio1: gpio@53f84000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53f84000 0x4000>;
				interrupts = <50 51>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@53f88000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53f88000 0x4000>;
				interrupts = <52 53>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@53f8c000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53f8c000 0x4000>;
				interrupts = <54 55>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@53f90000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53f90000 0x4000>;
				interrupts = <56 57>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			wdog1: wdog@53f98000 {
				compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
				reg = <0x53f98000 0x4000>;
				interrupts = <58>;
				clocks = <&clks 0>;
			};

			wdog2: wdog@53f9c000 {
				compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
				reg = <0x53f9c000 0x4000>;
				interrupts = <59>;
				clocks = <&clks 0>;
				status = "disabled";
			};

			iomuxc: iomuxc@53fa8000 {
				compatible = "fsl,imx53-iomuxc";
				reg = <0x53fa8000 0x4000>;

				audmux {
					pinctrl_audmux_1: audmuxgrp-1 {
						fsl,pins = <
							MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC  0x80000000
							MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD  0x80000000
							MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
							MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x80000000
						>;
					};
				};

				fec {
					pinctrl_fec_1: fecgrp-1 {
						fsl,pins = <
							MX53_PAD_FEC_MDC__FEC_MDC	 0x80000000
							MX53_PAD_FEC_MDIO__FEC_MDIO	 0x80000000
							MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
							MX53_PAD_FEC_RX_ER__FEC_RX_ER    0x80000000
							MX53_PAD_FEC_CRS_DV__FEC_RX_DV   0x80000000
							MX53_PAD_FEC_RXD1__FEC_RDATA_1   0x80000000
							MX53_PAD_FEC_RXD0__FEC_RDATA_0   0x80000000
							MX53_PAD_FEC_TX_EN__FEC_TX_EN    0x80000000
							MX53_PAD_FEC_TXD1__FEC_TDATA_1   0x80000000
							MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
						>;
					};
				};

				csi {
					pinctrl_csi_1: csigrp-1 {
						fsl,pins = <
							MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
							MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC     0x1d5
							MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC      0x1d5
							MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
							MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19      0x1d5
							MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18      0x1d5
							MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17      0x1d5
							MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16      0x1d5
							MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15      0x1d5
							MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14      0x1d5
							MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13      0x1d5
							MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12      0x1d5
							MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11      0x1d5
							MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10      0x1d5
							MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9	0x1d5
							MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8	0x1d5
							MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7	0x1d5
							MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6	0x1d5
							MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5	0x1d5
							MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4	0x1d5
							MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
						>;
					};
				};

				cspi {
					pinctrl_cspi_1: cspigrp-1 {
						fsl,pins = <
							MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
							MX53_PAD_SD1_CMD__CSPI_MOSI   0x1d5
							MX53_PAD_SD1_CLK__CSPI_SCLK   0x1d5
						>;
					};
				};

				ecspi1 {
					pinctrl_ecspi1_1: ecspi1grp-1 {
						fsl,pins = <
							MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
							MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
							MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
						>;
					};
				};

				esdhc1 {
					pinctrl_esdhc1_1: esdhc1grp-1 {
						fsl,pins = <
							MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
							MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
							MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
							MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
							MX53_PAD_SD1_CMD__ESDHC1_CMD	0x1d5
							MX53_PAD_SD1_CLK__ESDHC1_CLK	0x1d5
						>;
					};

					pinctrl_esdhc1_2: esdhc1grp-2 {
						fsl,pins = <
							MX53_PAD_SD1_DATA0__ESDHC1_DAT0   0x1d5
							MX53_PAD_SD1_DATA1__ESDHC1_DAT1   0x1d5
							MX53_PAD_SD1_DATA2__ESDHC1_DAT2   0x1d5
							MX53_PAD_SD1_DATA3__ESDHC1_DAT3   0x1d5
							MX53_PAD_PATA_DATA8__ESDHC1_DAT4  0x1d5
							MX53_PAD_PATA_DATA9__ESDHC1_DAT5  0x1d5
							MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
							MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
							MX53_PAD_SD1_CMD__ESDHC1_CMD	  0x1d5
							MX53_PAD_SD1_CLK__ESDHC1_CLK	  0x1d5
						>;
					};
				};

				esdhc2 {
					pinctrl_esdhc2_1: esdhc2grp-1 {
						fsl,pins = <
							MX53_PAD_SD2_CMD__ESDHC2_CMD	0x1d5
							MX53_PAD_SD2_CLK__ESDHC2_CLK	0x1d5
							MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
							MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
							MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
							MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
						>;
					};
				};

				esdhc3 {
					pinctrl_esdhc3_1: esdhc3grp-1 {
						fsl,pins = <
							MX53_PAD_PATA_DATA8__ESDHC3_DAT0  0x1d5
							MX53_PAD_PATA_DATA9__ESDHC3_DAT1  0x1d5
							MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
							MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
							MX53_PAD_PATA_DATA0__ESDHC3_DAT4  0x1d5
							MX53_PAD_PATA_DATA1__ESDHC3_DAT5  0x1d5
							MX53_PAD_PATA_DATA2__ESDHC3_DAT6  0x1d5
							MX53_PAD_PATA_DATA3__ESDHC3_DAT7  0x1d5
							MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
							MX53_PAD_PATA_IORDY__ESDHC3_CLK   0x1d5
						>;
					};
				};

				can1 {
					pinctrl_can1_1: can1grp-1 {
						fsl,pins = <
							MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
							MX53_PAD_PATA_DIOR__CAN1_RXCAN  0x80000000
						>;
					};

					pinctrl_can1_2: can1grp-2 {
						fsl,pins = <
							MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
							MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
						>;
					};
				};

				can2 {
					pinctrl_can2_1: can2grp-1 {
						fsl,pins = <
							MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
							MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
						>;
					};
				};

				i2c1 {
					pinctrl_i2c1_1: i2c1grp-1 {
						fsl,pins = <
							MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
							MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
						>;
					};
				};

				i2c2 {
					pinctrl_i2c2_1: i2c2grp-1 {
						fsl,pins = <
							MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
							MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
						>;
					};
				};

				i2c3 {
					pinctrl_i2c3_1: i2c3grp-1 {
						fsl,pins = <
							MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
							MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
						>;
					};
				};

				owire {
					pinctrl_owire_1: owiregrp-1 {
						fsl,pins = <
							MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
						>;
					};
				};

				uart1 {
					pinctrl_uart1_1: uart1grp-1 {
						fsl,pins = <
							MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
							MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
						>;
					};

					pinctrl_uart1_2: uart1grp-2 {
						fsl,pins = <
							MX53_PAD_PATA_DIOW__UART1_TXD_MUX  0x1c5
							MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
						>;
					};
				};

				uart2 {
					pinctrl_uart2_1: uart2grp-1 {
						fsl,pins = <
							MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
							MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     0x1c5
						>;
					};
				};

				uart3 {
					pinctrl_uart3_1: uart3grp-1 {
						fsl,pins = <
							MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
							MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
							MX53_PAD_PATA_DA_1__UART3_CTS	  0x1c5
							MX53_PAD_PATA_DA_2__UART3_RTS	  0x1c5
						>;
					};

					pinctrl_uart3_2: uart3grp-2 {
						fsl,pins = <
							MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
							MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
						>;
					};

				};

				uart4 {
					pinctrl_uart4_1: uart4grp-1 {
						fsl,pins = <
							MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
							MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
						>;
					};
				};

				uart5 {
					pinctrl_uart5_1: uart5grp-1 {
						fsl,pins = <
							MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
							MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
						>;
					};
				};

			};

			pwm1: pwm@53fb4000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
				reg = <0x53fb4000 0x4000>;
				clocks = <&clks 37>, <&clks 38>;
				clock-names = "ipg", "per";
				interrupts = <61>;
			};

			pwm2: pwm@53fb8000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
				reg = <0x53fb8000 0x4000>;
				clocks = <&clks 39>, <&clks 40>;
				clock-names = "ipg", "per";
				interrupts = <94>;
			};

			uart1: serial@53fbc000 {
				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
				reg = <0x53fbc000 0x4000>;
				interrupts = <31>;
				clocks = <&clks 28>, <&clks 29>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@53fc0000 {
				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
				reg = <0x53fc0000 0x4000>;
				interrupts = <32>;
				clocks = <&clks 30>, <&clks 31>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			can1: can@53fc8000 {
				compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
				reg = <0x53fc8000 0x4000>;
				interrupts = <82>;
				clocks = <&clks 158>, <&clks 157>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			can2: can@53fcc000 {
				compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
				reg = <0x53fcc000 0x4000>;
				interrupts = <83>;
				clocks = <&clks 87>, <&clks 86>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			clks: ccm@53fd4000{
				compatible = "fsl,imx53-ccm";
				reg = <0x53fd4000 0x4000>;
				interrupts = <0 71 0x04 0 72 0x04>;
				#clock-cells = <1>;
			};

			gpio5: gpio@53fdc000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53fdc000 0x4000>;
				interrupts = <103 104>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio6: gpio@53fe0000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53fe0000 0x4000>;
				interrupts = <105 106>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio7: gpio@53fe4000 {
				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
				reg = <0x53fe4000 0x4000>;
				interrupts = <107 108>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			i2c3: i2c@53fec000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
				reg = <0x53fec000 0x4000>;
				interrupts = <64>;
				clocks = <&clks 88>;
				status = "disabled";
			};

			uart4: serial@53ff0000 {
				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
				reg = <0x53ff0000 0x4000>;
				interrupts = <13>;
				clocks = <&clks 65>, <&clks 66>;
				clock-names = "ipg", "per";
				status = "disabled";
			};
		};

		aips@60000000 {	/* AIPS2 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x60000000 0x10000000>;
			ranges;

			uart5: serial@63f90000 {
				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
				reg = <0x63f90000 0x4000>;
				interrupts = <86>;
				clocks = <&clks 67>, <&clks 68>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			owire: owire@63fa4000 {
				compatible = "fsl,imx53-owire", "fsl,imx21-owire";
				reg = <0x63fa4000 0x4000>;
				clocks = <&clks 159>;
				status = "disabled";
			};

			ecspi2: ecspi@63fac000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
				reg = <0x63fac000 0x4000>;
				interrupts = <37>;
				clocks = <&clks 53>, <&clks 54>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			sdma: sdma@63fb0000 {
				compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
				reg = <0x63fb0000 0x4000>;
				interrupts = <6>;
				clocks = <&clks 56>, <&clks 56>;
				clock-names = "ipg", "ahb";
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
			};

			cspi: cspi@63fc0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
				reg = <0x63fc0000 0x4000>;
				interrupts = <38>;
				clocks = <&clks 55>, <&clks 0>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c2: i2c@63fc4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
				reg = <0x63fc4000 0x4000>;
				interrupts = <63>;
				clocks = <&clks 35>;
				status = "disabled";
			};

			i2c1: i2c@63fc8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
				reg = <0x63fc8000 0x4000>;
				interrupts = <62>;
				clocks = <&clks 34>;
				status = "disabled";
			};

			ssi1: ssi@63fcc000 {
				compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
				reg = <0x63fcc000 0x4000>;
				interrupts = <29>;
				clocks = <&clks 48>;
				fsl,fifo-depth = <15>;
				fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
				status = "disabled";
			};

			audmux: audmux@63fd0000 {
				compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
				reg = <0x63fd0000 0x4000>;
				status = "disabled";
			};

			nfc: nand@63fdb000 {
				compatible = "fsl,imx53-nand";
				reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
				interrupts = <8>;
				clocks = <&clks 60>;
				status = "disabled";
			};

			ssi3: ssi@63fe8000 {
				compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
				reg = <0x63fe8000 0x4000>;
				interrupts = <96>;
				clocks = <&clks 50>;
				fsl,fifo-depth = <15>;
				fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
				status = "disabled";
			};

			fec: ethernet@63fec000 {
				compatible = "fsl,imx53-fec", "fsl,imx25-fec";
				reg = <0x63fec000 0x4000>;
				interrupts = <87>;
				clocks = <&clks 42>, <&clks 42>, <&clks 42>;
				clock-names = "ipg", "ahb", "ptp";
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
73d2b4cd SG	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc.
	3	* Copyright 2011 Linaro Ltd.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
36dffd8f	13	#include "skeleton.dtsi"
e1641531	14	#include "imx53-pinfunc.h"
73d2b4cd SG	15
	16	/ {
	17	aliases {
8f9ffecf RZ	18	serial0 = &uart1;
	19	serial1 = &uart2;
	20	serial2 = &uart3;
	21	serial3 = &uart4;
	22	serial4 = &uart5;
5230f8fe SG	23	gpio0 = &gpio1;
	24	gpio1 = &gpio2;
	25	gpio2 = &gpio3;
	26	gpio3 = &gpio4;
	27	gpio4 = &gpio5;
	28	gpio5 = &gpio6;
	29	gpio6 = &gpio7;
73d2b4cd SG	30	};
	31
	32	tzic: tz-interrupt-controller@0fffc000 {
	33	compatible = "fsl,imx53-tzic", "fsl,tzic";
	34	interrupt-controller;
	35	#interrupt-cells = <1>;
	36	reg = <0x0fffc000 0x4000>;
	37	};
	38
	39	clocks {
	40	#address-cells = <1>;
	41	#size-cells = <0>;
	42
	43	ckil {
	44	compatible = "fsl,imx-ckil", "fixed-clock";
	45	clock-frequency = <32768>;
	46	};
	47
	48	ckih1 {
	49	compatible = "fsl,imx-ckih1", "fixed-clock";
	50	clock-frequency = <22579200>;
	51	};
	52
	53	ckih2 {
	54	compatible = "fsl,imx-ckih2", "fixed-clock";
	55	clock-frequency = <0>;
	56	};
	57
	58	osc {
	59	compatible = "fsl,imx-osc", "fixed-clock";
	60	clock-frequency = <24000000>;
	61	};
	62	};
	63
	64	soc {
	65	#address-cells = <1>;
	66	#size-cells = <1>;
	67	compatible = "simple-bus";
	68	interrupt-parent = <&tzic>;
	69	ranges;
	70
abed9a6b SH	71	ipu: ipu@18000000 {
	72	#crtc-cells = <1>;
	73	compatible = "fsl,imx53-ipu";
	74	reg = <0x18000000 0x080000000>;
	75	interrupts = <11 10>;
	76	};
	77
73d2b4cd SG	78	aips@50000000 { /* AIPS1 */
	79	compatible = "fsl,aips-bus", "simple-bus";
	80	#address-cells = <1>;
	81	#size-cells = <1>;
	82	reg = <0x50000000 0x10000000>;
	83	ranges;
	84
	85	spba@50000000 {
	86	compatible = "fsl,spba-bus", "simple-bus";
	87	#address-cells = <1>;
	88	#size-cells = <1>;
	89	reg = <0x50000000 0x40000>;
	90	ranges;
	91
7b7d6727	92	esdhc1: esdhc@50004000 {
73d2b4cd SG	93	compatible = "fsl,imx53-esdhc";
	94	reg = <0x50004000 0x4000>;
	95	interrupts = <1>;
f40f38d1 FE	96	clocks = <&clks 44>, <&clks 0>, <&clks 71>;
f40f38d1 FE	97	clock-names = "ipg", "ahb", "per";
c104b6a2	98	bus-width = <4>;
73d2b4cd SG	99	status = "disabled";
	100	};
	101
7b7d6727	102	esdhc2: esdhc@50008000 {
73d2b4cd SG	103	compatible = "fsl,imx53-esdhc";
	104	reg = <0x50008000 0x4000>;
	105	interrupts = <2>;
f40f38d1 FE	106	clocks = <&clks 45>, <&clks 0>, <&clks 72>;
f40f38d1 FE	107	clock-names = "ipg", "ahb", "per";
c104b6a2	108	bus-width = <4>;
73d2b4cd SG	109	status = "disabled";
	110	};
	111
0c456cfa	112	uart3: serial@5000c000 {
73d2b4cd SG	113	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	114	reg = <0x5000c000 0x4000>;
	115	interrupts = <33>;
f40f38d1 FE	116	clocks = <&clks 32>, <&clks 33>;
f40f38d1 FE	117	clock-names = "ipg", "per";
73d2b4cd SG	118	status = "disabled";
	119	};
	120
7b7d6727	121	ecspi1: ecspi@50010000 {
73d2b4cd SG	122	#address-cells = <1>;
	123	#size-cells = <0>;
	124	compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
	125	reg = <0x50010000 0x4000>;
	126	interrupts = <36>;
f40f38d1 FE	127	clocks = <&clks 51>, <&clks 52>;
f40f38d1 FE	128	clock-names = "ipg", "per";
73d2b4cd SG	129	status = "disabled";
	130	};
	131
ffc505c0 SG	132	ssi2: ssi@50014000 {
	133	compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
	134	reg = <0x50014000 0x4000>;
	135	interrupts = <30>;
f40f38d1	136	clocks = <&clks 49>;
ffc505c0 SG	137	fsl,fifo-depth = <15>;
	138	fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
	139	status = "disabled";
	140	};
	141
7b7d6727	142	esdhc3: esdhc@50020000 {
73d2b4cd SG	143	compatible = "fsl,imx53-esdhc";
	144	reg = <0x50020000 0x4000>;
	145	interrupts = <3>;
f40f38d1 FE	146	clocks = <&clks 46>, <&clks 0>, <&clks 73>;
f40f38d1 FE	147	clock-names = "ipg", "ahb", "per";
c104b6a2	148	bus-width = <4>;
73d2b4cd SG	149	status = "disabled";
	150	};
	151
7b7d6727	152	esdhc4: esdhc@50024000 {
73d2b4cd SG	153	compatible = "fsl,imx53-esdhc";
	154	reg = <0x50024000 0x4000>;
	155	interrupts = <4>;
f40f38d1 FE	156	clocks = <&clks 47>, <&clks 0>, <&clks 74>;
f40f38d1 FE	157	clock-names = "ipg", "ahb", "per";
c104b6a2	158	bus-width = <4>;
73d2b4cd SG	159	status = "disabled";
	160	};
	161	};
	162
7b7d6727	163	usbotg: usb@53f80000 {
212d0b83 MG	164	compatible = "fsl,imx53-usb", "fsl,imx27-usb";
	165	reg = <0x53f80000 0x0200>;
	166	interrupts = <18>;
	167	status = "disabled";
	168	};
	169
7b7d6727	170	usbh1: usb@53f80200 {
212d0b83 MG	171	compatible = "fsl,imx53-usb", "fsl,imx27-usb";
	172	reg = <0x53f80200 0x0200>;
	173	interrupts = <14>;
	174	status = "disabled";
	175	};
	176
7b7d6727	177	usbh2: usb@53f80400 {
212d0b83 MG	178	compatible = "fsl,imx53-usb", "fsl,imx27-usb";
	179	reg = <0x53f80400 0x0200>;
	180	interrupts = <16>;
	181	status = "disabled";
	182	};
	183
7b7d6727	184	usbh3: usb@53f80600 {
212d0b83 MG	185	compatible = "fsl,imx53-usb", "fsl,imx27-usb";
	186	reg = <0x53f80600 0x0200>;
	187	interrupts = <17>;
	188	status = "disabled";
	189	};
	190
4d191868	191	gpio1: gpio@53f84000 {
aeb27748	192	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	193	reg = <0x53f84000 0x4000>;
	194	interrupts = <50 51>;
	195	gpio-controller;
	196	#gpio-cells = <2>;
	197	interrupt-controller;
88cde8b7	198	#interrupt-cells = <2>;
73d2b4cd SG	199	};
73d2b4cd SG	200
4d191868	201	gpio2: gpio@53f88000 {
aeb27748	202	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	203	reg = <0x53f88000 0x4000>;
	204	interrupts = <52 53>;
	205	gpio-controller;
	206	#gpio-cells = <2>;
	207	interrupt-controller;
88cde8b7	208	#interrupt-cells = <2>;
73d2b4cd SG	209	};
73d2b4cd SG	210
4d191868	211	gpio3: gpio@53f8c000 {
aeb27748	212	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	213	reg = <0x53f8c000 0x4000>;
	214	interrupts = <54 55>;
	215	gpio-controller;
	216	#gpio-cells = <2>;
	217	interrupt-controller;
88cde8b7	218	#interrupt-cells = <2>;
73d2b4cd SG	219	};
73d2b4cd SG	220
4d191868	221	gpio4: gpio@53f90000 {
aeb27748	222	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	223	reg = <0x53f90000 0x4000>;
	224	interrupts = <56 57>;
	225	gpio-controller;
	226	#gpio-cells = <2>;
	227	interrupt-controller;
88cde8b7	228	#interrupt-cells = <2>;
73d2b4cd SG	229	};
73d2b4cd SG	230
7b7d6727	231	wdog1: wdog@53f98000 {
73d2b4cd SG	232	compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
	233	reg = <0x53f98000 0x4000>;
	234	interrupts = <58>;
f40f38d1	235	clocks = <&clks 0>;
73d2b4cd SG	236	};
73d2b4cd SG	237
7b7d6727	238	wdog2: wdog@53f9c000 {
73d2b4cd SG	239	compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
	240	reg = <0x53f9c000 0x4000>;
	241	interrupts = <59>;
f40f38d1	242	clocks = <&clks 0>;
73d2b4cd SG	243	status = "disabled";
	244	};
	245
7b7d6727	246	iomuxc: iomuxc@53fa8000 {
5be03a7b SG	247	compatible = "fsl,imx53-iomuxc";
	248	reg = <0x53fa8000 0x4000>;
	249
	250	audmux {
	251	pinctrl_audmux_1: audmuxgrp-1 {
	252	fsl,pins = <
e1641531 SG	253	MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
	254	MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
	255	MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
	256	MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
5be03a7b SG	257	>;
	258	};
	259	};
	260
	261	fec {
	262	pinctrl_fec_1: fecgrp-1 {
	263	fsl,pins = <
e1641531 SG	264	MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
	265	MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
	266	MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
	267	MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
	268	MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
	269	MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
	270	MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
	271	MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
	272	MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
	273	MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
5be03a7b SG	274	>;
	275	};
	276	};
	277
11ab21e9 ST	278	csi {
	279	pinctrl_csi_1: csigrp-1 {
	280	fsl,pins = <
e1641531 SG	281	MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
	282	MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
	283	MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
	284	MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
	285	MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
	286	MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
	287	MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
	288	MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
	289	MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
	290	MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
	291	MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
	292	MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
	293	MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
	294	MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
	295	MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
	296	MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
	297	MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
	298	MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
	299	MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
	300	MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
	301	MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
11ab21e9 ST	302	>;
	303	};
	304	};
	305
	306	cspi {
	307	pinctrl_cspi_1: cspigrp-1 {
	308	fsl,pins = <
e1641531 SG	309	MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
	310	MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
	311	MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
11ab21e9 ST	312	>;
	313	};
	314	};
	315
327a79c0 SG	316	ecspi1 {
	317	pinctrl_ecspi1_1: ecspi1grp-1 {
	318	fsl,pins = <
e1641531 SG	319	MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
	320	MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
	321	MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
327a79c0 SG	322	>;
	323	};
	324	};
	325
5be03a7b SG	326	esdhc1 {
	327	pinctrl_esdhc1_1: esdhc1grp-1 {
	328	fsl,pins = <
e1641531 SG	329	MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
	330	MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
	331	MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
	332	MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
	333	MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
	334	MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
5be03a7b SG	335	>;
5be03a7b SG	336	};
4bb6143c SG	337
	338	pinctrl_esdhc1_2: esdhc1grp-2 {
	339	fsl,pins = <
e1641531 SG	340	MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
	341	MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
	342	MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
	343	MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
	344	MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
	345	MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
	346	MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
	347	MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
	348	MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
	349	MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
4bb6143c SG	350	>;
4bb6143c SG	351	};
5be03a7b SG	352	};
5be03a7b SG	353
07248042 SG	354	esdhc2 {
	355	pinctrl_esdhc2_1: esdhc2grp-1 {
	356	fsl,pins = <
e1641531 SG	357	MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
	358	MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
	359	MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
	360	MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
	361	MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
	362	MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
07248042 SG	363	>;
	364	};
	365	};
	366
5be03a7b SG	367	esdhc3 {
	368	pinctrl_esdhc3_1: esdhc3grp-1 {
	369	fsl,pins = <
e1641531 SG	370	MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
	371	MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
	372	MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
	373	MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
	374	MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
	375	MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
	376	MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
	377	MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
	378	MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
	379	MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
5be03a7b SG	380	>;
	381	};
	382	};
	383
a1fff236 RS	384	can1 {
	385	pinctrl_can1_1: can1grp-1 {
	386	fsl,pins = <
e1641531 SG	387	MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
e1641531 SG	388	MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
a1fff236 RS	389	>;
a1fff236 RS	390	};
11ab21e9 ST	391
	392	pinctrl_can1_2: can1grp-2 {
	393	fsl,pins = <
e1641531 SG	394	MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
e1641531 SG	395	MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
11ab21e9 ST	396	>;
11ab21e9 ST	397	};
a1fff236 RS	398	};
	399
	400	can2 {
	401	pinctrl_can2_1: can2grp-1 {
	402	fsl,pins = <
e1641531 SG	403	MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
e1641531 SG	404	MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
a1fff236 RS	405	>;
	406	};
	407	};
	408
5be03a7b SG	409	i2c1 {
	410	pinctrl_i2c1_1: i2c1grp-1 {
	411	fsl,pins = <
e1641531 SG	412	MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
e1641531 SG	413	MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
5be03a7b SG	414	>;
	415	};
	416	};
	417
	418	i2c2 {
	419	pinctrl_i2c2_1: i2c2grp-1 {
	420	fsl,pins = <
e1641531 SG	421	MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
e1641531 SG	422	MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
5be03a7b SG	423	>;
	424	};
	425	};
	426
a1fff236 RS	427	i2c3 {
	428	pinctrl_i2c3_1: i2c3grp-1 {
	429	fsl,pins = <
e1641531 SG	430	MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
e1641531 SG	431	MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
a1fff236 RS	432	>;
	433	};
	434	};
	435
a82b7b9c MF	436	owire {
	437	pinctrl_owire_1: owiregrp-1 {
	438	fsl,pins = <
e1641531	439	MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
a82b7b9c MF	440	>;
	441	};
	442	};
	443
5be03a7b SG	444	uart1 {
	445	pinctrl_uart1_1: uart1grp-1 {
	446	fsl,pins = <
e1641531 SG	447	MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
e1641531 SG	448	MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
5be03a7b SG	449	>;
5be03a7b SG	450	};
4bb6143c SG	451
	452	pinctrl_uart1_2: uart1grp-2 {
	453	fsl,pins = <
e1641531 SG	454	MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5
e1641531 SG	455	MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
4bb6143c SG	456	>;
4bb6143c SG	457	};
5be03a7b	458	};
07248042 SG	459
	460	uart2 {
	461	pinctrl_uart2_1: uart2grp-1 {
	462	fsl,pins = <
e1641531 SG	463	MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
e1641531 SG	464	MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
07248042 SG	465	>;
	466	};
	467	};
	468
	469	uart3 {
	470	pinctrl_uart3_1: uart3grp-1 {
	471	fsl,pins = <
e1641531 SG	472	MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
	473	MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
	474	MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5
	475	MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5
07248042 SG	476	>;
07248042 SG	477	};
11ab21e9 ST	478
	479	pinctrl_uart3_2: uart3grp-2 {
	480	fsl,pins = <
e1641531 SG	481	MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
e1641531 SG	482	MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
11ab21e9 ST	483	>;
	484	};
	485
07248042	486	};
a1fff236 RS	487
	488	uart4 {
	489	pinctrl_uart4_1: uart4grp-1 {
	490	fsl,pins = <
e1641531 SG	491	MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
e1641531 SG	492	MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
a1fff236 RS	493	>;
	494	};
	495	};
	496
	497	uart5 {
	498	pinctrl_uart5_1: uart5grp-1 {
	499	fsl,pins = <
e1641531 SG	500	MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
e1641531 SG	501	MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
a1fff236 RS	502	>;
	503	};
	504	};
	505
5be03a7b SG	506	};
5be03a7b SG	507
9ae90afa SH	508	pwm1: pwm@53fb4000 {
	509	#pwm-cells = <2>;
	510	compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
	511	reg = <0x53fb4000 0x4000>;
	512	clocks = <&clks 37>, <&clks 38>;
	513	clock-names = "ipg", "per";
	514	interrupts = <61>;
	515	};
	516
	517	pwm2: pwm@53fb8000 {
	518	#pwm-cells = <2>;
	519	compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
	520	reg = <0x53fb8000 0x4000>;
	521	clocks = <&clks 39>, <&clks 40>;
	522	clock-names = "ipg", "per";
	523	interrupts = <94>;
	524	};
	525
0c456cfa	526	uart1: serial@53fbc000 {
73d2b4cd SG	527	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	528	reg = <0x53fbc000 0x4000>;
	529	interrupts = <31>;
f40f38d1 FE	530	clocks = <&clks 28>, <&clks 29>;
f40f38d1 FE	531	clock-names = "ipg", "per";
73d2b4cd SG	532	status = "disabled";
	533	};
	534
0c456cfa	535	uart2: serial@53fc0000 {
73d2b4cd SG	536	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	537	reg = <0x53fc0000 0x4000>;
	538	interrupts = <32>;
f40f38d1 FE	539	clocks = <&clks 30>, <&clks 31>;
f40f38d1 FE	540	clock-names = "ipg", "per";
73d2b4cd SG	541	status = "disabled";
	542	};
	543
a9d1f924 ST	544	can1: can@53fc8000 {
	545	compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
	546	reg = <0x53fc8000 0x4000>;
	547	interrupts = <82>;
f40f38d1 FE	548	clocks = <&clks 158>, <&clks 157>;
f40f38d1 FE	549	clock-names = "ipg", "per";
a9d1f924 ST	550	status = "disabled";
	551	};
	552
	553	can2: can@53fcc000 {
	554	compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
	555	reg = <0x53fcc000 0x4000>;
	556	interrupts = <83>;
e37f0d5b	557	clocks = <&clks 87>, <&clks 86>;
f40f38d1	558	clock-names = "ipg", "per";
a9d1f924 ST	559	status = "disabled";
	560	};
	561
f40f38d1 FE	562	clks: ccm@53fd4000{
	563	compatible = "fsl,imx53-ccm";
	564	reg = <0x53fd4000 0x4000>;
	565	interrupts = <0 71 0x04 0 72 0x04>;
	566	#clock-cells = <1>;
	567	};
	568
4d191868	569	gpio5: gpio@53fdc000 {
aeb27748	570	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	571	reg = <0x53fdc000 0x4000>;
	572	interrupts = <103 104>;
	573	gpio-controller;
	574	#gpio-cells = <2>;
	575	interrupt-controller;
88cde8b7	576	#interrupt-cells = <2>;
73d2b4cd SG	577	};
73d2b4cd SG	578
4d191868	579	gpio6: gpio@53fe0000 {
aeb27748	580	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	581	reg = <0x53fe0000 0x4000>;
	582	interrupts = <105 106>;
	583	gpio-controller;
	584	#gpio-cells = <2>;
	585	interrupt-controller;
88cde8b7	586	#interrupt-cells = <2>;
73d2b4cd SG	587	};
73d2b4cd SG	588
4d191868	589	gpio7: gpio@53fe4000 {
aeb27748	590	compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
73d2b4cd SG	591	reg = <0x53fe4000 0x4000>;
	592	interrupts = <107 108>;
	593	gpio-controller;
	594	#gpio-cells = <2>;
	595	interrupt-controller;
88cde8b7	596	#interrupt-cells = <2>;
73d2b4cd SG	597	};
73d2b4cd SG	598
7b7d6727	599	i2c3: i2c@53fec000 {
73d2b4cd SG	600	#address-cells = <1>;
73d2b4cd SG	601	#size-cells = <0>;
5bdfba29	602	compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd SG	603	reg = <0x53fec000 0x4000>;
73d2b4cd SG	604	interrupts = <64>;
f40f38d1	605	clocks = <&clks 88>;
73d2b4cd SG	606	status = "disabled";
	607	};
	608
0c456cfa	609	uart4: serial@53ff0000 {
73d2b4cd SG	610	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	611	reg = <0x53ff0000 0x4000>;
	612	interrupts = <13>;
f40f38d1 FE	613	clocks = <&clks 65>, <&clks 66>;
f40f38d1 FE	614	clock-names = "ipg", "per";
73d2b4cd SG	615	status = "disabled";
	616	};
	617	};
	618
	619	aips@60000000 { /* AIPS2 */
	620	compatible = "fsl,aips-bus", "simple-bus";
	621	#address-cells = <1>;
	622	#size-cells = <1>;
	623	reg = <0x60000000 0x10000000>;
	624	ranges;
	625
0c456cfa	626	uart5: serial@63f90000 {
73d2b4cd SG	627	compatible = "fsl,imx53-uart", "fsl,imx21-uart";
	628	reg = <0x63f90000 0x4000>;
	629	interrupts = <86>;
f40f38d1 FE	630	clocks = <&clks 67>, <&clks 68>;
f40f38d1 FE	631	clock-names = "ipg", "per";
73d2b4cd SG	632	status = "disabled";
	633	};
	634
a82b7b9c MF	635	owire: owire@63fa4000 {
	636	compatible = "fsl,imx53-owire", "fsl,imx21-owire";
	637	reg = <0x63fa4000 0x4000>;
	638	clocks = <&clks 159>;
	639	status = "disabled";
	640	};
	641
7b7d6727	642	ecspi2: ecspi@63fac000 {
73d2b4cd SG	643	#address-cells = <1>;
	644	#size-cells = <0>;
	645	compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
	646	reg = <0x63fac000 0x4000>;
	647	interrupts = <37>;
f40f38d1 FE	648	clocks = <&clks 53>, <&clks 54>;
f40f38d1 FE	649	clock-names = "ipg", "per";
73d2b4cd SG	650	status = "disabled";
	651	};
	652
7b7d6727	653	sdma: sdma@63fb0000 {
73d2b4cd SG	654	compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
	655	reg = <0x63fb0000 0x4000>;
	656	interrupts = <6>;
f40f38d1 FE	657	clocks = <&clks 56>, <&clks 56>;
f40f38d1 FE	658	clock-names = "ipg", "ahb";
7e4f0365	659	fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
73d2b4cd SG	660	};
73d2b4cd SG	661
7b7d6727	662	cspi: cspi@63fc0000 {
73d2b4cd SG	663	#address-cells = <1>;
	664	#size-cells = <0>;
	665	compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
	666	reg = <0x63fc0000 0x4000>;
	667	interrupts = <38>;
f40f38d1 FE	668	clocks = <&clks 55>, <&clks 0>;
f40f38d1 FE	669	clock-names = "ipg", "per";
73d2b4cd SG	670	status = "disabled";
	671	};
	672
7b7d6727	673	i2c2: i2c@63fc4000 {
73d2b4cd SG	674	#address-cells = <1>;
73d2b4cd SG	675	#size-cells = <0>;
5bdfba29	676	compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd SG	677	reg = <0x63fc4000 0x4000>;
73d2b4cd SG	678	interrupts = <63>;
f40f38d1	679	clocks = <&clks 35>;
73d2b4cd SG	680	status = "disabled";
	681	};
	682
7b7d6727	683	i2c1: i2c@63fc8000 {
73d2b4cd SG	684	#address-cells = <1>;
73d2b4cd SG	685	#size-cells = <0>;
5bdfba29	686	compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
73d2b4cd SG	687	reg = <0x63fc8000 0x4000>;
73d2b4cd SG	688	interrupts = <62>;
f40f38d1	689	clocks = <&clks 34>;
73d2b4cd SG	690	status = "disabled";
	691	};
	692
ffc505c0 SG	693	ssi1: ssi@63fcc000 {
	694	compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
	695	reg = <0x63fcc000 0x4000>;
	696	interrupts = <29>;
f40f38d1	697	clocks = <&clks 48>;
ffc505c0 SG	698	fsl,fifo-depth = <15>;
	699	fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
	700	status = "disabled";
	701	};
	702
7b7d6727	703	audmux: audmux@63fd0000 {
ffc505c0 SG	704	compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
	705	reg = <0x63fd0000 0x4000>;
	706	status = "disabled";
	707	};
	708
7b7d6727	709	nfc: nand@63fdb000 {
75453a08 SH	710	compatible = "fsl,imx53-nand";
	711	reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
	712	interrupts = <8>;
f40f38d1	713	clocks = <&clks 60>;
75453a08 SH	714	status = "disabled";
	715	};
	716
ffc505c0 SG	717	ssi3: ssi@63fe8000 {
	718	compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
	719	reg = <0x63fe8000 0x4000>;
	720	interrupts = <96>;
f40f38d1	721	clocks = <&clks 50>;
ffc505c0 SG	722	fsl,fifo-depth = <15>;
	723	fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
	724	status = "disabled";
	725	};
	726
7b7d6727	727	fec: ethernet@63fec000 {
73d2b4cd SG	728	compatible = "fsl,imx53-fec", "fsl,imx25-fec";
	729	reg = <0x63fec000 0x4000>;
	730	interrupts = <87>;
f40f38d1 FE	731	clocks = <&clks 42>, <&clks 42>, <&clks 42>;
f40f38d1 FE	732	clock-names = "ipg", "ahb", "ptp";
73d2b4cd SG	733	status = "disabled";
	734	};
	735	};
	736	};
	737	};