projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| f46af111 FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | // | |
| 3 | // Copyright 2011 Freescale Semiconductor, Inc. | |
| 4 | // Copyright 2011 Linaro Ltd. | |
| 73d2b4cd | 5 | |
| e1641531 | 6 | #include "imx53-pinfunc.h" |
| 564695dd | 7 | #include <dt-bindings/clock/imx5-clock.h> |
| 4e05a7af DC |
8 | #include <dt-bindings/gpio/gpio.h> |
| 9 | #include <dt-bindings/input/input.h> | |
| 34adba71 | 10 | #include <dt-bindings/interrupt-controller/irq.h> |
| 73d2b4cd SG |
11 | |
| 12 | / { | |
| 7f107887 FE |
13 | #address-cells = <1>; |
| 14 | #size-cells = <1>; | |
| a971c554 FE |
15 | /* |
| 16 | * The decompressor and also some bootloaders rely on a | |
| 17 | * pre-existing /chosen node to be available to insert the | |
| 18 | * command line and merge other ATAGS info. | |
| a971c554 FE |
19 | */ |
| 20 | chosen {}; | |
| 7f107887 | 21 | |
| 73d2b4cd | 22 | aliases { |
| 22970070 | 23 | ethernet0 = &fec; |
| 5230f8fe SG |
24 | gpio0 = &gpio1; |
| 25 | gpio1 = &gpio2; | |
| 26 | gpio2 = &gpio3; | |
| 27 | gpio3 = &gpio4; | |
| 28 | gpio4 = &gpio5; | |
| 29 | gpio5 = &gpio6; | |
| 30 | gpio6 = &gpio7; | |
| c60dc1d1 PZ |
31 | i2c0 = &i2c1; |
| 32 | i2c1 = &i2c2; | |
| 33 | i2c2 = &i2c3; | |
| e5ad3230 | 34 | ipu0 = &ipu; |
| c63d06de SH |
35 | mmc0 = &esdhc1; |
| 36 | mmc1 = &esdhc2; | |
| 37 | mmc2 = &esdhc3; | |
| 38 | mmc3 = &esdhc4; | |
| cf4e577e SH |
39 | serial0 = &uart1; |
| 40 | serial1 = &uart2; | |
| 41 | serial2 = &uart3; | |
| 42 | serial3 = &uart4; | |
| 43 | serial4 = &uart5; | |
| 44 | spi0 = &ecspi1; | |
| 45 | spi1 = &ecspi2; | |
| 46 | spi2 = &cspi; | |
| 73d2b4cd SG |
47 | }; |
| 48 | ||
| 070bd7e4 FE |
49 | cpus { |
| 50 | #address-cells = <1>; | |
| 51 | #size-cells = <0>; | |
| 791f4166 | 52 | cpu0: cpu@0 { |
| 070bd7e4 FE |
53 | device_type = "cpu"; |
| 54 | compatible = "arm,cortex-a8"; | |
| 55 | reg = <0x0>; | |
| 791f4166 LS |
56 | clocks = <&clks IMX5_CLK_ARM>; |
| 57 | clock-latency = <61036>; | |
| 58 | voltage-tolerance = <5>; | |
| 59 | operating-points = < | |
| 60 | /* kHz */ | |
| 61 | 166666 850000 | |
| 62 | 400000 900000 | |
| 63 | 800000 1050000 | |
| 64 | 1000000 1200000 | |
| 65 | 1200000 1300000 | |
| 66 | >; | |
| 070bd7e4 FE |
67 | }; |
| 68 | }; | |
| 69 | ||
| e05c8c9a PZ |
70 | display-subsystem { |
| 71 | compatible = "fsl,imx-display-subsystem"; | |
| 72 | ports = <&ipu_di0>, <&ipu_di1>; | |
| 73 | }; | |
| 74 | ||
| e5ad3230 SL |
75 | capture_subsystem { |
| 76 | compatible = "fsl,imx-capture-subsystem"; | |
| 77 | ports = <&ipu_csi0>, <&ipu_csi1>; | |
| 78 | }; | |
| 79 | ||
| 8dccafaa | 80 | tzic: tz-interrupt-controller@fffc000 { |
| 73d2b4cd SG |
81 | compatible = "fsl,imx53-tzic", "fsl,tzic"; |
| 82 | interrupt-controller; | |
| 83 | #interrupt-cells = <1>; | |
| 84 | reg = <0x0fffc000 0x4000>; | |
| 85 | }; | |
| 86 | ||
| 87 | clocks { | |
| 73d2b4cd SG |
88 | ckil { |
| 89 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
| 4b2b4043 | 90 | #clock-cells = <0>; |
| 73d2b4cd SG |
91 | clock-frequency = <32768>; |
| 92 | }; | |
| 93 | ||
| 94 | ckih1 { | |
| 95 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
| 4b2b4043 | 96 | #clock-cells = <0>; |
| 73d2b4cd SG |
97 | clock-frequency = <22579200>; |
| 98 | }; | |
| 99 | ||
| 100 | ckih2 { | |
| 101 | compatible = "fsl,imx-ckih2", "fixed-clock"; | |
| 4b2b4043 | 102 | #clock-cells = <0>; |
| 73d2b4cd SG |
103 | clock-frequency = <0>; |
| 104 | }; | |
| 105 | ||
| 106 | osc { | |
| 107 | compatible = "fsl,imx-osc", "fixed-clock"; | |
| 4b2b4043 | 108 | #clock-cells = <0>; |
| 73d2b4cd SG |
109 | clock-frequency = <24000000>; |
| 110 | }; | |
| 111 | }; | |
| 112 | ||
| 4a2190aa | 113 | pmu: pmu { |
| 5b232744 FE |
114 | compatible = "arm,cortex-a8-pmu"; |
| 115 | interrupt-parent = <&tzic>; | |
| 116 | interrupts = <77>; | |
| 117 | }; | |
| 118 | ||
| 119 | usbphy0: usbphy-0 { | |
| 120 | compatible = "usb-nop-xceiv"; | |
| 121 | clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; | |
| 122 | clock-names = "main_clk"; | |
| 123 | #phy-cells = <0>; | |
| 124 | status = "okay"; | |
| 125 | }; | |
| 126 | ||
| 127 | usbphy1: usbphy-1 { | |
| 128 | compatible = "usb-nop-xceiv"; | |
| 129 | clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; | |
| 130 | clock-names = "main_clk"; | |
| 131 | #phy-cells = <0>; | |
| 132 | status = "okay"; | |
| 133 | }; | |
| 134 | ||
| 73d2b4cd SG |
135 | soc { |
| 136 | #address-cells = <1>; | |
| 137 | #size-cells = <1>; | |
| 138 | compatible = "simple-bus"; | |
| 139 | interrupt-parent = <&tzic>; | |
| 140 | ranges; | |
| 141 | ||
| 7affee43 MV |
142 | sata: sata@10000000 { |
| 143 | compatible = "fsl,imx53-ahci"; | |
| 144 | reg = <0x10000000 0x1000>; | |
| 145 | interrupts = <28>; | |
| 146 | clocks = <&clks IMX5_CLK_SATA_GATE>, | |
| 147 | <&clks IMX5_CLK_SATA_REF>, | |
| 148 | <&clks IMX5_CLK_AHB>; | |
| 02578153 | 149 | clock-names = "sata", "sata_ref", "ahb"; |
| 7affee43 MV |
150 | status = "disabled"; |
| 151 | }; | |
| 152 | ||
| abed9a6b | 153 | ipu: ipu@18000000 { |
| e05c8c9a PZ |
154 | #address-cells = <1>; |
| 155 | #size-cells = <0>; | |
| abed9a6b | 156 | compatible = "fsl,imx53-ipu"; |
| 6d66da89 | 157 | reg = <0x18000000 0x08000000>; |
| abed9a6b | 158 | interrupts = <11 10>; |
| 564695dd | 159 | clocks = <&clks IMX5_CLK_IPU_GATE>, |
| 46311707 JT |
160 | <&clks IMX5_CLK_IPU_DI0_GATE>, |
| 161 | <&clks IMX5_CLK_IPU_DI1_GATE>; | |
| 4438a6a1 | 162 | clock-names = "bus", "di0", "di1"; |
| 8d84c374 | 163 | resets = <&src 2>; |
| e05c8c9a | 164 | |
| 2a8e583c FL |
165 | ipu_csi0: port@0 { |
| 166 | reg = <0>; | |
| e5ad3230 SL |
167 | |
| 168 | ipu_csi0_from_parallel_sensor: endpoint { | |
| 169 | }; | |
| 2a8e583c FL |
170 | }; |
| 171 | ||
| 172 | ipu_csi1: port@1 { | |
| 173 | reg = <1>; | |
| e5ad3230 SL |
174 | |
| 175 | ipu_csi1_from_parallel_sensor: endpoint { | |
| 176 | }; | |
| 2a8e583c FL |
177 | }; |
| 178 | ||
| e05c8c9a PZ |
179 | ipu_di0: port@2 { |
| 180 | #address-cells = <1>; | |
| 181 | #size-cells = <0>; | |
| 182 | reg = <2>; | |
| 183 | ||
| 184 | ipu_di0_disp0: endpoint@0 { | |
| 185 | reg = <0>; | |
| 186 | }; | |
| 187 | ||
| 188 | ipu_di0_lvds0: endpoint@1 { | |
| 189 | reg = <1>; | |
| 190 | remote-endpoint = <&lvds0_in>; | |
| 191 | }; | |
| 192 | }; | |
| 193 | ||
| 194 | ipu_di1: port@3 { | |
| 195 | #address-cells = <1>; | |
| 196 | #size-cells = <0>; | |
| 197 | reg = <3>; | |
| 198 | ||
| 199 | ipu_di1_disp1: endpoint@0 { | |
| 200 | reg = <0>; | |
| 201 | }; | |
| 202 | ||
| 203 | ipu_di1_lvds1: endpoint@1 { | |
| 204 | reg = <1>; | |
| 205 | remote-endpoint = <&lvds1_in>; | |
| 206 | }; | |
| 207 | ||
| 208 | ipu_di1_tve: endpoint@2 { | |
| 209 | reg = <2>; | |
| 210 | remote-endpoint = <&tve_in>; | |
| 211 | }; | |
| 212 | }; | |
| abed9a6b SH |
213 | }; |
| 214 | ||
| 006303d6 JM |
215 | gpu: gpu@30000000 { |
| 216 | compatible = "amd,imageon-200.0", "amd,imageon"; | |
| 217 | reg = <0x30000000 0x20000>; | |
| 218 | reg-names = "kgsl_3d0_reg_memory"; | |
| 219 | interrupts = <12>; | |
| 220 | interrupt-names = "kgsl_3d0_irq"; | |
| 221 | clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; | |
| 222 | clock-names = "core_clk", "mem_iface_clk"; | |
| 223 | }; | |
| 224 | ||
| 73d2b4cd SG |
225 | aips@50000000 { /* AIPS1 */ |
| 226 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 227 | #address-cells = <1>; | |
| 228 | #size-cells = <1>; | |
| 229 | reg = <0x50000000 0x10000000>; | |
| 230 | ranges; | |
| 231 | ||
| 232 | spba@50000000 { | |
| 233 | compatible = "fsl,spba-bus", "simple-bus"; | |
| 234 | #address-cells = <1>; | |
| 235 | #size-cells = <1>; | |
| 236 | reg = <0x50000000 0x40000>; | |
| 237 | ranges; | |
| 238 | ||
| 7b7d6727 | 239 | esdhc1: esdhc@50004000 { |
| 73d2b4cd SG |
240 | compatible = "fsl,imx53-esdhc"; |
| 241 | reg = <0x50004000 0x4000>; | |
| 242 | interrupts = <1>; | |
| 564695dd | 243 | clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, |
| 46311707 JT |
244 | <&clks IMX5_CLK_DUMMY>, |
| 245 | <&clks IMX5_CLK_ESDHC1_PER_GATE>; | |
| f40f38d1 | 246 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 247 | bus-width = <4>; |
| 73d2b4cd SG |
248 | status = "disabled"; |
| 249 | }; | |
| 250 | ||
| 7b7d6727 | 251 | esdhc2: esdhc@50008000 { |
| 73d2b4cd SG |
252 | compatible = "fsl,imx53-esdhc"; |
| 253 | reg = <0x50008000 0x4000>; | |
| 254 | interrupts = <2>; | |
| 564695dd | 255 | clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, |
| 46311707 JT |
256 | <&clks IMX5_CLK_DUMMY>, |
| 257 | <&clks IMX5_CLK_ESDHC2_PER_GATE>; | |
| f40f38d1 | 258 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 259 | bus-width = <4>; |
| 73d2b4cd SG |
260 | status = "disabled"; |
| 261 | }; | |
| 262 | ||
| 0c456cfa | 263 | uart3: serial@5000c000 { |
| 73d2b4cd SG |
264 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 265 | reg = <0x5000c000 0x4000>; | |
| 266 | interrupts = <33>; | |
| 564695dd | 267 | clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, |
| 46311707 | 268 | <&clks IMX5_CLK_UART3_PER_GATE>; |
| f40f38d1 | 269 | clock-names = "ipg", "per"; |
| d04eba90 FL |
270 | dmas = <&sdma 42 4 0>, <&sdma 43 4 0>; |
| 271 | dma-names = "rx", "tx"; | |
| 73d2b4cd SG |
272 | status = "disabled"; |
| 273 | }; | |
| 274 | ||
| 5a2ecf0d | 275 | ecspi1: spi@50010000 { |
| 73d2b4cd SG |
276 | #address-cells = <1>; |
| 277 | #size-cells = <0>; | |
| 278 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
| 279 | reg = <0x50010000 0x4000>; | |
| 280 | interrupts = <36>; | |
| 564695dd | 281 | clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, |
| 46311707 | 282 | <&clks IMX5_CLK_ECSPI1_PER_GATE>; |
| f40f38d1 | 283 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
284 | status = "disabled"; |
| 285 | }; | |
| 286 | ||
| ffc505c0 | 287 | ssi2: ssi@50014000 { |
| 6ff7f51e | 288 | #sound-dai-cells = <0>; |
| 28f93d0b MP |
289 | compatible = "fsl,imx53-ssi", |
| 290 | "fsl,imx51-ssi", | |
| 291 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
292 | reg = <0x50014000 0x4000>; |
| 293 | interrupts = <30>; | |
| 685570ab FE |
294 | clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, |
| 295 | <&clks IMX5_CLK_SSI2_ROOT_GATE>; | |
| 296 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
297 | dmas = <&sdma 24 1 0>, |
| 298 | <&sdma 25 1 0>; | |
| 299 | dma-names = "rx", "tx"; | |
| ffc505c0 | 300 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
301 | status = "disabled"; |
| 302 | }; | |
| 303 | ||
| 7b7d6727 | 304 | esdhc3: esdhc@50020000 { |
| 73d2b4cd SG |
305 | compatible = "fsl,imx53-esdhc"; |
| 306 | reg = <0x50020000 0x4000>; | |
| 307 | interrupts = <3>; | |
| 564695dd | 308 | clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, |
| 46311707 JT |
309 | <&clks IMX5_CLK_DUMMY>, |
| 310 | <&clks IMX5_CLK_ESDHC3_PER_GATE>; | |
| f40f38d1 | 311 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 312 | bus-width = <4>; |
| 73d2b4cd SG |
313 | status = "disabled"; |
| 314 | }; | |
| 315 | ||
| 7b7d6727 | 316 | esdhc4: esdhc@50024000 { |
| 73d2b4cd SG |
317 | compatible = "fsl,imx53-esdhc"; |
| 318 | reg = <0x50024000 0x4000>; | |
| 319 | interrupts = <4>; | |
| 564695dd | 320 | clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, |
| 46311707 JT |
321 | <&clks IMX5_CLK_DUMMY>, |
| 322 | <&clks IMX5_CLK_ESDHC4_PER_GATE>; | |
| f40f38d1 | 323 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 324 | bus-width = <4>; |
| 73d2b4cd SG |
325 | status = "disabled"; |
| 326 | }; | |
| 327 | }; | |
| 328 | ||
| ac08281e ST |
329 | aipstz1: bridge@53f00000 { |
| 330 | compatible = "fsl,imx53-aipstz"; | |
| 331 | reg = <0x53f00000 0x60>; | |
| 332 | }; | |
| 333 | ||
| 7b7d6727 | 334 | usbotg: usb@53f80000 { |
| 212d0b83 MG |
335 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 336 | reg = <0x53f80000 0x0200>; | |
| 337 | interrupts = <18>; | |
| 564695dd | 338 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 339 | fsl,usbmisc = <&usbmisc 0>; |
| a79025c4 | 340 | fsl,usbphy = <&usbphy0>; |
| 212d0b83 MG |
341 | status = "disabled"; |
| 342 | }; | |
| 343 | ||
| 7b7d6727 | 344 | usbh1: usb@53f80200 { |
| 212d0b83 MG |
345 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 346 | reg = <0x53f80200 0x0200>; | |
| 347 | interrupts = <14>; | |
| 564695dd | 348 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 349 | fsl,usbmisc = <&usbmisc 1>; |
| a79025c4 | 350 | fsl,usbphy = <&usbphy1>; |
| 3ec481ed | 351 | dr_mode = "host"; |
| 212d0b83 MG |
352 | status = "disabled"; |
| 353 | }; | |
| 354 | ||
| 7b7d6727 | 355 | usbh2: usb@53f80400 { |
| 212d0b83 MG |
356 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 357 | reg = <0x53f80400 0x0200>; | |
| 358 | interrupts = <16>; | |
| 564695dd | 359 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 360 | fsl,usbmisc = <&usbmisc 2>; |
| 3ec481ed | 361 | dr_mode = "host"; |
| 212d0b83 MG |
362 | status = "disabled"; |
| 363 | }; | |
| 364 | ||
| 7b7d6727 | 365 | usbh3: usb@53f80600 { |
| 212d0b83 MG |
366 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 367 | reg = <0x53f80600 0x0200>; | |
| 368 | interrupts = <17>; | |
| 564695dd | 369 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 | 370 | fsl,usbmisc = <&usbmisc 3>; |
| 3ec481ed | 371 | dr_mode = "host"; |
| 212d0b83 MG |
372 | status = "disabled"; |
| 373 | }; | |
| 374 | ||
| a5735021 MG |
375 | usbmisc: usbmisc@53f80800 { |
| 376 | #index-cells = <1>; | |
| 377 | compatible = "fsl,imx53-usbmisc"; | |
| 378 | reg = <0x53f80800 0x200>; | |
| 564695dd | 379 | clocks = <&clks IMX5_CLK_USBOH3_GATE>; |
| a5735021 MG |
380 | }; |
| 381 | ||
| 4d191868 | 382 | gpio1: gpio@53f84000 { |
| aeb27748 | 383 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
384 | reg = <0x53f84000 0x4000>; |
| 385 | interrupts = <50 51>; | |
| 386 | gpio-controller; | |
| 387 | #gpio-cells = <2>; | |
| 388 | interrupt-controller; | |
| 88cde8b7 | 389 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
390 | }; |
| 391 | ||
| 4d191868 | 392 | gpio2: gpio@53f88000 { |
| aeb27748 | 393 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
394 | reg = <0x53f88000 0x4000>; |
| 395 | interrupts = <52 53>; | |
| 396 | gpio-controller; | |
| 397 | #gpio-cells = <2>; | |
| 398 | interrupt-controller; | |
| 88cde8b7 | 399 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
400 | }; |
| 401 | ||
| 4d191868 | 402 | gpio3: gpio@53f8c000 { |
| aeb27748 | 403 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
404 | reg = <0x53f8c000 0x4000>; |
| 405 | interrupts = <54 55>; | |
| 406 | gpio-controller; | |
| 407 | #gpio-cells = <2>; | |
| 408 | interrupt-controller; | |
| 88cde8b7 | 409 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
410 | }; |
| 411 | ||
| 4d191868 | 412 | gpio4: gpio@53f90000 { |
| aeb27748 | 413 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
414 | reg = <0x53f90000 0x4000>; |
| 415 | interrupts = <56 57>; | |
| 416 | gpio-controller; | |
| 417 | #gpio-cells = <2>; | |
| 418 | interrupt-controller; | |
| 88cde8b7 | 419 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
420 | }; |
| 421 | ||
| 675e4d03 RL |
422 | kpp: kpp@53f94000 { |
| 423 | compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; | |
| 424 | reg = <0x53f94000 0x4000>; | |
| 425 | interrupts = <60>; | |
| 564695dd | 426 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 675e4d03 RL |
427 | status = "disabled"; |
| 428 | }; | |
| 429 | ||
| 7b7d6727 | 430 | wdog1: wdog@53f98000 { |
| 73d2b4cd SG |
431 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 432 | reg = <0x53f98000 0x4000>; | |
| 433 | interrupts = <58>; | |
| 564695dd | 434 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 73d2b4cd SG |
435 | }; |
| 436 | ||
| 7b7d6727 | 437 | wdog2: wdog@53f9c000 { |
| 73d2b4cd SG |
438 | compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; |
| 439 | reg = <0x53f9c000 0x4000>; | |
| 440 | interrupts = <59>; | |
| 564695dd | 441 | clocks = <&clks IMX5_CLK_DUMMY>; |
| 73d2b4cd SG |
442 | status = "disabled"; |
| 443 | }; | |
| 444 | ||
| cc8aae9b SH |
445 | gpt: timer@53fa0000 { |
| 446 | compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; | |
| 447 | reg = <0x53fa0000 0x4000>; | |
| 448 | interrupts = <39>; | |
| 564695dd | 449 | clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, |
| 46311707 | 450 | <&clks IMX5_CLK_GPT_HF_GATE>; |
| cc8aae9b SH |
451 | clock-names = "ipg", "per"; |
| 452 | }; | |
| 453 | ||
| 3473a3a1 PB |
454 | srtc: rtc@53fa4000 { |
| 455 | compatible = "fsl,imx53-rtc"; | |
| 456 | reg = <0x53fa4000 0x4000>; | |
| 457 | interrupts = <24>; | |
| 458 | clocks = <&clks IMX5_CLK_SRTC_GATE>; | |
| 459 | }; | |
| 460 | ||
| 7b7d6727 | 461 | iomuxc: iomuxc@53fa8000 { |
| 5be03a7b SG |
462 | compatible = "fsl,imx53-iomuxc"; |
| 463 | reg = <0x53fa8000 0x4000>; | |
| 5be03a7b SG |
464 | }; |
| 465 | ||
| 5af9f143 PZ |
466 | gpr: iomuxc-gpr@53fa8000 { |
| 467 | compatible = "fsl,imx53-iomuxc-gpr", "syscon"; | |
| 468 | reg = <0x53fa8000 0xc>; | |
| 469 | }; | |
| 470 | ||
| 420714aa PZ |
471 | ldb: ldb@53fa8008 { |
| 472 | #address-cells = <1>; | |
| 473 | #size-cells = <0>; | |
| 474 | compatible = "fsl,imx53-ldb"; | |
| 475 | reg = <0x53fa8008 0x4>; | |
| 476 | gpr = <&gpr>; | |
| 564695dd | 477 | clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, |
| 46311707 JT |
478 | <&clks IMX5_CLK_LDB_DI1_SEL>, |
| 479 | <&clks IMX5_CLK_IPU_DI0_SEL>, | |
| 480 | <&clks IMX5_CLK_IPU_DI1_SEL>, | |
| 481 | <&clks IMX5_CLK_LDB_DI0_GATE>, | |
| 482 | <&clks IMX5_CLK_LDB_DI1_GATE>; | |
| 420714aa PZ |
483 | clock-names = "di0_pll", "di1_pll", |
| 484 | "di0_sel", "di1_sel", | |
| 485 | "di0", "di1"; | |
| 486 | status = "disabled"; | |
| 487 | ||
| 488 | lvds-channel@0 { | |
| 1b134c9c MN |
489 | #address-cells = <1>; |
| 490 | #size-cells = <0>; | |
| 420714aa | 491 | reg = <0>; |
| 420714aa | 492 | status = "disabled"; |
| e05c8c9a | 493 | |
| 1b134c9c MN |
494 | port@0 { |
| 495 | reg = <0>; | |
| 496 | ||
| e05c8c9a PZ |
497 | lvds0_in: endpoint { |
| 498 | remote-endpoint = <&ipu_di0_lvds0>; | |
| 499 | }; | |
| 500 | }; | |
| 77dd4bd0 RH |
501 | |
| 502 | port@2 { | |
| 503 | reg = <2>; | |
| 504 | }; | |
| 420714aa PZ |
505 | }; |
| 506 | ||
| 507 | lvds-channel@1 { | |
| 1b134c9c MN |
508 | #address-cells = <1>; |
| 509 | #size-cells = <0>; | |
| 420714aa | 510 | reg = <1>; |
| 420714aa | 511 | status = "disabled"; |
| e05c8c9a | 512 | |
| 1b134c9c MN |
513 | port@1 { |
| 514 | reg = <1>; | |
| 515 | ||
| e05c8c9a | 516 | lvds1_in: endpoint { |
| fa1746ae | 517 | remote-endpoint = <&ipu_di1_lvds1>; |
| e05c8c9a PZ |
518 | }; |
| 519 | }; | |
| 77dd4bd0 RH |
520 | |
| 521 | port@2 { | |
| 522 | reg = <2>; | |
| 523 | }; | |
| 420714aa PZ |
524 | }; |
| 525 | }; | |
| 526 | ||
| 9ae90afa SH |
527 | pwm1: pwm@53fb4000 { |
| 528 | #pwm-cells = <2>; | |
| 529 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
| 530 | reg = <0x53fb4000 0x4000>; | |
| 564695dd | 531 | clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, |
| 46311707 | 532 | <&clks IMX5_CLK_PWM1_HF_GATE>; |
| 9ae90afa SH |
533 | clock-names = "ipg", "per"; |
| 534 | interrupts = <61>; | |
| 535 | }; | |
| 536 | ||
| 537 | pwm2: pwm@53fb8000 { | |
| 538 | #pwm-cells = <2>; | |
| 539 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | |
| 540 | reg = <0x53fb8000 0x4000>; | |
| 564695dd | 541 | clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, |
| 46311707 | 542 | <&clks IMX5_CLK_PWM2_HF_GATE>; |
| 9ae90afa SH |
543 | clock-names = "ipg", "per"; |
| 544 | interrupts = <94>; | |
| 545 | }; | |
| 546 | ||
| 0c456cfa | 547 | uart1: serial@53fbc000 { |
| 73d2b4cd SG |
548 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 549 | reg = <0x53fbc000 0x4000>; | |
| 550 | interrupts = <31>; | |
| 564695dd | 551 | clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, |
| 46311707 | 552 | <&clks IMX5_CLK_UART1_PER_GATE>; |
| f40f38d1 | 553 | clock-names = "ipg", "per"; |
| d04eba90 FL |
554 | dmas = <&sdma 18 4 0>, <&sdma 19 4 0>; |
| 555 | dma-names = "rx", "tx"; | |
| 73d2b4cd SG |
556 | status = "disabled"; |
| 557 | }; | |
| 558 | ||
| 0c456cfa | 559 | uart2: serial@53fc0000 { |
| 73d2b4cd SG |
560 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 561 | reg = <0x53fc0000 0x4000>; | |
| 562 | interrupts = <32>; | |
| 564695dd | 563 | clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, |
| 46311707 | 564 | <&clks IMX5_CLK_UART2_PER_GATE>; |
| f40f38d1 | 565 | clock-names = "ipg", "per"; |
| d04eba90 FL |
566 | dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; |
| 567 | dma-names = "rx", "tx"; | |
| 73d2b4cd SG |
568 | status = "disabled"; |
| 569 | }; | |
| 570 | ||
| a9d1f924 | 571 | can1: can@53fc8000 { |
| 9a62dcf4 | 572 | compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; |
| a9d1f924 ST |
573 | reg = <0x53fc8000 0x4000>; |
| 574 | interrupts = <82>; | |
| 564695dd | 575 | clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, |
| 46311707 | 576 | <&clks IMX5_CLK_CAN1_SERIAL_GATE>; |
| f40f38d1 | 577 | clock-names = "ipg", "per"; |
| a9d1f924 ST |
578 | status = "disabled"; |
| 579 | }; | |
| 580 | ||
| 581 | can2: can@53fcc000 { | |
| 9a62dcf4 | 582 | compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; |
| a9d1f924 ST |
583 | reg = <0x53fcc000 0x4000>; |
| 584 | interrupts = <83>; | |
| 564695dd | 585 | clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, |
| 46311707 | 586 | <&clks IMX5_CLK_CAN2_SERIAL_GATE>; |
| f40f38d1 | 587 | clock-names = "ipg", "per"; |
| a9d1f924 ST |
588 | status = "disabled"; |
| 589 | }; | |
| 590 | ||
| 8d84c374 PZ |
591 | src: src@53fd0000 { |
| 592 | compatible = "fsl,imx53-src", "fsl,imx51-src"; | |
| 593 | reg = <0x53fd0000 0x4000>; | |
| 594 | #reset-cells = <1>; | |
| 595 | }; | |
| 596 | ||
| f40f38d1 FE |
597 | clks: ccm@53fd4000{ |
| 598 | compatible = "fsl,imx53-ccm"; | |
| 599 | reg = <0x53fd4000 0x4000>; | |
| 600 | interrupts = <0 71 0x04 0 72 0x04>; | |
| 601 | #clock-cells = <1>; | |
| 602 | }; | |
| 603 | ||
| 4d191868 | 604 | gpio5: gpio@53fdc000 { |
| aeb27748 | 605 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
606 | reg = <0x53fdc000 0x4000>; |
| 607 | interrupts = <103 104>; | |
| 608 | gpio-controller; | |
| 609 | #gpio-cells = <2>; | |
| 610 | interrupt-controller; | |
| 88cde8b7 | 611 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
612 | }; |
| 613 | ||
| 4d191868 | 614 | gpio6: gpio@53fe0000 { |
| aeb27748 | 615 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
616 | reg = <0x53fe0000 0x4000>; |
| 617 | interrupts = <105 106>; | |
| 618 | gpio-controller; | |
| 619 | #gpio-cells = <2>; | |
| 620 | interrupt-controller; | |
| 88cde8b7 | 621 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
622 | }; |
| 623 | ||
| 4d191868 | 624 | gpio7: gpio@53fe4000 { |
| aeb27748 | 625 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 73d2b4cd SG |
626 | reg = <0x53fe4000 0x4000>; |
| 627 | interrupts = <107 108>; | |
| 628 | gpio-controller; | |
| 629 | #gpio-cells = <2>; | |
| 630 | interrupt-controller; | |
| 88cde8b7 | 631 | #interrupt-cells = <2>; |
| 73d2b4cd SG |
632 | }; |
| 633 | ||
| 7b7d6727 | 634 | i2c3: i2c@53fec000 { |
| 73d2b4cd SG |
635 | #address-cells = <1>; |
| 636 | #size-cells = <0>; | |
| 5bdfba29 | 637 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
638 | reg = <0x53fec000 0x4000>; |
| 639 | interrupts = <64>; | |
| 564695dd | 640 | clocks = <&clks IMX5_CLK_I2C3_GATE>; |
| 73d2b4cd SG |
641 | status = "disabled"; |
| 642 | }; | |
| 643 | ||
| 0c456cfa | 644 | uart4: serial@53ff0000 { |
| 73d2b4cd SG |
645 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 646 | reg = <0x53ff0000 0x4000>; | |
| 647 | interrupts = <13>; | |
| 564695dd | 648 | clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, |
| 46311707 | 649 | <&clks IMX5_CLK_UART4_PER_GATE>; |
| f40f38d1 | 650 | clock-names = "ipg", "per"; |
| d04eba90 FL |
651 | dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; |
| 652 | dma-names = "rx", "tx"; | |
| 73d2b4cd SG |
653 | status = "disabled"; |
| 654 | }; | |
| 655 | }; | |
| 656 | ||
| 657 | aips@60000000 { /* AIPS2 */ | |
| 658 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 659 | #address-cells = <1>; | |
| 660 | #size-cells = <1>; | |
| 661 | reg = <0x60000000 0x10000000>; | |
| 662 | ranges; | |
| 663 | ||
| ac08281e ST |
664 | aipstz2: bridge@63f00000 { |
| 665 | compatible = "fsl,imx53-aipstz"; | |
| 666 | reg = <0x63f00000 0x60>; | |
| 667 | }; | |
| 668 | ||
| 4f3b2a41 SH |
669 | iim: iim@63f98000 { |
| 670 | compatible = "fsl,imx53-iim", "fsl,imx27-iim"; | |
| 671 | reg = <0x63f98000 0x4000>; | |
| 672 | interrupts = <69>; | |
| 564695dd | 673 | clocks = <&clks IMX5_CLK_IIM_GATE>; |
| 4f3b2a41 SH |
674 | }; |
| 675 | ||
| 0c456cfa | 676 | uart5: serial@63f90000 { |
| 73d2b4cd SG |
677 | compatible = "fsl,imx53-uart", "fsl,imx21-uart"; |
| 678 | reg = <0x63f90000 0x4000>; | |
| 679 | interrupts = <86>; | |
| 564695dd | 680 | clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, |
| 46311707 | 681 | <&clks IMX5_CLK_UART5_PER_GATE>; |
| f40f38d1 | 682 | clock-names = "ipg", "per"; |
| d04eba90 FL |
683 | dmas = <&sdma 16 4 0>, <&sdma 17 4 0>; |
| 684 | dma-names = "rx", "tx"; | |
| 73d2b4cd SG |
685 | status = "disabled"; |
| 686 | }; | |
| 687 | ||
| e548eac2 FE |
688 | tigerp: tigerp@63fa0000 { |
| 689 | compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp"; | |
| 690 | reg = <0x63fa0000 0x28>; | |
| 691 | }; | |
| 692 | ||
| a82b7b9c MF |
693 | owire: owire@63fa4000 { |
| 694 | compatible = "fsl,imx53-owire", "fsl,imx21-owire"; | |
| 695 | reg = <0x63fa4000 0x4000>; | |
| 564695dd | 696 | clocks = <&clks IMX5_CLK_OWIRE_GATE>; |
| a82b7b9c MF |
697 | status = "disabled"; |
| 698 | }; | |
| 699 | ||
| 5a2ecf0d | 700 | ecspi2: spi@63fac000 { |
| 73d2b4cd SG |
701 | #address-cells = <1>; |
| 702 | #size-cells = <0>; | |
| 703 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; | |
| 704 | reg = <0x63fac000 0x4000>; | |
| 705 | interrupts = <37>; | |
| 564695dd | 706 | clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, |
| 46311707 | 707 | <&clks IMX5_CLK_ECSPI2_PER_GATE>; |
| f40f38d1 | 708 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
709 | status = "disabled"; |
| 710 | }; | |
| 711 | ||
| 7b7d6727 | 712 | sdma: sdma@63fb0000 { |
| 73d2b4cd SG |
713 | compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; |
| 714 | reg = <0x63fb0000 0x4000>; | |
| 715 | interrupts = <6>; | |
| 564695dd | 716 | clocks = <&clks IMX5_CLK_SDMA_GATE>, |
| 28c16801 | 717 | <&clks IMX5_CLK_AHB>; |
| f40f38d1 | 718 | clock-names = "ipg", "ahb"; |
| fb72bb21 | 719 | #dma-cells = <3>; |
| 7e4f0365 | 720 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; |
| 73d2b4cd SG |
721 | }; |
| 722 | ||
| 5a2ecf0d | 723 | cspi: spi@63fc0000 { |
| 73d2b4cd SG |
724 | #address-cells = <1>; |
| 725 | #size-cells = <0>; | |
| 726 | compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; | |
| 727 | reg = <0x63fc0000 0x4000>; | |
| 728 | interrupts = <38>; | |
| 564695dd | 729 | clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, |
| 46311707 | 730 | <&clks IMX5_CLK_CSPI_IPG_GATE>; |
| f40f38d1 | 731 | clock-names = "ipg", "per"; |
| 73d2b4cd SG |
732 | status = "disabled"; |
| 733 | }; | |
| 734 | ||
| 7b7d6727 | 735 | i2c2: i2c@63fc4000 { |
| 73d2b4cd SG |
736 | #address-cells = <1>; |
| 737 | #size-cells = <0>; | |
| 5bdfba29 | 738 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
739 | reg = <0x63fc4000 0x4000>; |
| 740 | interrupts = <63>; | |
| 564695dd | 741 | clocks = <&clks IMX5_CLK_I2C2_GATE>; |
| 73d2b4cd SG |
742 | status = "disabled"; |
| 743 | }; | |
| 744 | ||
| 7b7d6727 | 745 | i2c1: i2c@63fc8000 { |
| 73d2b4cd SG |
746 | #address-cells = <1>; |
| 747 | #size-cells = <0>; | |
| 5bdfba29 | 748 | compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; |
| 73d2b4cd SG |
749 | reg = <0x63fc8000 0x4000>; |
| 750 | interrupts = <62>; | |
| 564695dd | 751 | clocks = <&clks IMX5_CLK_I2C1_GATE>; |
| 73d2b4cd SG |
752 | status = "disabled"; |
| 753 | }; | |
| 754 | ||
| ffc505c0 | 755 | ssi1: ssi@63fcc000 { |
| 6ff7f51e | 756 | #sound-dai-cells = <0>; |
| 28f93d0b MP |
757 | compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", |
| 758 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
759 | reg = <0x63fcc000 0x4000>; |
| 760 | interrupts = <29>; | |
| 685570ab FE |
761 | clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, |
| 762 | <&clks IMX5_CLK_SSI1_ROOT_GATE>; | |
| 763 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
764 | dmas = <&sdma 28 0 0>, |
| 765 | <&sdma 29 0 0>; | |
| 766 | dma-names = "rx", "tx"; | |
| ffc505c0 | 767 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
768 | status = "disabled"; |
| 769 | }; | |
| 770 | ||
| 7b7d6727 | 771 | audmux: audmux@63fd0000 { |
| ffc505c0 SG |
772 | compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; |
| 773 | reg = <0x63fd0000 0x4000>; | |
| 774 | status = "disabled"; | |
| 775 | }; | |
| 776 | ||
| 7b7d6727 | 777 | nfc: nand@63fdb000 { |
| 75453a08 SH |
778 | compatible = "fsl,imx53-nand"; |
| 779 | reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; | |
| 780 | interrupts = <8>; | |
| 564695dd | 781 | clocks = <&clks IMX5_CLK_NFC_GATE>; |
| 75453a08 SH |
782 | status = "disabled"; |
| 783 | }; | |
| 784 | ||
| ffc505c0 | 785 | ssi3: ssi@63fe8000 { |
| 6ff7f51e | 786 | #sound-dai-cells = <0>; |
| 28f93d0b MP |
787 | compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", |
| 788 | "fsl,imx21-ssi"; | |
| ffc505c0 SG |
789 | reg = <0x63fe8000 0x4000>; |
| 790 | interrupts = <96>; | |
| 685570ab FE |
791 | clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, |
| 792 | <&clks IMX5_CLK_SSI3_ROOT_GATE>; | |
| 793 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
794 | dmas = <&sdma 46 0 0>, |
| 795 | <&sdma 47 0 0>; | |
| 796 | dma-names = "rx", "tx"; | |
| ffc505c0 | 797 | fsl,fifo-depth = <15>; |
| ffc505c0 SG |
798 | status = "disabled"; |
| 799 | }; | |
| 800 | ||
| 7b7d6727 | 801 | fec: ethernet@63fec000 { |
| 73d2b4cd SG |
802 | compatible = "fsl,imx53-fec", "fsl,imx25-fec"; |
| 803 | reg = <0x63fec000 0x4000>; | |
| 804 | interrupts = <87>; | |
| 564695dd | 805 | clocks = <&clks IMX5_CLK_FEC_GATE>, |
| 46311707 JT |
806 | <&clks IMX5_CLK_FEC_GATE>, |
| 807 | <&clks IMX5_CLK_FEC_GATE>; | |
| f40f38d1 | 808 | clock-names = "ipg", "ahb", "ptp"; |
| 73d2b4cd SG |
809 | status = "disabled"; |
| 810 | }; | |
| 19194c2b PZ |
811 | |
| 812 | tve: tve@63ff0000 { | |
| 813 | compatible = "fsl,imx53-tve"; | |
| 814 | reg = <0x63ff0000 0x1000>; | |
| 815 | interrupts = <92>; | |
| 564695dd | 816 | clocks = <&clks IMX5_CLK_TVE_GATE>, |
| 46311707 | 817 | <&clks IMX5_CLK_IPU_DI1_SEL>; |
| 19194c2b | 818 | clock-names = "tve", "di_sel"; |
| 19194c2b | 819 | status = "disabled"; |
| e05c8c9a PZ |
820 | |
| 821 | port { | |
| 822 | tve_in: endpoint { | |
| 823 | remote-endpoint = <&ipu_di1_tve>; | |
| 824 | }; | |
| 825 | }; | |
| 19194c2b | 826 | }; |
| fbf970f6 FE |
827 | |
| 828 | vpu: vpu@63ff4000 { | |
| 71946619 | 829 | compatible = "fsl,imx53-vpu", "cnm,coda7541"; |
| fbf970f6 FE |
830 | reg = <0x63ff4000 0x1000>; |
| 831 | interrupts = <9>; | |
| fa97d2f7 | 832 | clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, |
| 46311707 | 833 | <&clks IMX5_CLK_VPU_GATE>; |
| fbf970f6 | 834 | clock-names = "per", "ahb"; |
| b1e2e546 | 835 | resets = <&src 1>; |
| fbf970f6 | 836 | iram = <&ocram>; |
| fbf970f6 | 837 | }; |
| 60811cc2 ST |
838 | |
| 839 | sahara: crypto@63ff8000 { | |
| 840 | compatible = "fsl,imx53-sahara"; | |
| 841 | reg = <0x63ff8000 0x4000>; | |
| 842 | interrupts = <19 20>; | |
| 843 | clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, | |
| 46311707 | 844 | <&clks IMX5_CLK_SAHARA_IPG_GATE>; |
| 60811cc2 ST |
845 | clock-names = "ipg", "ahb"; |
| 846 | }; | |
| 73d2b4cd | 847 | }; |
| 481fbe13 PZ |
848 | |
| 849 | ocram: sram@f8000000 { | |
| 850 | compatible = "mmio-sram"; | |
| 851 | reg = <0xf8000000 0x20000>; | |
| 564695dd | 852 | clocks = <&clks IMX5_CLK_OCRAM>; |
| 481fbe13 | 853 | }; |
| 73d2b4cd SG |
854 | }; |
| 855 | }; |