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ARM: dts: imx6qdl-wandboard: enable USB OTG
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx6dl-riotboard.dts
CommitLineData
ec55b150
IP		 1/*
2 * Copyright 2014 Iain Paton <ipaton0@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10/dts-v1/;
11#include "imx6dl.dtsi"
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15 model = "RIoTboard i.MX6S";
16 compatible = "riot,imx6s-riotboard", "fsl,imx6dl";
17
ad00e080 18 memory@10000000 {
ec55b150
IP		 19 reg = <0x10000000 0x40000000>;
20 };
21
ec55b150
IP		 22 leds {
23 compatible = "gpio-leds";
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_led>;
26
27 led0: user1 {
28 label = "user1";
29 gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
30 default-state = "on";
31 linux,default-trigger = "heartbeat";
32 };
33
34 led1: user2 {
35 label = "user2";
36 gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
37 default-state = "off";
38 };
39 };
40
41 sound {
42 compatible = "fsl,imx-audio-sgtl5000";
43 model = "imx6-riotboard-sgtl5000";
44 ssi-controller = <&ssi1>;
45 audio-codec = <&codec>;
46 audio-routing =
47 "MIC_IN", "Mic Jack",
48 "Mic Jack", "Mic Bias",
49 "Headphone Jack", "HP_OUT";
50 mux-int-port = <1>;
51 mux-ext-port = <3>;
52 };
d8d5f9dc
AK		 53
54 reg_2p5v: regulator-2p5v {
55 compatible = "regulator-fixed";
56 regulator-name = "2P5V";
57 regulator-min-microvolt = <2500000>;
58 regulator-max-microvolt = <2500000>;
59 };
60
61 reg_3p3v: regulator-3p3v {
62 compatible = "regulator-fixed";
63 regulator-name = "3P3V";
64 regulator-min-microvolt = <3300000>;
65 regulator-max-microvolt = <3300000>;
66 };
67
68 reg_usb_otg_vbus: regulator-usbotgvbus {
69 compatible = "regulator-fixed";
70 regulator-name = "usb_otg_vbus";
71 regulator-min-microvolt = <5000000>;
72 regulator-max-microvolt = <5000000>;
73 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
74 enable-active-high;
75 };
ec55b150
IP		 76};
77
78&audmux {
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_audmux>;
81 status = "okay";
82};
83
84&fec {
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_enet>;
87 phy-mode = "rgmii";
12de44f5 88 phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
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IP		 89 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
90 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
a28eeb43 91 fsl,err006687-workaround-present;
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IP		 92 status = "okay";
93};
94
e8ebecf6
OR		 95&gpio1 {
96 gpio-line-names =
97 "", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL",
98 "I2C3_SDA", "I2C4_SCL",
99 "I2C4_SDA", "", "", "", "", "", "", "",
100 "", "PWM3", "", "", "", "", "", "",
101 "", "", "", "", "", "", "", "";
102};
103
104&gpio3 {
105 gpio-line-names =
106 "", "", "", "", "", "", "", "",
107 "", "", "", "", "", "", "", "",
108 "", "", "", "", "", "", "USB_OTG_VBUS", "",
109 "UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", "";
110};
111
112&gpio4 {
113 gpio-line-names =
114 "", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
115 "UART5_TXD", "UART5_RXD", "", "", "", "", "", "",
116 "GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "",
117 "CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO",
118 "CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27",
119 "CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31";
120};
121
122&gpio5 {
123 gpio-line-names =
124 "", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06",
125 "GPIO5_07",
126 "GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO",
127 "CSPI2_CS0", "CSPI2_CLK", "", "",
128 "", "", "", "", "", "", "", "",
129 "", "", "", "", "", "", "", "";
130};
131
132&gpio7 {
133 gpio-line-names =
134 "SD3_CD", "SD3_WP", "", "", "", "", "", "",
135 "", "", "", "", "", "", "", "",
136 "", "", "", "", "", "", "", "",
137 "", "", "", "", "", "", "", "";
138};
139
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IP		 140&hdmi {
141 ddc-i2c-bus = <&i2c2>;
142 status = "okay";
143};
144
145&i2c1 {
146 clock-frequency = <100000>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_i2c1>;
149 status = "okay";
150
8dccafaa 151 codec: sgtl5000@a {
ec55b150
IP		 152 compatible = "fsl,sgtl5000";
153 reg = <0x0a>;
b26a68c1 154 clocks = <&clks IMX6QDL_CLK_CKO>;
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IP		 155 VDDA-supply = <&reg_2p5v>;
156 VDDIO-supply = <&reg_3p3v>;
157 };
158
8dccafaa 159 pmic: pf0100@8 {
ec55b150
IP		 160 compatible = "fsl,pfuze100";
161 reg = <0x08>;
162 interrupt-parent = <&gpio5>;
163 interrupts = <16 8>;
164
165 regulators {
166 reg_vddcore: sw1ab { /* VDDARM_IN */
167 regulator-min-microvolt = <300000>;
168 regulator-max-microvolt = <1875000>;
169 regulator-always-on;
170 };
171
172 reg_vddsoc: sw1c { /* VDDSOC_IN */
173 regulator-min-microvolt = <300000>;
174 regulator-max-microvolt = <1875000>;
175 regulator-always-on;
176 };
177
178 reg_gen_3v3: sw2 { /* VDDHIGH_IN */
179 regulator-min-microvolt = <800000>;
180 regulator-max-microvolt = <3300000>;
181 regulator-always-on;
182 };
183
184 reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */
185 regulator-min-microvolt = <400000>;
186 regulator-max-microvolt = <1975000>;
187 regulator-always-on;
188 };
189
190 reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */
191 regulator-min-microvolt = <400000>;
192 regulator-max-microvolt = <1975000>;
193 regulator-always-on;
194 };
195
196 reg_ddr_vtt: sw4 { /* MIPI conn */
197 regulator-min-microvolt = <400000>;
198 regulator-max-microvolt = <1975000>;
199 regulator-always-on;
200 };
201
202 reg_5v_600mA: swbst { /* not used */
203 regulator-min-microvolt = <5000000>;
204 regulator-max-microvolt = <5150000>;
205 };
206
207 reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */
208 regulator-min-microvolt = <1500000>;
209 regulator-max-microvolt = <3000000>;
210 regulator-always-on;
211 };
212
213 vref_reg: vrefddr { /* VREF_DDR */
214 regulator-boot-on;
215 regulator-always-on;
216 };
217
218 reg_vgen1_1v5: vgen1 { /* not used */
219 regulator-min-microvolt = <800000>;
220 regulator-max-microvolt = <1550000>;
221 };
222
223 reg_vgen2_1v2_eth: vgen2 { /* pcie ? */
224 regulator-min-microvolt = <800000>;
225 regulator-max-microvolt = <1550000>;
226 regulator-always-on;
227 };
228
229 reg_vgen3_2v8: vgen3 { /* not used */
230 regulator-min-microvolt = <1800000>;
231 regulator-max-microvolt = <3300000>;
232 };
233 reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */
234 regulator-min-microvolt = <1800000>;
235 regulator-max-microvolt = <3300000>;
236 regulator-always-on;
237 };
238
239 reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */
240 regulator-min-microvolt = <1800000>;
241 regulator-max-microvolt = <3300000>;
242 regulator-always-on;
243 };
244
245 reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */
246 regulator-min-microvolt = <1800000>;
247 regulator-max-microvolt = <3300000>;
248 regulator-always-on;
249 };
250 };
251 };
252};
253
254&i2c2 {
255 clock-frequency = <100000>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_i2c2>;
258 status = "okay";
259};
260
261&i2c4 {
262 clock-frequency = <100000>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_i2c4>;
265 clocks = <&clks 116>;
266 status = "okay";
267};
268
269&pwm1 {
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_pwm1>;
272 status = "okay";
273};
274
275&pwm2 {
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_pwm2>;
278 status = "okay";
279};
280
281&pwm3 {
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_pwm3>;
284 status = "okay";
285};
286
287&pwm4 {
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_pwm4>;
290 status = "okay";
291};
292
293&ssi1 {
ec55b150
IP		 294 status = "okay";
295};
296
297&uart1 {
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_uart1>;
300 status = "okay";
301};
302
303&uart2 {
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_uart2>;
306 status = "okay";
307};
308
309&uart3 {
310 pinctrl-names = "default";
311 pinctrl-0 = <&pinctrl_uart3>;
312 status = "okay";
313};
314
315&uart4 {
316 pinctrl-names = "default";
317 pinctrl-0 = <&pinctrl_uart4>;
318 status = "okay";
319};
320
321&uart5 {
322 pinctrl-names = "default";
323 pinctrl-0 = <&pinctrl_uart5>;
324 status = "okay";
325};
326
327&usbh1 {
328 dr_mode = "host";
329 disable-over-current;
330 status = "okay";
331};
332
333&usbotg {
334 vbus-supply = <&reg_usb_otg_vbus>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_usbotg>;
337 disable-over-current;
338 dr_mode = "otg";
339 status = "okay";
340};
341
342&usdhc2 {
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_usdhc2>;
89c1a8cf
DA		 345 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
346 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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IP		 347 vmmc-supply = <&reg_3p3v>;
348 status = "okay";
349};
350
351&usdhc3 {
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_usdhc3>;
89c1a8cf
DA		 354 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
355 wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
ec55b150
IP		 356 vmmc-supply = <&reg_3p3v>;
357 status = "okay";
358};
359
360&usdhc4 {
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_usdhc4>;
363 vmmc-supply = <&reg_3p3v>;
364 non-removable;
365 status = "okay";
366};
367
368&iomuxc {
369 pinctrl-names = "default";
370
371 imx6-riotboard {
372 pinctrl_audmux: audmuxgrp {
373 fsl,pins = <
cb9456b5
IP		 374 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
375 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
376 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
377 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
ec55b150
IP		 378 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */
379 >;
380 };
381
382 pinctrl_ecspi1: ecspi1grp {
383 fsl,pins = <
384 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
385 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
386 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
387 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */
388 >;
389 };
390
391 pinctrl_ecspi2: ecspi2grp {
392 fsl,pins = <
393 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */
394 MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1
395 MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1
396 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */
397 MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1
398 >;
399 };
400
401 pinctrl_ecspi3: ecspi3grp {
402 fsl,pins = <
403 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
404 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
405 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
406 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */
407 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */
408 >;
409 };
410
411 pinctrl_enet: enetgrp {
412 fsl,pins = <
413 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
414 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
c007b3a6
UKK		 415 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
416 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
417 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
418 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
419 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
420 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
ec55b150 421 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
c007b3a6
UKK		 422 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */
423 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */
424 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */
425 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */
426 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */
ec55b150 427 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */
cb9456b5 428 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */
46311707 429 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
cb9456b5 430 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */
ec55b150
IP		 431 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
432 >;
433 };
434
435 pinctrl_i2c1: i2c1grp {
436 fsl,pins = <
437 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
438 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
439 >;
440 };
441
442 pinctrl_i2c2: i2c2grp {
443 fsl,pins = <
444 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
445 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
446 >;
447 };
448
449 pinctrl_i2c3: i2c3grp {
450 fsl,pins = <
451 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
452 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
453 >;
454 };
455
456 pinctrl_i2c4: i2c4grp {
457 fsl,pins = <
458 MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
459 MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
460 >;
461 };
462
463 pinctrl_led: ledgrp {
464 fsl,pins = <
cb9456b5
IP		 465 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */
466 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */
ec55b150
IP		 467 >;
468 };
469
470 pinctrl_pwm1: pwm1grp {
471 fsl,pins = <
472 MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1
473 >;
474 };
475
476 pinctrl_pwm2: pwm2grp {
477 fsl,pins = <
478 MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
479 >;
480 };
481
482 pinctrl_pwm3: pwm3grp {
483 fsl,pins = <
484 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
485 >;
486 };
487
488 pinctrl_pwm4: pwm4grp {
489 fsl,pins = <
490 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
491 >;
492 };
493
494 pinctrl_uart1: uart1grp {
495 fsl,pins = <
496 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
497 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
498 >;
499 };
500
501 pinctrl_uart2: uart2grp {
502 fsl,pins = <
503 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
504 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
505 >;
506 };
507
508 pinctrl_uart3: uart3grp {
509 fsl,pins = <
510 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
511 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
512 >;
513 };
514
515 pinctrl_uart4: uart4grp {
516 fsl,pins = <
517 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
518 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
519 >;
520 };
521
522 pinctrl_uart5: uart5grp {
523 fsl,pins = <
524 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
525 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
526 >;
527 };
528
529 pinctrl_usbotg: usbotggrp {
530 fsl,pins = <
531 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
cb9456b5
IP		 532 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
533 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
ec55b150
IP		 534 >;
535 };
536
537 pinctrl_usdhc2: usdhc2grp {
538 fsl,pins = <
539 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
540 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
541 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
542 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
543 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
544 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
cb9456b5
IP		 545 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */
546 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */
ec55b150
IP		 547 >;
548 };
549
550 pinctrl_usdhc3: usdhc3grp {
551 fsl,pins = <
552 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
553 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
554 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
555 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
556 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
557 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
cb9456b5
IP		 558 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */
559 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */
ec55b150
IP		 560 >;
561 };
562
563 pinctrl_usdhc4: usdhc4grp {
564 fsl,pins = <
565 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
566 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
567 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
568 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
569 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
570 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
cb9456b5 571 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */
ec55b150
IP		 572 >;
573 };
574 };
575};
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