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7c1da585 SG |
1 | |
2 | /* | |
3 | * Copyright 2013 Freescale Semiconductor, Inc. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | */ | |
10 | ||
e6117ff3 | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
e1641531 | 12 | #include "imx6q-pinfunc.h" |
c56009b2 | 13 | #include "imx6qdl.dtsi" |
7c1da585 SG |
14 | |
15 | / { | |
a26be0f0 SH |
16 | aliases { |
17 | spi4 = &ecspi5; | |
18 | }; | |
19 | ||
7c1da585 SG |
20 | cpus { |
21 | #address-cells = <1>; | |
22 | #size-cells = <0>; | |
23 | ||
24 | cpu@0 { | |
25 | compatible = "arm,cortex-a9"; | |
7925e89f | 26 | device_type = "cpu"; |
7c1da585 SG |
27 | reg = <0>; |
28 | next-level-cache = <&L2>; | |
29 | operating-points = < | |
30 | /* kHz uV */ | |
31 | 1200000 1275000 | |
32 | 996000 1250000 | |
89ef8ef4 | 33 | 852000 1250000 |
7c1da585 | 34 | 792000 1150000 |
26ea5801 | 35 | 396000 975000 |
7c1da585 | 36 | >; |
69171eda AH |
37 | fsl,soc-operating-points = < |
38 | /* ARM kHz SOC-PU uV */ | |
39 | 1200000 1275000 | |
40 | 996000 1250000 | |
89ef8ef4 | 41 | 852000 1250000 |
69171eda AH |
42 | 792000 1175000 |
43 | 396000 1175000 | |
7c1da585 SG |
44 | >; |
45 | clock-latency = <61036>; /* two CLK32 periods */ | |
8888f651 SG |
46 | clocks = <&clks IMX6QDL_CLK_ARM>, |
47 | <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, | |
48 | <&clks IMX6QDL_CLK_STEP>, | |
49 | <&clks IMX6QDL_CLK_PLL1_SW>, | |
50 | <&clks IMX6QDL_CLK_PLL1_SYS>; | |
7c1da585 SG |
51 | clock-names = "arm", "pll2_pfd2_396m", "step", |
52 | "pll1_sw", "pll1_sys"; | |
53 | arm-supply = <®_arm>; | |
54 | pu-supply = <®_pu>; | |
55 | soc-supply = <®_soc>; | |
56 | }; | |
57 | ||
58 | cpu@1 { | |
59 | compatible = "arm,cortex-a9"; | |
7925e89f | 60 | device_type = "cpu"; |
7c1da585 SG |
61 | reg = <1>; |
62 | next-level-cache = <&L2>; | |
63 | }; | |
64 | ||
65 | cpu@2 { | |
66 | compatible = "arm,cortex-a9"; | |
7925e89f | 67 | device_type = "cpu"; |
7c1da585 SG |
68 | reg = <2>; |
69 | next-level-cache = <&L2>; | |
70 | }; | |
71 | ||
72 | cpu@3 { | |
73 | compatible = "arm,cortex-a9"; | |
7925e89f | 74 | device_type = "cpu"; |
7c1da585 SG |
75 | reg = <3>; |
76 | next-level-cache = <&L2>; | |
77 | }; | |
78 | }; | |
79 | ||
80 | soc { | |
951ebf58 SG |
81 | ocram: sram@00900000 { |
82 | compatible = "mmio-sram"; | |
83 | reg = <0x00900000 0x40000>; | |
8888f651 | 84 | clocks = <&clks IMX6QDL_CLK_OCRAM>; |
951ebf58 SG |
85 | }; |
86 | ||
7c1da585 SG |
87 | aips-bus@02000000 { /* AIPS1 */ |
88 | spba-bus@02000000 { | |
89 | ecspi5: ecspi@02018000 { | |
90 | #address-cells = <1>; | |
91 | #size-cells = <0>; | |
92 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
93 | reg = <0x02018000 0x4000>; | |
e6117ff3 | 94 | interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
95 | clocks = <&clks IMX6Q_CLK_ECSPI5>, |
96 | <&clks IMX6Q_CLK_ECSPI5>; | |
7c1da585 SG |
97 | clock-names = "ipg", "per"; |
98 | status = "disabled"; | |
99 | }; | |
100 | }; | |
101 | ||
102 | iomuxc: iomuxc@020e0000 { | |
103 | compatible = "fsl,imx6q-iomuxc"; | |
b72ce929 SG |
104 | |
105 | ipu2 { | |
106 | pinctrl_ipu2_1: ipu2grp-1 { | |
107 | fsl,pins = < | |
108 | MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10 | |
109 | MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10 | |
110 | MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10 | |
111 | MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10 | |
112 | MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000 | |
113 | MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10 | |
114 | MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10 | |
115 | MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10 | |
116 | MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10 | |
117 | MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10 | |
118 | MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10 | |
119 | MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10 | |
120 | MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10 | |
121 | MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10 | |
122 | MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10 | |
123 | MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10 | |
124 | MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10 | |
125 | MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10 | |
126 | MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10 | |
127 | MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10 | |
128 | MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10 | |
129 | MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10 | |
130 | MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10 | |
131 | MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10 | |
132 | MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10 | |
133 | MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10 | |
134 | MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10 | |
135 | MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10 | |
136 | MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10 | |
137 | >; | |
138 | }; | |
139 | }; | |
7c1da585 SG |
140 | }; |
141 | }; | |
142 | ||
0fb1f804 RZ |
143 | sata: sata@02200000 { |
144 | compatible = "fsl,imx6q-ahci"; | |
145 | reg = <0x02200000 0x4000>; | |
e6117ff3 | 146 | interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
147 | clocks = <&clks IMX6QDL_CLK_SATA>, |
148 | <&clks IMX6QDL_CLK_SATA_REF_100M>, | |
149 | <&clks IMX6QDL_CLK_AHB>; | |
0fb1f804 RZ |
150 | clock-names = "sata", "sata_ref", "ahb"; |
151 | status = "disabled"; | |
152 | }; | |
153 | ||
7c1da585 | 154 | ipu2: ipu@02800000 { |
4520e692 PZ |
155 | #address-cells = <1>; |
156 | #size-cells = <0>; | |
7c1da585 SG |
157 | compatible = "fsl,imx6q-ipu"; |
158 | reg = <0x02800000 0x400000>; | |
e6117ff3 TK |
159 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, |
160 | <0 7 IRQ_TYPE_LEVEL_HIGH>; | |
8888f651 SG |
161 | clocks = <&clks IMX6QDL_CLK_IPU2>, |
162 | <&clks IMX6QDL_CLK_IPU2_DI0>, | |
163 | <&clks IMX6QDL_CLK_IPU2_DI1>; | |
7c1da585 | 164 | clock-names = "bus", "di0", "di1"; |
09ebf366 | 165 | resets = <&src 4>; |
4520e692 | 166 | |
c0470c38 PZ |
167 | ipu2_csi0: port@0 { |
168 | reg = <0>; | |
169 | }; | |
170 | ||
171 | ipu2_csi1: port@1 { | |
172 | reg = <1>; | |
173 | }; | |
174 | ||
4520e692 PZ |
175 | ipu2_di0: port@2 { |
176 | #address-cells = <1>; | |
177 | #size-cells = <0>; | |
178 | reg = <2>; | |
179 | ||
180 | ipu2_di0_disp0: endpoint@0 { | |
181 | }; | |
182 | ||
183 | ipu2_di0_hdmi: endpoint@1 { | |
184 | remote-endpoint = <&hdmi_mux_2>; | |
185 | }; | |
186 | ||
187 | ipu2_di0_mipi: endpoint@2 { | |
188 | }; | |
189 | ||
190 | ipu2_di0_lvds0: endpoint@3 { | |
191 | remote-endpoint = <&lvds0_mux_2>; | |
192 | }; | |
193 | ||
194 | ipu2_di0_lvds1: endpoint@4 { | |
195 | remote-endpoint = <&lvds1_mux_2>; | |
196 | }; | |
197 | }; | |
198 | ||
199 | ipu2_di1: port@3 { | |
200 | #address-cells = <1>; | |
201 | #size-cells = <0>; | |
202 | reg = <3>; | |
203 | ||
204 | ipu2_di1_hdmi: endpoint@1 { | |
205 | remote-endpoint = <&hdmi_mux_3>; | |
206 | }; | |
207 | ||
208 | ipu2_di1_mipi: endpoint@2 { | |
209 | }; | |
210 | ||
211 | ipu2_di1_lvds0: endpoint@3 { | |
212 | remote-endpoint = <&lvds0_mux_3>; | |
213 | }; | |
214 | ||
215 | ipu2_di1_lvds1: endpoint@4 { | |
216 | remote-endpoint = <&lvds1_mux_3>; | |
217 | }; | |
218 | }; | |
219 | }; | |
220 | }; | |
221 | ||
222 | display-subsystem { | |
223 | compatible = "fsl,imx-display-subsystem"; | |
224 | ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; | |
225 | }; | |
226 | }; | |
227 | ||
228 | &hdmi { | |
229 | compatible = "fsl,imx6q-hdmi"; | |
230 | ||
231 | port@2 { | |
232 | reg = <2>; | |
233 | ||
234 | hdmi_mux_2: endpoint { | |
235 | remote-endpoint = <&ipu2_di0_hdmi>; | |
236 | }; | |
237 | }; | |
238 | ||
239 | port@3 { | |
240 | reg = <3>; | |
241 | ||
242 | hdmi_mux_3: endpoint { | |
243 | remote-endpoint = <&ipu2_di1_hdmi>; | |
7c1da585 SG |
244 | }; |
245 | }; | |
246 | }; | |
41c04342 ST |
247 | |
248 | &ldb { | |
8888f651 SG |
249 | clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, |
250 | <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, | |
251 | <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, | |
252 | <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; | |
41c04342 ST |
253 | clock-names = "di0_pll", "di1_pll", |
254 | "di0_sel", "di1_sel", "di2_sel", "di3_sel", | |
255 | "di0", "di1"; | |
256 | ||
257 | lvds-channel@0 { | |
4520e692 PZ |
258 | port@2 { |
259 | reg = <2>; | |
260 | ||
261 | lvds0_mux_2: endpoint { | |
262 | remote-endpoint = <&ipu2_di0_lvds0>; | |
263 | }; | |
264 | }; | |
265 | ||
266 | port@3 { | |
267 | reg = <3>; | |
268 | ||
269 | lvds0_mux_3: endpoint { | |
270 | remote-endpoint = <&ipu2_di1_lvds0>; | |
271 | }; | |
272 | }; | |
41c04342 ST |
273 | }; |
274 | ||
275 | lvds-channel@1 { | |
4520e692 PZ |
276 | port@2 { |
277 | reg = <2>; | |
278 | ||
279 | lvds1_mux_2: endpoint { | |
280 | remote-endpoint = <&ipu2_di0_lvds1>; | |
281 | }; | |
282 | }; | |
283 | ||
284 | port@3 { | |
285 | reg = <3>; | |
286 | ||
287 | lvds1_mux_3: endpoint { | |
288 | remote-endpoint = <&ipu2_di1_lvds1>; | |
289 | }; | |
290 | }; | |
41c04342 ST |
291 | }; |
292 | }; | |
04cec1a2 | 293 | |
4520e692 PZ |
294 | &mipi_dsi { |
295 | port@2 { | |
296 | reg = <2>; | |
297 | ||
298 | mipi_mux_2: endpoint { | |
299 | remote-endpoint = <&ipu2_di0_mipi>; | |
300 | }; | |
301 | }; | |
302 | ||
303 | port@3 { | |
304 | reg = <3>; | |
305 | ||
306 | mipi_mux_3: endpoint { | |
307 | remote-endpoint = <&ipu2_di1_mipi>; | |
308 | }; | |
309 | }; | |
04cec1a2 | 310 | }; |