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Merge remote-tracking branch 'mkp-scsi/fixes' into fixes
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx6qdl-apalis.dtsi
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693e3ffa
PŠ		 1/*
2 * Copyright 2014-2016 Toradex AG
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
14 *
13283626 15 * This file is distributed in the hope that it will be useful,
693e3ffa
PŠ		 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
13283626 20 * Or, alternatively,
693e3ffa
PŠ		 21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
13283626 25 * restriction, including without limitation the rights to use,
693e3ffa
PŠ		 26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
13283626 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
693e3ffa
PŠ		 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
13283626 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
693e3ffa
PŠ		 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include <dt-bindings/gpio/gpio.h>
45
46/ {
47 model = "Toradex Apalis iMX6Q/D Module";
48 compatible = "toradex,apalis_imx6q", "fsl,imx6q";
49
50 backlight: backlight {
51 compatible = "pwm-backlight";
ebedca04
SM		 52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_gpio_bl_on>;
693e3ffa 54 pwms = <&pwm4 0 5000000>;
ebedca04 55 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
693e3ffa
PŠ		 56 status = "disabled";
57 };
58
59 /* DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 */
60 i2cddc: i2c@0 {
61 compatible = "i2c-gpio";
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_i2c_ddc>;
64 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH /* sda */
65 &gpio2 30 GPIO_ACTIVE_HIGH /* scl */
66 >;
67 i2c-gpio,delay-us = <2>; /* ~100 kHz */
68 status = "disabled";
69 };
70
71 reg_1p8v: regulator-1p8v {
72 compatible = "regulator-fixed";
73 regulator-name = "1P8V";
74 regulator-min-microvolt = <1800000>;
75 regulator-max-microvolt = <1800000>;
76 regulator-always-on;
77 };
78
79 reg_2p5v: regulator-2p5v {
80 compatible = "regulator-fixed";
81 regulator-name = "2P5V";
82 regulator-min-microvolt = <2500000>;
83 regulator-max-microvolt = <2500000>;
84 regulator-always-on;
85 };
86
87 reg_3p3v: regulator-3p3v {
88 compatible = "regulator-fixed";
89 regulator-name = "3P3V";
90 regulator-min-microvolt = <3300000>;
91 regulator-max-microvolt = <3300000>;
92 regulator-always-on;
93 };
94
95 reg_usb_otg_vbus: regulator-usb-otg-vbus {
96 compatible = "regulator-fixed";
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
99 regulator-name = "usb_otg_vbus";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
102 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
103 enable-active-high;
104 status = "disabled";
105 };
106
107 /* on module USB hub */
108 reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
109 compatible = "regulator-fixed";
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
112 regulator-name = "usb_host_vbus_hub";
113 regulator-min-microvolt = <5000000>;
114 regulator-max-microvolt = <5000000>;
115 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
116 startup-delay-us = <2000>;
117 enable-active-high;
118 status = "okay";
119 };
120
121 reg_usb_host_vbus: regulator-usb-host-vbus {
122 compatible = "regulator-fixed";
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
125 regulator-name = "usb_host_vbus";
126 regulator-min-microvolt = <5000000>;
127 regulator-max-microvolt = <5000000>;
128 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
129 enable-active-high;
130 vin-supply = <&reg_usb_host_vbus_hub>;
131 status = "disabled";
132 };
133
134 sound {
135 compatible = "fsl,imx-audio-sgtl5000";
136 model = "imx6q-apalis-sgtl5000";
137 ssi-controller = <&ssi1>;
138 audio-codec = <&codec>;
139 audio-routing =
140 "LINE_IN", "Line In Jack",
141 "MIC_IN", "Mic Jack",
142 "Mic Jack", "Mic Bias",
143 "Headphone Jack", "HP_OUT";
144 mux-int-port = <1>;
145 mux-ext-port = <4>;
146 };
147
148 sound_spdif: sound-spdif {
149 compatible = "fsl,imx-audio-spdif";
150 model = "imx-spdif";
151 spdif-controller = <&spdif>;
152 spdif-in;
153 spdif-out;
154 status = "disabled";
155 };
156};
157
158&audmux {
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_audmux>;
161 status = "okay";
162};
163
164&can1 {
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_flexcan1>;
167 status = "disabled";
168};
169
170&can2 {
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_flexcan2>;
173 status = "disabled";
174};
175
176/* Apalis SPI1 */
177&ecspi1 {
693e3ffa
PŠ		 178 cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_ecspi1>;
181 status = "disabled";
182};
183
184/* Apalis SPI2 */
185&ecspi2 {
693e3ffa
PŠ		 186 cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_ecspi2>;
189 status = "disabled";
190};
191
192&fec {
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_enet>;
195 phy-mode = "rgmii";
196 phy-handle = <&ethphy>;
197 phy-reset-duration = <10>;
198 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
199 status = "okay";
200
201 mdio {
202 #address-cells = <1>;
203 #size-cells = <0>;
204
205 ethphy: ethernet-phy@7 {
206 interrupt-parent = <&gpio1>;
207 interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
208 reg = <7>;
209 };
210 };
211};
212
213/*
214 * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier
215 * board)
216 */
217&i2c1 {
218 clock-frequency = <100000>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_i2c1>;
221 status = "disabled";
222};
223
224/*
225 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
226 * touch screen controller
227 */
228&i2c2 {
229 clock-frequency = <100000>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_i2c2>;
232 status = "okay";
233
234 pmic: pfuze100@08 {
235 compatible = "fsl,pfuze100";
236 reg = <0x08>;
237
238 regulators {
239 sw1a_reg: sw1ab {
240 regulator-min-microvolt = <300000>;
241 regulator-max-microvolt = <1875000>;
242 regulator-boot-on;
243 regulator-always-on;
244 regulator-ramp-delay = <6250>;
245 };
246
247 sw1c_reg: sw1c {
248 regulator-min-microvolt = <300000>;
249 regulator-max-microvolt = <1875000>;
250 regulator-boot-on;
251 regulator-always-on;
252 regulator-ramp-delay = <6250>;
253 };
254
255 sw3a_reg: sw3a {
256 regulator-min-microvolt = <400000>;
257 regulator-max-microvolt = <1975000>;
258 regulator-boot-on;
259 regulator-always-on;
260 };
261
262 swbst_reg: swbst {
263 regulator-min-microvolt = <5000000>;
264 regulator-max-microvolt = <5150000>;
265 regulator-boot-on;
266 regulator-always-on;
267 };
268
269 snvs_reg: vsnvs {
270 regulator-min-microvolt = <1000000>;
271 regulator-max-microvolt = <3000000>;
272 regulator-boot-on;
273 regulator-always-on;
274 };
275
276 vref_reg: vrefddr {
277 regulator-boot-on;
278 regulator-always-on;
279 };
280
281 vgen1_reg: vgen1 {
282 regulator-min-microvolt = <800000>;
283 regulator-max-microvolt = <1550000>;
284 regulator-boot-on;
285 regulator-always-on;
286 };
287
288 vgen2_reg: vgen2 {
289 regulator-min-microvolt = <800000>;
290 regulator-max-microvolt = <1550000>;
291 regulator-boot-on;
292 regulator-always-on;
293 };
294
295 vgen3_reg: vgen3 {
296 regulator-min-microvolt = <1800000>;
297 regulator-max-microvolt = <3300000>;
298 regulator-boot-on;
299 regulator-always-on;
300 };
301
302 vgen4_reg: vgen4 {
303 regulator-min-microvolt = <1800000>;
304 regulator-max-microvolt = <3300000>;
305 regulator-boot-on;
306 regulator-always-on;
307 };
308
309 vgen5_reg: vgen5 {
310 regulator-min-microvolt = <1800000>;
311 regulator-max-microvolt = <3300000>;
312 regulator-boot-on;
313 regulator-always-on;
314 };
315
316 vgen6_reg: vgen6 {
317 regulator-min-microvolt = <1800000>;
318 regulator-max-microvolt = <3300000>;
319 regulator-boot-on;
320 regulator-always-on;
321 };
322 };
323 };
324
325 codec: sgtl5000@0a {
326 compatible = "fsl,sgtl5000";
327 reg = <0x0a>;
b26a68c1 328 clocks = <&clks IMX6QDL_CLK_CKO>;
693e3ffa
PŠ		 329 VDDA-supply = <&reg_2p5v>;
330 VDDIO-supply = <&reg_3p3v>;
331 };
332
333 /* STMPE811 touch screen controller */
334 stmpe811@41 {
335 compatible = "st,stmpe811";
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_touch_int>;
338 #address-cells = <1>;
339 #size-cells = <0>;
340 reg = <0x41>;
341 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
342 interrupt-parent = <&gpio4>;
343 interrupt-controller;
344 id = <0>;
345 blocks = <0x5>;
346 irq-trigger = <0x1>;
347
348 stmpe_touchscreen {
349 compatible = "st,stmpe-ts";
350 reg = <0>;
351 /* 3.25 MHz ADC clock speed */
352 st,adc-freq = <1>;
353 /* 8 sample average control */
354 st,ave-ctrl = <3>;
355 /* 7 length fractional part in z */
356 st,fraction-z = <7>;
357 /*
358 * 50 mA typical 80 mA max touchscreen drivers
359 * current limit value
360 */
361 st,i-drive = <1>;
362 /* 12-bit ADC */
363 st,mod-12b = <1>;
364 /* internal ADC reference */
365 st,ref-sel = <0>;
366 /* ADC converstion time: 80 clocks */
367 st,sample-time = <4>;
368 /* 1 ms panel driver settling time */
369 st,settling = <3>;
370 /* 5 ms touch detect interrupt delay */
371 st,touch-det-delay = <5>;
372 };
373 };
374};
375
376/*
377 * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused)
378 */
379&i2c3 {
380 clock-frequency = <100000>;
381 pinctrl-names = "default", "recovery";
382 pinctrl-0 = <&pinctrl_i2c3>;
383 pinctrl-1 = <&pinctrl_i2c3_recovery>;
384 scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
385 sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
386 status = "disabled";
387};
388
389&pwm1 {
390 pinctrl-names = "default";
391 pinctrl-0 = <&pinctrl_pwm1>;
392 status = "disabled";
393};
394
395&pwm2 {
396 pinctrl-names = "default";
397 pinctrl-0 = <&pinctrl_pwm2>;
398 status = "disabled";
399};
400
401&pwm3 {
402 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_pwm3>;
404 status = "disabled";
405};
406
407&pwm4 {
408 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_pwm4>;
410 status = "disabled";
411};
412
413&spdif {
414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_spdif>;
416 status = "disabled";
417};
418
419&ssi1 {
420 status = "okay";
421};
422
423&uart1 {
424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
426 fsl,dte-mode;
2e7c416c 427 uart-has-rtscts;
693e3ffa
PŠ		 428 status = "disabled";
429};
430
431&uart2 {
432 pinctrl-names = "default";
433 pinctrl-0 = <&pinctrl_uart2_dte>;
434 fsl,dte-mode;
2e7c416c 435 uart-has-rtscts;
693e3ffa
PŠ		 436 status = "disabled";
437};
438
439&uart4 {
440 pinctrl-names = "default";
441 pinctrl-0 = <&pinctrl_uart4_dte>;
442 fsl,dte-mode;
443 status = "disabled";
444};
445
446&uart5 {
447 pinctrl-names = "default";
448 pinctrl-0 = <&pinctrl_uart5_dte>;
449 fsl,dte-mode;
450 status = "disabled";
451};
452
453&usbotg {
454 pinctrl-names = "default";
455 pinctrl-0 = <&pinctrl_usbotg>;
456 disable-over-current;
457 status = "disabled";
458};
459
460/* MMC1 */
461&usdhc1 {
462 pinctrl-names = "default";
463 pinctrl-0 = <&pinctrl_usdhc1>;
464 vqmmc-supply = <&reg_3p3v>;
465 bus-width = <8>;
466 voltage-ranges = <3300 3300>;
467 status = "disabled";
468};
469
470/* SD1 */
471&usdhc2 {
472 pinctrl-names = "default";
473 pinctrl-0 = <&pinctrl_usdhc2>;
474 vqmmc-supply = <&reg_3p3v>;
475 bus-width = <4>;
476 voltage-ranges = <3300 3300>;
477 status = "disabled";
478};
479
480/* eMMC */
481&usdhc3 {
482 pinctrl-names = "default";
483 pinctrl-0 = <&pinctrl_usdhc3>;
484 vqmmc-supply = <&reg_3p3v>;
485 bus-width = <8>;
486 voltage-ranges = <3300 3300>;
487 non-removable;
488 status = "okay";
489};
490
491&weim {
492 status = "disabled";
493};
494
495&iomuxc {
496 /* pins used on module */
497 pinctrl-names = "default";
498 pinctrl-0 = <&pinctrl_reset_moci>;
499
500 pinctrl_apalis_gpio1: gpio2io04grp {
501 fsl,pins = <
502 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
503 >;
504 };
505
506 pinctrl_apalis_gpio2: gpio2io05grp {
507 fsl,pins = <
508 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
509 >;
510 };
511
512 pinctrl_apalis_gpio3: gpio2io06grp {
513 fsl,pins = <
514 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
515 >;
516 };
517
518 pinctrl_apalis_gpio4: gpio2io07grp {
519 fsl,pins = <
520 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
521 >;
522 };
523
524 pinctrl_apalis_gpio5: gpio6io10grp {
525 fsl,pins = <
526 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
527 >;
528 };
529
530 pinctrl_apalis_gpio6: gpio6io09grp {
531 fsl,pins = <
532 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
533 >;
534 };
535
536 pinctrl_apalis_gpio7: gpio1io02grp {
537 fsl,pins = <
538 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
539 >;
540 };
541
542 pinctrl_apalis_gpio8: gpio1io06grp {
543 fsl,pins = <
544 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
545 >;
546 };
547
548 pinctrl_audmux: audmuxgrp {
549 fsl,pins = <
550 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
551 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
552 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
553 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
554 /* SGTL5000 sys_mclk */
555 MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
556 >;
557 };
558
559 pinctrl_cam_mclk: cammclkgrp {
560 fsl,pins = <
561 /* CAM sys_mclk */
562 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
563 >;
564 };
565
566 pinctrl_ecspi1: ecspi1grp {
567 fsl,pins = <
568 MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
569 MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
570 MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
571 /* SPI1 cs */
572 MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1
573 >;
574 };
575
576 pinctrl_ecspi2: ecspi2grp {
577 fsl,pins = <
578 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
579 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
580 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
581 /* SPI2 cs */
582 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
583 >;
584 };
585
586 pinctrl_enet: enetgrp {
587 fsl,pins = <
588 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
589 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
c007b3a6
UKK		 590 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
591 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
592 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
593 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
594 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
595 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
693e3ffa 596 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
c007b3a6
UKK		 597 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
598 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
599 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
600 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
601 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
602 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
693e3ffa
PŠ		 603 /* Ethernet PHY reset */
604 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
605 /* Ethernet PHY interrupt */
606 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1
607 >;
608 };
609
610 pinctrl_flexcan1: flexcan1grp {
611 fsl,pins = <
612 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
613 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
614 >;
615 };
616
617 pinctrl_flexcan2: flexcan2grp {
618 fsl,pins = <
619 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
620 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
621 >;
622 };
623
ebedca04
SM		 624 pinctrl_gpio_bl_on: gpioblon {
625 fsl,pins = <
626 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
627 >;
628 };
629
693e3ffa
PŠ		 630 pinctrl_gpio_keys: gpio1io04grp {
631 fsl,pins = <
632 /* Power button */
633 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
634 >;
635 };
636
637 pinctrl_hdmi_cec: hdmicecgrp {
638 fsl,pins = <
639 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
640 >;
641 };
642
643 pinctrl_i2c_ddc: gpioi2cddcgrp {
644 fsl,pins = <
645 /* DDC bitbang */
646 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
647 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0
648 >;
649 };
650
651 pinctrl_i2c1: i2c1grp {
652 fsl,pins = <
653 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
654 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
655 >;
656 };
657
658 pinctrl_i2c2: i2c2grp {
659 fsl,pins = <
660 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
661 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
662 >;
663 };
664
665 pinctrl_i2c3: i2c3grp {
666 fsl,pins = <
667 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
668 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
669 >;
670 };
671
672 pinctrl_i2c3_recovery: i2c3recoverygrp {
673 fsl,pins = <
674 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
675 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
676 >;
677 };
678
679 pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
680 fsl,pins = <
681 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1
682 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1
683 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1
684 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1
685 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1
686 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1
687 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1
688 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1
689 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
690 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1
691 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1
692 >;
693 };
694
695 pinctrl_ipu1_lcdif: ipu1lcdifgrp {
696 fsl,pins = <
697 MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61
698 /* DE */
699 MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61
700 /* HSync */
701 MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61
702 /* VSync */
703 MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61
704 MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61
705 MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61
706 MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61
707 MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61
708 MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61
709 MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61
710 MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61
711 MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61
712 MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61
713 MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61
714 MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61
715 MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61
716 MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61
717 MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61
718 MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61
719 MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61
720 MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61
721 MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61
722 MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61
723 MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61
724 MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61
725 MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61
726 MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61
727 MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61
728 >;
729 };
730
731 pinctrl_ipu2_vdac: ipu2vdacgrp {
732 fsl,pins = <
733 MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1
734 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1
735 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1
736 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1
737 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9
738 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9
739 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9
740 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9
741 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9
742 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9
743 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9
744 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9
745 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9
746 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9
747 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9
748 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9
749 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9
750 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9
751 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9
752 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9
753 >;
754 };
755
756 pinctrl_mmc_cd: gpiommccdgrp {
757 fsl,pins = <
758 /* MMC1 CD */
759 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
760 >;
761 };
762
763 pinctrl_pwm1: pwm1grp {
764 fsl,pins = <
765 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
766 >;
767 };
768
769 pinctrl_pwm2: pwm2grp {
770 fsl,pins = <
771 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
772 >;
773 };
774
775 pinctrl_pwm3: pwm3grp {
776 fsl,pins = <
777 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
778 >;
779 };
780
781 pinctrl_pwm4: pwm4grp {
782 fsl,pins = <
783 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
784 >;
785 };
786
787 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
788 fsl,pins = <
789 /* USBH_EN */
790 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
791 >;
792 };
793
794 pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
795 fsl,pins = <
796 /* USBH_HUB_EN */
797 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
798 >;
799 };
800
801 pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
802 fsl,pins = <
803 /* USBO1 power en */
804 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
805 >;
806 };
807
808 pinctrl_reset_moci: gpioresetmocigrp {
809 fsl,pins = <
810 /* RESET_MOCI control */
811 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
812 >;
813 };
814
815 pinctrl_sd_cd: gpiosdcdgrp {
816 fsl,pins = <
817 /* SD1 CD */
818 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
819 >;
820 };
821
822 pinctrl_spdif: spdifgrp {
823 fsl,pins = <
824 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
825 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
826 >;
827 };
828
829 pinctrl_touch_int: gpiotouchintgrp {
830 fsl,pins = <
831 /* STMPE811 interrupt */
832 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
833 >;
834 };
835
836 pinctrl_uart1_dce: uart1dcegrp {
837 fsl,pins = <
838 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
839 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
840 >;
841 };
842
843 /* DTE mode */
844 pinctrl_uart1_dte: uart1dtegrp {
845 fsl,pins = <
846 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
847 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
848 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
849 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
850 >;
851 };
852
853 /* Additional DTR, DSR, DCD */
854 pinctrl_uart1_ctrl: uart1ctrlgrp {
855 fsl,pins = <
856 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
857 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
858 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
859 >;
860 };
861
862 pinctrl_uart2_dce: uart2dcegrp {
863 fsl,pins = <
864 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
865 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
866 >;
867 };
868
869 /* DTE mode */
870 pinctrl_uart2_dte: uart2dtegrp {
871 fsl,pins = <
872 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
873 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
874 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
875 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
876 >;
877 };
878
879 pinctrl_uart4_dce: uart4dcegrp {
880 fsl,pins = <
881 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
882 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
883 >;
884 };
885
886 /* DTE mode */
887 pinctrl_uart4_dte: uart4dtegrp {
888 fsl,pins = <
889 MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
890 MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
891 >;
892 };
893
894 pinctrl_uart5_dce: uart5dcegrp {
895 fsl,pins = <
896 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
897 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
898 >;
899 };
900
901 /* DTE mode */
902 pinctrl_uart5_dte: uart5dtegrp {
903 fsl,pins = <
904 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
905 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
906 >;
907 };
908
909 pinctrl_usbotg: usbotggrp {
910 fsl,pins = <
911 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
912 >;
913 };
914
915 pinctrl_usdhc1: usdhc1grp {
916 fsl,pins = <
917 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
918 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
919 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
920 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
921 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
922 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
923 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
924 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
925 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
926 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
927 >;
928 };
929
930 pinctrl_usdhc2: usdhc2grp {
931 fsl,pins = <
932 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071
933 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
934 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
935 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
936 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
937 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
938 >;
939 };
940
941 pinctrl_usdhc3: usdhc3grp {
942 fsl,pins = <
943 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
944 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
945 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
946 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
947 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
948 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
949 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
950 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
951 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
952 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
953 /* eMMC reset */
954 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
955 >;
956 };
957
958 pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
959 fsl,pins = <
960 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
961 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
962 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
963 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
964 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
965 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
966 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
967 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
968 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
969 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
970 /* eMMC reset */
971 MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9
972 >;
973 };
974
975 pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
976 fsl,pins = <
977 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
978 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
979 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
980 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
981 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
982 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
983 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
984 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
985 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
986 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
987 /* eMMC reset */
988 MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9
989 >;
990 };
991};
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