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Merge tag 'topic/designware-baytrail-2017-03-02' of git://anongit.freedesktop.org...
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx6qdl-aristainetos.dtsi
CommitLineData
c64b874f
HS		 1/*
2 * support fot the imx6 based aristainetos board
3 *
4 * Copyright (C) 2014 Heiko Schocher <hs@denx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15 regulators {
16 compatible = "simple-bus";
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 reg_2p5v: regulator@0 {
21 compatible = "regulator-fixed";
22 regulator-name = "2P5V";
23 regulator-min-microvolt = <2500000>;
24 regulator-max-microvolt = <2500000>;
25 regulator-always-on;
26 };
27
28 reg_3p3v: regulator@1 {
29 compatible = "regulator-fixed";
30 regulator-name = "3P3V";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
33 regulator-always-on;
34 };
35
36 reg_usbh1_vbus: regulator@2 {
37 compatible = "regulator-fixed";
38 enable-active-high;
39 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_aristainetos_usbh1_vbus>;
42 regulator-name = "usb_h1_vbus";
43 regulator-min-microvolt = <5000000>;
44 regulator-max-microvolt = <5000000>;
45 };
46
47 reg_usbotg_vbus: regulator@3 {
48 compatible = "regulator-fixed";
49 enable-active-high;
50 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
51 pinctrl-names = "default";
52 pinctrl-0 = <&pinctrl_aristainetos_usbotg_vbus>;
53 regulator-name = "usb_otg_vbus";
54 regulator-min-microvolt = <5000000>;
55 regulator-max-microvolt = <5000000>;
56 };
57 };
58};
59
60&audmux {
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_audmux>;
63 status = "okay";
64};
65
66&can1 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_flexcan1>;
69 status = "okay";
70};
71
72&can2 {
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_flexcan2>;
75 status = "okay";
76};
77
78&i2c1 {
79 clock-frequency = <100000>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_i2c1>;
82 status = "okay";
83
84 tmp103: tmp103@71 {
85 compatible = "ti,tmp103";
86 reg = <0x71>;
87 };
88};
89
90&i2c3 {
91 clock-frequency = <100000>;
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_i2c3>;
94 status = "okay";
95
96 rtc@68 {
97 compatible = "dallas,m41t00";
98 reg = <0x68>;
99 };
100};
101
102&ecspi4 {
c64b874f
HS		 103 cs-gpios = <&gpio3 20 0>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_ecspi4>;
106 status = "okay";
107
108 flash: m25p80@0 {
109 #address-cells = <1>;
110 #size-cells = <1>;
79826ac6 111 compatible = "micron,n25q128a11", "jedec,spi-nor";
c64b874f
HS		 112 spi-max-frequency = <20000000>;
113 reg = <0>;
114 };
115};
116
117&fec {
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_enet>;
120 phy-mode = "rmii";
121 phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
122 status = "okay";
123};
124
125&gpmi {
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_gpmi_nand>;
128 status = "okay";
129};
130
131&pcie {
132 status = "okay";
133};
134
135&uart2 {
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_uart2>;
138 status = "okay";
139};
140
141
142&uart4 {
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_uart4>;
2e7c416c 145 uart-has-rtscts;
c64b874f
HS		 146 status = "okay";
147};
148
149&uart5 {
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_uart5>;
2e7c416c 152 uart-has-rtscts;
c64b874f
HS		 153 status = "okay";
154};
155
156&usbh1 {
157 vbus-supply = <&reg_usbh1_vbus>;
158 dr_mode = "host";
159 status = "okay";
160};
161
162&usbotg {
163 vbus-supply = <&reg_usbotg_vbus>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_usbotg>;
166 disable-over-current;
167 dr_mode = "host";
168 status = "okay";
169};
170
171&usdhc1 {
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_usdhc1>;
174 vmmc-supply = <&reg_3p3v>;
89c1a8cf 175 cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
c64b874f
HS		 176 status = "okay";
177};
178
179&usdhc2 {
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_usdhc2>;
182 vmmc-supply = <&reg_3p3v>;
89c1a8cf 183 cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
c64b874f
HS		 184 status = "okay";
185};
186
187&iomuxc {
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_hog &pinctrl_gpio>;
190
191 imx6qdl-aristainetos {
192 pinctrl_aristainetos_usbh1_vbus: aristainetos-usbh1-vbus {
193 fsl,pins = <MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0>;
194 };
195
196 pinctrl_aristainetos_usbotg_vbus: aristainetos-usbotg-vbus {
197 fsl,pins = <MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0>;
198 };
199
200 pinctrl_audmux: audmuxgrp {
201 fsl,pins = <
202 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
203 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
204 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
205 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
206 >;
207 };
208
209 pinctrl_backlight: backlightgrp {
210 fsl,pins = <
211 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0
212 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0
213 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
214 >;
215 };
216
217 pinctrl_ecspi2: ecspi2grp {
218 fsl,pins = <
219 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
220 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
221 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
222 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x100b1
223 >;
224 };
225
226 pinctrl_ecspi4: ecspi4grp {
227 fsl,pins = <
228 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
229 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
230 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
231 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b1
232 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */
233 >;
234 };
235
236 pinctrl_enet: enetgrp {
237 fsl,pins = <
238 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
239 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
240 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
241 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
242 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
243 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
244 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
245 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
246 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
247 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
248 >;
249 };
250
251 pinctrl_flexcan1: flexcan1grp {
252 fsl,pins = <
253 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
254 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
255 >;
256 };
257
258 pinctrl_flexcan2: flexcan2grp {
259 fsl,pins = <
260 MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
261 MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
262 >;
263 };
264
265 pinctrl_gpio: gpiogrp {
266 fsl,pins = <
267 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
268 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
269 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
270 MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0
271 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0
272 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
273 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
274 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
275 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
276 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
277 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
278 >;
279 };
280
281 pinctrl_gpmi_nand: gpminandgrp {
282 fsl,pins = <
283 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
284 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
285 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
286 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
287 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
288 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
289 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
290 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
291 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
292 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
293 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
294 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
295 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
296 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
297 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
298 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
299 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
300 >;
301 };
302
303 pinctrl_hog: hoggrp {
304 fsl,pins = <
305 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x10
306 >;
307 };
308
309 pinctrl_i2c1: i2c1grp {
310 fsl,pins = <
311 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
312 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
313 >;
314 };
315
316 pinctrl_i2c2: i2c2grp {
317 fsl,pins = <
318 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
319 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
320 >;
321 };
322
323 pinctrl_i2c3: i2c3grp {
324 fsl,pins = <
325 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
326 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
327 >;
328 };
329
330 pinctrl_ipu_disp: ipudisp1grp {
331 fsl,pins = <
332 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
333 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
334 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
335 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
336 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x20000
337 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
338 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
339 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
340 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
341 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
342 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
343 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
344 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
345 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
346 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
347 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
348 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
349 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
350 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
351 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
352 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
353 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
354 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
355 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
356 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
357 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
358 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
359 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
360 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
361 >;
362 };
363
364 pinctrl_uart2: uart2grp {
365 fsl,pins = <
366 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
367 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
368 >;
369 };
370
371 pinctrl_uart4: uart4grp {
372 fsl,pins = <
373 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
374 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
375 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
376 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
377 >;
378 };
379
380 pinctrl_uart5: uart5grp {
381 fsl,pins = <
382 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
383 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
384 >;
385 };
386
387 pinctrl_usbotg: usbotggrp {
388 fsl,pins = <
389 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
390 >;
391 };
392
393 pinctrl_usdhc1: usdhc1grp {
394 fsl,pins = <
395 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
396 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
397 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
398 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
399 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
400 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
401 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
402 >;
403 };
404
405 pinctrl_usdhc2: usdhc2grp {
406 fsl,pins = <
407 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
408 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
409 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
410 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
411 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
412 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
413 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0
414 >;
415 };
416 };
417};
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