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ARM: dts: imx6qdl-apalis/-colibri: fix on-module regulators
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx6qdl-colibri.dtsi
CommitLineData
fc48e764
SM		 1/*
2 * Copyright 2014-2016 Toradex AG
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
14 *
13283626 15 * This file is distributed in the hope that it will be useful,
fc48e764
SM		 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
13283626 20 * Or, alternatively,
fc48e764
SM		 21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
13283626 25 * restriction, including without limitation the rights to use,
fc48e764
SM		 26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
13283626 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
fc48e764
SM		 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
13283626 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
fc48e764
SM		 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include <dt-bindings/gpio/gpio.h>
45
46/ {
47 model = "Toradex Colibri iMX6DL/S Module";
48 compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
49
50 backlight: backlight {
51 compatible = "pwm-backlight";
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_gpio_bl_on>;
54 pwms = <&pwm3 0 5000000>;
55 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
56 status = "disabled";
57 };
58
7060066d 59 reg_module_3v3: regulator-module-3v3 {
fc48e764 60 compatible = "regulator-fixed";
7060066d
SA		 61 regulator-name = "+V3.3";
62 regulator-min-microvolt = <3300000>;
63 regulator-max-microvolt = <3300000>;
fc48e764
SM		 64 regulator-always-on;
65 };
66
7060066d 67 reg_module_3v3_audio: regulator-module-3v3-audio {
fc48e764 68 compatible = "regulator-fixed";
7060066d 69 regulator-name = "+V3.3_AUDIO";
fc48e764
SM		 70 regulator-min-microvolt = <3300000>;
71 regulator-max-microvolt = <3300000>;
72 regulator-always-on;
73 };
74
75 reg_usb_host_vbus: regulator-usb-host-vbus {
76 compatible = "regulator-fixed";
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
79 regulator-name = "usb_host_vbus";
80 regulator-min-microvolt = <5000000>;
81 regulator-max-microvolt = <5000000>;
82 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
83 status = "disabled";
84 };
85
86 sound {
87 compatible = "fsl,imx-audio-sgtl5000";
88 model = "imx6dl-colibri-sgtl5000";
89 ssi-controller = <&ssi1>;
90 audio-codec = <&codec>;
91 audio-routing =
92 "Headphone Jack", "HP_OUT",
93 "LINE_IN", "Line In Jack",
94 "MIC_IN", "Mic Jack",
95 "Mic Jack", "Mic Bias";
96 mux-int-port = <1>;
97 mux-ext-port = <5>;
98 };
99
100 /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
101 sound_spdif: sound-spdif {
102 compatible = "fsl,imx-audio-spdif";
103 model = "imx-spdif";
104 spdif-controller = <&spdif>;
105 spdif-in;
106 spdif-out;
107 status = "disabled";
108 };
109};
110
111&audmux {
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
114 status = "okay";
115};
116
117/* Optional on SODIMM 55/63 */
118&can1 {
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_flexcan1>;
121 status = "disabled";
122};
123
124/* Optional on SODIMM 178/188 */
125&can2 {
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_flexcan2>;
128 status = "disabled";
129};
130
131/* Colibri SSP */
132&ecspi4 {
fc48e764
SM		 133 cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_ecspi4>;
136 status = "disabled";
137};
138
139&fec {
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_enet>;
142 phy-mode = "rmii";
143 status = "okay";
144};
145
146&hdmi {
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_hdmi_ddc>;
149 status = "disabled";
150};
151
152/*
153 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
154 * touch screen controller
155 */
156&i2c2 {
157 clock-frequency = <100000>;
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_i2c2>;
160 status = "okay";
161
8dccafaa 162 pmic: pfuze100@8 {
fc48e764
SM		 163 compatible = "fsl,pfuze100";
164 reg = <0x08>;
165
166 regulators {
167 sw1a_reg: sw1ab {
168 regulator-min-microvolt = <300000>;
169 regulator-max-microvolt = <1875000>;
170 regulator-boot-on;
171 regulator-always-on;
172 regulator-ramp-delay = <6250>;
173 };
174
175 sw1c_reg: sw1c {
176 regulator-min-microvolt = <300000>;
177 regulator-max-microvolt = <1875000>;
178 regulator-boot-on;
179 regulator-always-on;
180 regulator-ramp-delay = <6250>;
181 };
182
183 sw3a_reg: sw3a {
184 regulator-min-microvolt = <400000>;
185 regulator-max-microvolt = <1975000>;
186 regulator-boot-on;
187 regulator-always-on;
188 };
189
190 swbst_reg: swbst {
191 regulator-min-microvolt = <5000000>;
192 regulator-max-microvolt = <5150000>;
193 regulator-boot-on;
194 regulator-always-on;
195 };
196
197 snvs_reg: vsnvs {
198 regulator-min-microvolt = <1000000>;
199 regulator-max-microvolt = <3000000>;
200 regulator-boot-on;
201 regulator-always-on;
202 };
203
204 vref_reg: vrefddr {
205 regulator-boot-on;
206 regulator-always-on;
207 };
208
209 /* vgen1: unused */
210
211 vgen2_reg: vgen2 {
212 regulator-min-microvolt = <800000>;
213 regulator-max-microvolt = <1550000>;
214 regulator-boot-on;
215 regulator-always-on;
216 };
217
218 /* vgen3: unused */
219
220 vgen4_reg: vgen4 {
221 regulator-min-microvolt = <1800000>;
222 regulator-max-microvolt = <3300000>;
223 regulator-boot-on;
224 regulator-always-on;
225 };
226
227 vgen5_reg: vgen5 {
228 regulator-min-microvolt = <1800000>;
229 regulator-max-microvolt = <3300000>;
230 regulator-boot-on;
231 regulator-always-on;
232 };
233
234 vgen6_reg: vgen6 {
235 regulator-min-microvolt = <1800000>;
236 regulator-max-microvolt = <3300000>;
237 regulator-boot-on;
238 regulator-always-on;
239 };
240 };
241 };
242
8dccafaa 243 codec: sgtl5000@a {
fc48e764
SM		 244 compatible = "fsl,sgtl5000";
245 reg = <0x0a>;
246 clocks = <&clks IMX6QDL_CLK_CKO>;
7060066d
SA		 247 VDDA-supply = <&reg_module_3v3_audio>;
248 VDDIO-supply = <&reg_module_3v3>;
7d098b91 249 lrclk-strength = <3>;
fc48e764
SM		 250 };
251
252 /* STMPE811 touch screen controller */
253 stmpe811@41 {
254 compatible = "st,stmpe811";
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_touch_int>;
fc48e764
SM		 257 reg = <0x41>;
258 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
259 interrupt-parent = <&gpio6>;
260 interrupt-controller;
261 id = <0>;
262 blocks = <0x5>;
263 irq-trigger = <0x1>;
264
265 stmpe_touchscreen {
266 compatible = "st,stmpe-ts";
fc48e764
SM		 267 /* 3.25 MHz ADC clock speed */
268 st,adc-freq = <1>;
269 /* 8 sample average control */
270 st,ave-ctrl = <3>;
271 /* 7 length fractional part in z */
272 st,fraction-z = <7>;
273 /*
274 * 50 mA typical 80 mA max touchscreen drivers
275 * current limit value
276 */
277 st,i-drive = <1>;
278 /* 12-bit ADC */
279 st,mod-12b = <1>;
280 /* internal ADC reference */
281 st,ref-sel = <0>;
282 /* ADC converstion time: 80 clocks */
283 st,sample-time = <4>;
284 /* 1 ms panel driver settling time */
285 st,settling = <3>;
286 /* 5 ms touch detect interrupt delay */
287 st,touch-det-delay = <5>;
288 };
289 };
290};
291
292/*
293 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
294 */
295&i2c3 {
296 clock-frequency = <100000>;
297 pinctrl-names = "default", "recovery";
298 pinctrl-0 = <&pinctrl_i2c3>;
299 pinctrl-1 = <&pinctrl_i2c3_recovery>;
300 scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
301 sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
302 status = "disabled";
303};
304
305/* Colibri PWM<B> */
306&pwm1 {
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_pwm1>;
309 status = "disabled";
310};
311
312/* Colibri PWM<D> */
313&pwm2 {
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_pwm2>;
316 status = "disabled";
317};
318
319/* Colibri PWM<A> */
320&pwm3 {
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_pwm3>;
323 status = "disabled";
324};
325
326/* Colibri PWM<C> */
327&pwm4 {
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_pwm4>;
330 status = "disabled";
331};
332
333/* Optional S/PDIF out on SODIMM 137 */
334&spdif {
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_spdif>;
337 status = "disabled";
338};
339
340&ssi1 {
341 status = "okay";
342};
343
344/* Colibri UART_A */
345&uart1 {
346 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
348 fsl,dte-mode;
349 uart-has-rtscts;
350 status = "disabled";
351};
352
353/* Colibri UART_B */
354&uart2 {
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_uart2_dte>;
357 fsl,dte-mode;
358 uart-has-rtscts;
359 status = "disabled";
360};
361
362/* Colibri UART_C */
363&uart3 {
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_uart3_dte>;
366 fsl,dte-mode;
367 status = "disabled";
368};
369
370&usbotg {
371 pinctrl-names = "default";
372 disable-over-current;
373 dr_mode = "peripheral";
374 status = "disabled";
375};
376
377/* Colibri MMC */
378&usdhc1 {
379 pinctrl-names = "default";
c7682243
SA		 380 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
381 cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
147299a8 382 disable-wp;
7060066d 383 vqmmc-supply = <&reg_module_3v3>;
fc48e764 384 bus-width = <4>;
3b1147a9 385 no-1-8-v;
fc48e764
SM		 386 status = "disabled";
387};
388
389/* eMMC */
390&usdhc3 {
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_usdhc3>;
7060066d 393 vqmmc-supply = <&reg_module_3v3>;
fc48e764 394 bus-width = <8>;
3b1147a9 395 no-1-8-v;
fc48e764
SM		 396 non-removable;
397 status = "okay";
398};
399
400&weim {
401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0
403 &pinctrl_weim_cs1 &pinctrl_weim_cs2
404 &pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
405 #address-cells = <2>;
406 #size-cells = <1>;
407 status = "disabled";
408};
409
410&iomuxc {
411 pinctrl_audmux: audmuxgrp {
412 fsl,pins = <
413 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
414 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
415 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
416 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
417 /* SGTL5000 sys_mclk */
418 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
419 >;
420 };
421
422 pinctrl_cam_mclk: cammclkgrp {
423 fsl,pins = <
424 /* Parallel Camera CAM sys_mclk */
425 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
426 >;
427 };
428
429 pinctrl_ecspi4: ecspi4grp {
430 fsl,pins = <
431 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
432 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
433 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
434 /* SPI CS */
435 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
436 >;
437 };
438
439 pinctrl_enet: enetgrp {
440 fsl,pins = <
441 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
442 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
443 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
444 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
445 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
446 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
447 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
448 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
449 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
450 MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
451 >;
452 };
453
454 pinctrl_flexcan1: flexcan1grp {
455 fsl,pins = <
456 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
457 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
458 >;
459 };
460
461 pinctrl_flexcan2: flexcan2grp {
462 fsl,pins = <
463 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
464 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
465 >;
466 };
467
468 pinctrl_gpio_bl_on: gpioblon {
469 fsl,pins = <
470 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0
471 >;
472 };
473
474 pinctrl_gpio_keys: gpiokeys {
475 fsl,pins = <
c4288946 476 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
fc48e764
SM		 477 >;
478 };
479
480 pinctrl_hdmi_ddc: hdmiddcgrp {
481 fsl,pins = <
482 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
483 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
484 >;
485 };
486
487 pinctrl_i2c2: i2c2grp {
488 fsl,pins = <
489 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
490 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
491 >;
492 };
493
494 pinctrl_i2c3: i2c3grp {
495 fsl,pins = <
496 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
497 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
498 >;
499 };
500
501 pinctrl_i2c3_recovery: i2c3recoverygrp {
502 fsl,pins = <
503 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
504 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
505 >;
506 };
507
508 pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
509 fsl,pins = <
510 MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1
511 MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1
512 MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1
513 MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1
514 MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1
515 MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1
516 MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1
517 MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1
518 MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1
519 MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1
520 MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1
521 /* Disable PWM pins on camera interface */
522 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
523 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40
524 >;
525 };
526
527 pinctrl_ipu1_lcdif: ipu1lcdifgrp {
528 fsl,pins = <
529 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1
530 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1
531 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1
532 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1
533 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1
534 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1
535 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1
536 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1
537 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1
538 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1
539 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1
540 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1
541 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1
542 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1
543 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1
544 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1
545 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1
546 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1
547 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1
548 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1
549 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1
550 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1
551 >;
552 };
553
554 pinctrl_mic_gnd: gpiomicgnd {
555 fsl,pins = <
556 /* Controls Mic GND, PU or '1' pull Mic GND to GND */
557 MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
558 >;
559 };
560
561 pinctrl_mmc_cd: gpiommccd {
562 fsl,pins = <
10d11dad 563 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1
fc48e764
SM		 564 >;
565 };
566
567 pinctrl_pwm1: pwm1grp {
568 fsl,pins = <
569 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
570 >;
571 };
572
573 pinctrl_pwm2: pwm2grp {
574 fsl,pins = <
575 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
576 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040
577 >;
578 };
579
580 pinctrl_pwm3: pwm3grp {
581 fsl,pins = <
582 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
583 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040
584 >;
585 };
586
587 pinctrl_pwm4: pwm4grp {
588 fsl,pins = <
589 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
590 >;
591 };
592
593 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
594 fsl,pins = <
595 /* USBH_EN */
596 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058
597 >;
598 };
599
600 pinctrl_spdif: spdifgrp {
601 fsl,pins = <
602 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
603 >;
604 };
605
606 pinctrl_touch_int: gpiotouchintgrp {
607 fsl,pins = <
608 /* STMPE811 interrupt */
609 MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
610 >;
611 };
612
613 pinctrl_uart1_dce: uart1dcegrp {
614 fsl,pins = <
615 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
616 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
617 >;
618 };
619
620 /* DTE mode */
621 pinctrl_uart1_dte: uart1dtegrp {
622 fsl,pins = <
623 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
624 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
625 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
626 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
627 >;
628 };
629
630 /* Additional DTR, DSR, DCD */
631 pinctrl_uart1_ctrl: uart1ctrlgrp {
632 fsl,pins = <
633 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
634 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
635 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
636 >;
637 };
638
639 pinctrl_uart2_dte: uart2dtegrp {
640 fsl,pins = <
641 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
642 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
643 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
644 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
645 >;
646 };
647
648 pinctrl_uart3_dte: uart3dtegrp {
649 fsl,pins = <
650 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
651 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
652 >;
653 };
654
655 pinctrl_usbc_det: usbcdetgrp {
656 fsl,pins = <
657 /* USBC_DET */
658 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
659 /* USBC_DET_EN */
660 MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
661 /* USBC_DET_OVERWRITE */
662 MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058
663 >;
664 };
665
666 pinctrl_usdhc1: usdhc1grp {
667 fsl,pins = <
668 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
669 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
670 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
671 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
672 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
673 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
674 >;
675 };
676
677 pinctrl_usdhc3: usdhc3grp {
678 fsl,pins = <
679 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
680 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
681 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
682 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
683 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
684 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
685 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
686 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
687 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
688 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
689 /* eMMC reset */
690 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
691 >;
692 };
693
694 pinctrl_usdhc3_100mhz: usdhc3100mhzgrp {
695 fsl,pins = <
696 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
697 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
698 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
699 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
700 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
701 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
702 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
703 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
704 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
705 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
706 /* eMMC reset */
707 MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9
708 >;
709 };
710
711 pinctrl_usdhc3_200mhz: usdhc3200mhzgrp {
712 fsl,pins = <
713 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
714 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
715 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
716 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
717 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
718 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
719 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
720 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
721 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
722 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
723 /* eMMC reset */
724 MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9
725 >;
726 };
727
728 pinctrl_weim_cs0: weimcs0grp {
729 fsl,pins = <
730 /* nEXT_CS0 */
731 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
732 >;
733 };
734
735 pinctrl_weim_cs1: weimcs1grp {
736 fsl,pins = <
737 /* nEXT_CS1 */
738 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
739 >;
740 };
741
742 pinctrl_weim_cs2: weimcs2grp {
743 fsl,pins = <
744 /* nEXT_CS2 */
745 MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1
746 >;
747 };
748
749 pinctrl_weim_sram: weimsramgrp {
750 fsl,pins = <
751 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
752 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
753 /* Data */
754 MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
755 MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
756 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
757 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
758 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
759 MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
760 MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
761 MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
762 MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
763 MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
764 MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
765 MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
766 MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
767 MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
768 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
769 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
770 /* Address */
771 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
772 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
773 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
774 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
775 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
776 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
777 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
778 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
779 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
780 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
781 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
782 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
783 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
784 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
785 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
786 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
787 >;
788 };
789
790 pinctrl_weim_rdnwr: weimrdnwr {
791 fsl,pins = <
792 MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
793 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
794 >;
795 };
796
797 pinctrl_weim_npwe: weimnpwe {
798 fsl,pins = <
799 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
800 MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
801 >;
802 };
803
804 /* ADDRESS[16:18] [25] used as GPIO */
805 pinctrl_weim_gpio_1: weimgpio-1 {
806 fsl,pins = <
807 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
808 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
809 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
810 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
811 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
812 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
813 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
814 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
815 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
816 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
817 >;
818 };
819
820 /* ADDRESS[19:24] used as GPIO */
821 pinctrl_weim_gpio_2: weimgpio-2 {
822 fsl,pins = <
823 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
824 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
825 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
826 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
827 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
828 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
829 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
830 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
831 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
832 >;
833 };
834
835 /* DATA[16:31] used as GPIO */
836 pinctrl_weim_gpio_3: weimgpio-3 {
837 fsl,pins = <
838 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
839 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
840 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
841 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
842 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
843 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
844 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
845 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
846 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
847 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
848 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
849 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
850 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
851 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
852 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
853 >;
854 };
855
856 /* DQM[0:3] used as GPIO */
857 pinctrl_weim_gpio_4: weimgpio-4 {
858 fsl,pins = <
859 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
860 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
861 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
862 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
863 >;
864 };
865
866 /* RDY used as GPIO */
867 pinctrl_weim_gpio_5: weimgpio-5 {
868 fsl,pins = <
869 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
870 >;
871 };
872
873 /* ADDRESS[16] DATA[30] used as GPIO */
874 pinctrl_weim_gpio_6: weimgpio-6 {
875 fsl,pins = <
876 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
877 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
878 >;
879 };
880};
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