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Merge tag 'mips_fixes_5.1_1' into mips-next
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx6qdl-emcon.dtsi
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63e71fed
JT		 1// SPDX-License-Identifier: (GPL-2.0 or MIT)
2//
3// Copyright (C) 2018 emtrion GmbH
4//
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/pwm/pwm.h>
8#include <dt-bindings/input/input.h>
9
10/ {
11
12 model = "emtrion SoM emCON-MX6";
13 compatible = "emtrion,emcon-mx6";
14
15 aliases {
16 mmc0 = &usdhc3;
17 mmc1 = &usdhc2;
18 mmc2 = &usdhc1;
19 rtc0 = &ds1307;
20 };
21
22 chosen {
23 stdout-path = &uart1;
24 };
25
26 memory@10000000 {
404c0c93 27 device_type = "memory";
63e71fed
JT		 28 reg = <0x10000000 0x40000000>;
29 };
30
31 gpio-keys {
32 compatible = "gpio-keys";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_emcon_wake>;
35
36 wake {
37 label = "Wake";
38 linux,code = <KEY_WAKEUP>;
39 gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
40 wakeup-source;
41 };
42 };
43
44 som_leds: leds {
45 compatible = "gpio-leds";
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_som_leds>;
48
49 green {
50 label = "som:green";
51 gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
52 linux,default-trigger = "heartbeat";
53 default-state = "on";
54 };
55
56 red {
57 label = "som:red";
58 gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;
59 default-state = "keep";
60 };
61
62 };
63
64 lvds_backlight: lvds-backlight {
65 compatible = "pwm-backlight";
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_lvds_bl>;
68 enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
69 pwms = <&pwm1 0 50000>;
70 brightness-levels = <
71 0 4 8 16 32 64 80 96 112
72 128 144 160 176 250
73 >;
74 default-brightness-level = <13>;
75 status = "okay";
76 };
77
78 pwm_fan: pwm-fan {
79 compatible = "pwm-fan";
80 cooling-min-state = <0>;
81 cooling-max-state = <4>;
82 #cooling-cells = <2>;
83 pwms = <&pwm4 0 50000>;
84 cooling-levels = <0 64 127 191 255>;
85 status = "disabled";
86 };
87
88
89 rgb_encoder: display {
90 compatible = "fsl,imx-parallel-display";
91 #address-cells = <1>;
92 #size-cells = <0>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_rgb24_display>;
95 status = "disabled";
96
97 port@0 {
98 reg = <0>;
99
100 rgb_encoder_in: endpoint {
101 remote-endpoint = <&ipu1_di0_disp0>;
102 };
103 };
104
105 port@1 {
106 reg = <1>;
107
108 rgb_encoder_out: endpoint {
109 remote-endpoint = <&rgb_panel_in>;
110 };
111 };
112 };
113
114 rgb_panel: lcd {
115 backlight = <&rgb_backlight>;
116 power-supply = <&reg_parallel_disp>;
117
118 port {
119 rgb_panel_in: endpoint {
120 remote-endpoint = <&rgb_encoder_out>;
121 };
122 };
123 };
124
125 reg_parallel_disp: reg-parallel-display {
126 compatible = "regulator-fixed";
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_rgb_bl_en>;
129 regulator-name = "LCD-Supply";
130 regulator-min-microvolt = <5000000>;
131 regulator-max-microvolt = <5000000>;
132 gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>;
133 enable-active-high;
134 };
135
136 reg_lvds_disp: reg-lvds-display {
137 compatible = "regulator-fixed";
138 regulator-name = "LVDS-Supply";
139 regulator-min-microvolt = <5000000>;
140 regulator-max-microvolt = <5000000>;
141 gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>;
142 enable-active-high;
143 };
144
145 rgb_backlight: rgb-backlight {
146 compatible = "pwm-backlight";
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_rgb_bl>;
149 enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
150 pwms = <&pwm3 0 5000000>;
151 brightness-levels = <
152 250 176 160 144 128 112
153 96 80 64 48 32 16 8 1
154 >;
155 default-brightness-level = <13>;
156 status = "okay";
157 };
158};
159
160&can1 {
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_can1>;
163};
164
165&can2 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_can2>;
168};
169
170&ecspi2 {
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_ecspi2>;
173 cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>,
174 <&gpio2 27 GPIO_ACTIVE_HIGH>;
175};
176
177&ecspi4 {
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_nor_flash>;
180};
181
182&fec {
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_enet>;
185 phy-mode = "rgmii";
186 phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
187 phy-reset-duration = <50>;
188 phy-supply = <&vdd_1V8_reg>;
189 phy-handle = <&ksz9031>;
190 status = "okay";
191
192 mdio {
193 #address-cells = <1>;
194 #size-cells = <0>;
195
196 ksz9031: phy@0 {
197 compatible = "ethernet-phy-ieee802.3-c22";
198 reg = <0>;
199 interrupt-parent = <&gpio1>;
200 interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
201 rxdv-skew-ps = <480>;
202 txen-skew-ps = <480>;
203 rxd0-skew-ps = <480>;
204 rxd1-skew-ps = <480>;
205 rxd2-skew-ps = <480>;
206 rxd3-skew-ps = <480>;
207 txd0-skew-ps = <420>;
208 txd1-skew-ps = <420>;
209 txd2-skew-ps = <360>;
210 txd3-skew-ps = <360>;
211 txc-skew-ps = <1020>;
212 rxc-skew-ps = <960>;
213 };
214 };
215};
216
217&i2c1 {
218 clock-frequency = <100000>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_i2c1>;
221 status = "okay";
222
223 da9063: pmic@58 {
224 compatible = "dlg,da9063";
225 reg = <0x58>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_pmic>;
228 interrupt-parent = <&gpio2>;
229 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
230 interrupt-controller;
231
232 onkey {
233 compatible = "dlg,da9063-onkey";
234 wakeup-source;
235 };
236
237 watchdog {
238 compatible = "dlg,da9063-watchdog";
239 timeout-sec = <0>;
240 };
241
242 regulators {
243 vddcore_reg: bcore1 {
244 regulator-min-microvolt = <1100000>;
245 regulator-max-microvolt = <1450000>;
246 regulator-ramp-delay = <2>;
247 regulator-name = "DA9063_CORE";
248 regulator-always-on;
249 };
250
251 vddsoc_reg: bcore2 {
252 regulator-min-microvolt = <1100000>;
253 regulator-max-microvolt = <1450000>;
254 regulator-ramp-delay = <2>;
255 regulator-name = "DA9063_SOC";
256 regulator-always-on;
257 };
258
259 vdd_ddr3_reg: bpro {
260 regulator-min-microvolt = <1500000>;
261 regulator-max-microvolt = <1500000>;
262 regulator-ramp-delay = <2>;
263 regulator-always-on;
264 };
265
266 vdd_3v3_reg: bperi {
267 regulator-min-microvolt = <3300000>;
268 regulator-max-microvolt = <3300000>;
269 regulator-ramp-delay = <2>;
270 regulator-always-on;
271 };
272
273 vdd_sata_reg: ldo3 {
274 regulator-min-microvolt = <2500000>;
275 regulator-max-microvolt = <2500000>;
276 regulator-always-on;
277 };
278 vdd_mipi_reg: ldo4 {
279 regulator-min-microvolt = <2500000>;
280 regulator-max-microvolt = <2500000>;
281 regulator-always-on;
282 };
283
284 vdd_mx6_snvs_reg: ldo5 {
285 regulator-min-microvolt = <3300000>;
286 regulator-max-microvolt = <3300000>;
287 regulator-always-on;
288 };
289
290 vdd_hdmi_reg: ldo6 {
291 regulator-min-microvolt = <2500000>;
292 regulator-max-microvolt = <2500000>;
293 regulator-always-on;
294 regulator-boot-on;
295 };
296
297 vdd_pcie_reg: ldo7 {
298 regulator-min-microvolt = <2500000>;
299 regulator-max-microvolt = <2500000>;
300 regulator-always-on;
301 };
302
303 vdd_1V8_reg: ldo8 {
304 regulator-min-microvolt = <1800000>;
305 regulator-max-microvolt = <1800000>;
306 regulator-always-on;
307 };
308
309 vdd_3V3_sdc_reg: ldo9 {
310 regulator-min-microvolt = <1800000>;
311 regulator-max-microvolt = <3300000>;
312 regulator-always-on;
313 };
314
315 vdd_1V2_reg: ldo10 {
316 regulator-min-microvolt = <1200000>;
317 regulator-max-microvolt = <1200000>;
318 regulator-always-on;
319 };
320 };
321 };
322
323 ds1307: rtc@68 {
324 compatible = "dallas,ds1307";
325 reg = <0x68>;
326 };
327};
328
329&i2c2 {
330 clock-frequency = <100000>;
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_i2c2>;
333};
334
335&iomuxc {
336
337 pinctrl_audmux: audmuxgrp {
338 fsl,pins = <
339 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
340 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060
341 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0
342 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060
343 >;
344 };
345
346 pinctrl_can1: can1grp {
347 fsl,pins = <
348 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
349 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
350 >;
351 };
352
353 pinctrl_can2: can2grp {
354 fsl,pins = <
355 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1
356 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1
357 >;
358 };
359
360 pinctrl_cpi1: csi0grp {
361 fsl,pins = <
362 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
363 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1
364 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1
365 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1
366 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1
367 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1
368 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1
369 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1
370 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1
371 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1
372 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1
373 >;
374 };
375
376 /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/
377
378 pinctrl_ecspi2: ecspi2grp {
379 fsl,pins = <
380 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
381 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
382 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
383 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1
384 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
385 >;
386 };
387
388 pinctrl_emcon_gpio1: emcongpio1 {
389 fsl,pins = <
390 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1
391 >;
392 };
393
394 pinctrl_emcon_gpio2: emcongpio2 {
395 fsl,pins = <
396 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1
397 >;
398 };
399
400 pinctrl_emcon_gpio3: emcongpio3 {
401 fsl,pins = <
402 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1
403 >;
404 };
405
406 pinctrl_emcon_gpio4: emcongpio4 {
407 fsl,pins = <
408 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1
409 >;
410 };
411
412 pinctrl_emcon_gpio5: emcongpio5 {
413 fsl,pins = <
414 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1
415 >;
416 };
417
418 pinctrl_emcon_gpio6: emcongpio6 {
419 fsl,pins = <
420 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1
421 >;
422 };
423
424 pinctrl_emcon_gpio7: emcongpio7 {
425 fsl,pins = <
426 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1
427 >;
428 };
429
430 pinctrl_emcon_gpio8: emcongpio8 {
431 fsl,pins = <
432 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1
433 >;
434 };
435
436 pinctrl_emcon_irq_a: emconirqa {
437 fsl,pins = <
438 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1
439 >;
440 };
441
442 pinctrl_emcon_irq_b: emconirqb {
443 fsl,pins = <
444 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1
445 >;
446 };
447
448 pinctrl_emcon_irq_c: emconirqc {
449 fsl,pins = <
450 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1
451 >;
452 };
453
454 pinctrl_emcon_irq_pwr: emconirqpwr {
455 fsl,pins = <
456 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1
457 >;
458 };
459
460 pinctrl_emcon_wake: emconwake {
461 fsl,pins = <
462 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1
463 >;
464 };
465
466 pinctrl_enet: enetgrp {
467 fsl,pins = <
468 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030
469 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030
470 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
471 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
472 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
473 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
474 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
475 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
476 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1
477 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
478 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
479 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
480 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
481 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
482 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
483 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058
484 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
485 >;
486 };
487
488 pinctrl_i2c1: i2c1grp {
489 fsl,pins = <
490 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
491 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
492 >;
493 };
494
495 pinctrl_i2c2: i2c2grp {
496 fsl,pins = <
497 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
498 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
499 >;
500 };
501
502 pinctrl_i2c3: i2c3grp {
503 fsl,pins = <
504 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070
505 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870
506 >;
507 };
508
509 pinctrl_irq_touch1: irqtouch1 {
510 fsl,pins = <
511 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1
512 >;
513 };
514
515 pinctrl_irq_touch2: irqtouch2 {
516 fsl,pins = <
517 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1
518 >;
519 };
520
521 pinctrl_lvds_bl: lvdsbacklightgrp {
522 fsl,pins = <
523 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1
524 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1
525 >;
526 };
527
528 pinctrl_lvds_reg: lvdsreggrp {
529 fsl,pins = <
530 MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1
531 >;
532 };
533
534
535 pinctrl_nor_flash: norflashgrp {
536 fsl,pins = <
537 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1
538 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
539 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
540 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
541 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1
542 >;
543 };
544
545 pinctrl_pcie_ctrl: pciegrp {
546 fsl,pins = <
547 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1
548 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1
549 >;
550 };
551
552 pinctrl_pmic: pmicgrp {
553 fsl,pins = <
554 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1
555 >;
556 };
557
558 pinctrl_pwm_fan: pwmfan {
559 fsl,pins = <
560 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1
561 >;
562 };
563
564 pinctrl_rgb_bl: rgbbacklightgrp {
565 fsl,pins = <
566 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1
567 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1
568 >;
569 };
570
571 pinctrl_rgb_bl_en: rgbenable {
572 fsl,pins = <
573 MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1
574 >;
575 };
576
577 pinctrl_rgb24_display: rgbgrp {
578 fsl,pins = <
579 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
580 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
581 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
582 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
583 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
584 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
585 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
586 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
587 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
588 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
589 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
590 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
591 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
592 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
593 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
594 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
595 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
596 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
597 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
598 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
599 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
600 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
601 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
602 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
603 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
604 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
605 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
606 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
607 >;
608 };
609
610 pinctrl_secure: securegrp {
611 fsl,pins = <
612 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
613 >;
614 };
615
616 pinctrl_som_leds: somledgrp {
617 fsl,pins = <
618 MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1
619 MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1
620 >;
621 };
622
623 pinctrl_spdif_in: spdifin {
624 fsl,pins = <
625 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
626 >;
627 };
628
629 pinctrl_spdif_out: spdifout {
630 fsl,pins = <
631 MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091
632 >;
633 };
634
635 pinctrl_uart1: uart1grp {
636 fsl,pins = <
637 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
638 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
639 >;
640 };
641
642 pinctrl_uart2: uart2grp {
643 fsl,pins = <
644 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
645 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
646 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
647 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
648 >;
649 };
650
651 pinctrl_uart3: uart3grp {
652 fsl,pins = <
653 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
654 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
655 >;
656 };
657
658 pinctrl_uart4: uart4grp {
659 fsl,pins = <
660 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
661 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
662 >;
663 };
664
665 pinctrl_uart5: uart5grp {
666 fsl,pins = <
667 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
668 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
669 >;
670 };
671
672 pinctrl_usb_host1: usbhgrp {
673 fsl,pins = <
674 MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058
675 MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058
676 >;
677 };
678
679 pinctrl_usb_otg: usbotggrp {
680 fsl,pins = <
681 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
682 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059
683 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059
684 >;
685 };
686
687 pinctrl_usdhc1: usdhc1grp {
688 fsl,pins = <
689 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
690 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
691 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
692 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
693 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
694 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
695 MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1
696 MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1
697 >;
698 };
699
700 pinctrl_usdhc2: usdhc2grp {
701 fsl,pins = <
702 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
703 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
704 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
705 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
706 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
707 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
708 MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1
709 MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1
710 >;
711 };
712
713 pinctrl_usdhc3: usdhc3grp {
714 fsl,pins = <
715 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
716 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
717 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
718 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
719 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
720 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
721 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
722 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
723 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
724 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
725 MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
726 >;
727 };
728};
729
730&ipu1_di0_disp0 {
731 remote-endpoint = <&rgb_encoder_in>;
732};
733
734&pcie {
735 pinctrl-names = "default";
736 pinctrl-0 = <&pinctrl_pcie_ctrl>;
737 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
738 disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>;
739};
740
741&pwm1 {
742 status = "okay";
743};
744
745&pwm3 {
746 status = "okay";
747};
748
749&pwm4 {
750 status = "okay";
751};
752
753&uart1 {
754 pinctrl-names = "default";
755 pinctrl-0 = <&pinctrl_uart1>;
756 status = "okay";
757};
758
759&uart2 {
760 pinctrl-names = "default";
761 pinctrl-0 = <&pinctrl_uart2>;
762};
763
764&uart3 {
765 pinctrl-names = "default";
766 pinctrl-0 = <&pinctrl_uart3>;
767};
768
769&uart4 {
770 pinctrl-names = "default";
771 pinctrl-0 = <&pinctrl_uart4>;
772};
773
774&uart5 {
775 pinctrl-names = "default";
776 pinctrl-0 = <&pinctrl_uart5>;
777};
778
779&usbh1 {
780 pinctrl-names = "default";
781 pinctrl-0 = <&pinctrl_usb_host1>;
782};
783
784&usbotg {
785 pinctrl-names = "default";
786 pinctrl-0 = <&pinctrl_usb_otg>;
787 vbus-supply = <&reg_usb_otg>;
788 dr_mode = "peripheral";
789};
790
791&usdhc1 {
792 pinctrl-names = "default";
793 pinctrl-0 = <&pinctrl_usdhc1>;
794 fsl,wp-controller;
795};
796
797&usdhc2 {
798 pinctrl-names = "default";
799 pinctrl-0 = <&pinctrl_usdhc2>;
800 fsl,wp-controller;
801};
802
803&usdhc3 {
804 pinctrl-names = "default";
805 pinctrl-0 = <&pinctrl_usdhc3>;
806 non-removable;
807 bus-width = <8>;
808 status = "okay";
809};
810
811/******device power Management*********/
812
813&cpu0 {
814 voltage-tolerance = <2>;
815};
816
817&reg_arm {
818 vin-supply = <&vddcore_reg>;
819};
820
821&reg_soc {
822 vin-supply = <&vddsoc_reg>;
823};
824
825&reg_pu {
826 vin-supply = <&vddsoc_reg>;
827};
828
829/*******Disabled HW following***********/
830
831&snvs_rtc {
832 status = "disabled";
833};
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