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UBUNTU: Ubuntu-5.3.0-29.31
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx6qdl-emcon.dtsi
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63e71fed
JT		 1// SPDX-License-Identifier: (GPL-2.0 or MIT)
2//
3// Copyright (C) 2018 emtrion GmbH
4//
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/pwm/pwm.h>
8#include <dt-bindings/input/input.h>
9
10/ {
11
12 model = "emtrion SoM emCON-MX6";
13 compatible = "emtrion,emcon-mx6";
14
15 aliases {
16 mmc0 = &usdhc3;
17 mmc1 = &usdhc2;
18 mmc2 = &usdhc1;
19 rtc0 = &ds1307;
20 };
21
22 chosen {
23 stdout-path = &uart1;
24 };
25
26 memory@10000000 {
404c0c93 27 device_type = "memory";
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JT		 28 reg = <0x10000000 0x40000000>;
29 };
30
31 gpio-keys {
32 compatible = "gpio-keys";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_emcon_wake>;
35
36 wake {
37 label = "Wake";
38 linux,code = <KEY_WAKEUP>;
39 gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
40 wakeup-source;
41 };
42 };
43
44 som_leds: leds {
45 compatible = "gpio-leds";
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_som_leds>;
48
49 green {
50 label = "som:green";
51 gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
52 linux,default-trigger = "heartbeat";
53 default-state = "on";
54 };
55
56 red {
57 label = "som:red";
58 gpios = <&gpio3 1 GPIO_ACTIVE_LOW>;
59 default-state = "keep";
60 };
61
62 };
63
64 lvds_backlight: lvds-backlight {
65 compatible = "pwm-backlight";
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_lvds_bl>;
68 enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
69 pwms = <&pwm1 0 50000>;
70 brightness-levels = <
71 0 4 8 16 32 64 80 96 112
72 128 144 160 176 250
73 >;
74 default-brightness-level = <13>;
75 status = "okay";
76 };
77
78 pwm_fan: pwm-fan {
79 compatible = "pwm-fan";
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JT		 80 #cooling-cells = <2>;
81 pwms = <&pwm4 0 50000>;
82 cooling-levels = <0 64 127 191 255>;
83 status = "disabled";
84 };
85
86
87 rgb_encoder: display {
88 compatible = "fsl,imx-parallel-display";
89 #address-cells = <1>;
90 #size-cells = <0>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_rgb24_display>;
93 status = "disabled";
94
95 port@0 {
96 reg = <0>;
97
98 rgb_encoder_in: endpoint {
99 remote-endpoint = <&ipu1_di0_disp0>;
100 };
101 };
102
103 port@1 {
104 reg = <1>;
105
106 rgb_encoder_out: endpoint {
107 remote-endpoint = <&rgb_panel_in>;
108 };
109 };
110 };
111
112 rgb_panel: lcd {
113 backlight = <&rgb_backlight>;
114 power-supply = <&reg_parallel_disp>;
115
116 port {
117 rgb_panel_in: endpoint {
118 remote-endpoint = <&rgb_encoder_out>;
119 };
120 };
121 };
122
123 reg_parallel_disp: reg-parallel-display {
124 compatible = "regulator-fixed";
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_rgb_bl_en>;
127 regulator-name = "LCD-Supply";
128 regulator-min-microvolt = <5000000>;
129 regulator-max-microvolt = <5000000>;
130 gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>;
131 enable-active-high;
132 };
133
134 reg_lvds_disp: reg-lvds-display {
135 compatible = "regulator-fixed";
136 regulator-name = "LVDS-Supply";
137 regulator-min-microvolt = <5000000>;
138 regulator-max-microvolt = <5000000>;
139 gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>;
140 enable-active-high;
141 };
142
143 rgb_backlight: rgb-backlight {
144 compatible = "pwm-backlight";
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_rgb_bl>;
147 enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
148 pwms = <&pwm3 0 5000000>;
149 brightness-levels = <
150 250 176 160 144 128 112
151 96 80 64 48 32 16 8 1
152 >;
153 default-brightness-level = <13>;
154 status = "okay";
155 };
156};
157
158&can1 {
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_can1>;
161};
162
163&can2 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_can2>;
166};
167
168&ecspi2 {
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_ecspi2>;
171 cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>,
172 <&gpio2 27 GPIO_ACTIVE_HIGH>;
173};
174
175&ecspi4 {
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_nor_flash>;
178};
179
180&fec {
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_enet>;
183 phy-mode = "rgmii";
184 phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
185 phy-reset-duration = <50>;
186 phy-supply = <&vdd_1V8_reg>;
187 phy-handle = <&ksz9031>;
188 status = "okay";
189
190 mdio {
191 #address-cells = <1>;
192 #size-cells = <0>;
193
194 ksz9031: phy@0 {
195 compatible = "ethernet-phy-ieee802.3-c22";
196 reg = <0>;
197 interrupt-parent = <&gpio1>;
198 interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
199 rxdv-skew-ps = <480>;
200 txen-skew-ps = <480>;
201 rxd0-skew-ps = <480>;
202 rxd1-skew-ps = <480>;
203 rxd2-skew-ps = <480>;
204 rxd3-skew-ps = <480>;
205 txd0-skew-ps = <420>;
206 txd1-skew-ps = <420>;
207 txd2-skew-ps = <360>;
208 txd3-skew-ps = <360>;
209 txc-skew-ps = <1020>;
210 rxc-skew-ps = <960>;
211 };
212 };
213};
214
215&i2c1 {
216 clock-frequency = <100000>;
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_i2c1>;
219 status = "okay";
220
221 da9063: pmic@58 {
222 compatible = "dlg,da9063";
223 reg = <0x58>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_pmic>;
226 interrupt-parent = <&gpio2>;
227 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
228 interrupt-controller;
229
230 onkey {
231 compatible = "dlg,da9063-onkey";
232 wakeup-source;
233 };
234
235 watchdog {
236 compatible = "dlg,da9063-watchdog";
237 timeout-sec = <0>;
238 };
239
240 regulators {
241 vddcore_reg: bcore1 {
242 regulator-min-microvolt = <1100000>;
243 regulator-max-microvolt = <1450000>;
244 regulator-ramp-delay = <2>;
245 regulator-name = "DA9063_CORE";
246 regulator-always-on;
247 };
248
249 vddsoc_reg: bcore2 {
250 regulator-min-microvolt = <1100000>;
251 regulator-max-microvolt = <1450000>;
252 regulator-ramp-delay = <2>;
253 regulator-name = "DA9063_SOC";
254 regulator-always-on;
255 };
256
257 vdd_ddr3_reg: bpro {
258 regulator-min-microvolt = <1500000>;
259 regulator-max-microvolt = <1500000>;
260 regulator-ramp-delay = <2>;
261 regulator-always-on;
262 };
263
264 vdd_3v3_reg: bperi {
265 regulator-min-microvolt = <3300000>;
266 regulator-max-microvolt = <3300000>;
267 regulator-ramp-delay = <2>;
268 regulator-always-on;
269 };
270
271 vdd_sata_reg: ldo3 {
272 regulator-min-microvolt = <2500000>;
273 regulator-max-microvolt = <2500000>;
274 regulator-always-on;
275 };
276 vdd_mipi_reg: ldo4 {
277 regulator-min-microvolt = <2500000>;
278 regulator-max-microvolt = <2500000>;
279 regulator-always-on;
280 };
281
282 vdd_mx6_snvs_reg: ldo5 {
283 regulator-min-microvolt = <3300000>;
284 regulator-max-microvolt = <3300000>;
285 regulator-always-on;
286 };
287
288 vdd_hdmi_reg: ldo6 {
289 regulator-min-microvolt = <2500000>;
290 regulator-max-microvolt = <2500000>;
291 regulator-always-on;
292 regulator-boot-on;
293 };
294
295 vdd_pcie_reg: ldo7 {
296 regulator-min-microvolt = <2500000>;
297 regulator-max-microvolt = <2500000>;
298 regulator-always-on;
299 };
300
301 vdd_1V8_reg: ldo8 {
302 regulator-min-microvolt = <1800000>;
303 regulator-max-microvolt = <1800000>;
304 regulator-always-on;
305 };
306
307 vdd_3V3_sdc_reg: ldo9 {
308 regulator-min-microvolt = <1800000>;
309 regulator-max-microvolt = <3300000>;
310 regulator-always-on;
311 };
312
313 vdd_1V2_reg: ldo10 {
314 regulator-min-microvolt = <1200000>;
315 regulator-max-microvolt = <1200000>;
316 regulator-always-on;
317 };
318 };
319 };
320
321 ds1307: rtc@68 {
322 compatible = "dallas,ds1307";
323 reg = <0x68>;
324 };
325};
326
327&i2c2 {
328 clock-frequency = <100000>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_i2c2>;
331};
332
333&iomuxc {
334
335 pinctrl_audmux: audmuxgrp {
336 fsl,pins = <
337 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
338 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060
339 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0
340 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060
341 >;
342 };
343
344 pinctrl_can1: can1grp {
345 fsl,pins = <
346 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
347 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
348 >;
349 };
350
351 pinctrl_can2: can2grp {
352 fsl,pins = <
353 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1
354 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1
355 >;
356 };
357
358 pinctrl_cpi1: csi0grp {
359 fsl,pins = <
360 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
361 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1
362 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1
363 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1
364 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1
365 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1
366 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1
367 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1
368 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1
369 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1
370 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1
371 >;
372 };
373
374 /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/
375
376 pinctrl_ecspi2: ecspi2grp {
377 fsl,pins = <
378 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
379 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
380 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
381 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1
382 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
383 >;
384 };
385
386 pinctrl_emcon_gpio1: emcongpio1 {
387 fsl,pins = <
388 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1
389 >;
390 };
391
392 pinctrl_emcon_gpio2: emcongpio2 {
393 fsl,pins = <
394 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1
395 >;
396 };
397
398 pinctrl_emcon_gpio3: emcongpio3 {
399 fsl,pins = <
400 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1
401 >;
402 };
403
404 pinctrl_emcon_gpio4: emcongpio4 {
405 fsl,pins = <
406 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1
407 >;
408 };
409
410 pinctrl_emcon_gpio5: emcongpio5 {
411 fsl,pins = <
412 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1
413 >;
414 };
415
416 pinctrl_emcon_gpio6: emcongpio6 {
417 fsl,pins = <
418 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1
419 >;
420 };
421
422 pinctrl_emcon_gpio7: emcongpio7 {
423 fsl,pins = <
424 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1
425 >;
426 };
427
428 pinctrl_emcon_gpio8: emcongpio8 {
429 fsl,pins = <
430 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1
431 >;
432 };
433
434 pinctrl_emcon_irq_a: emconirqa {
435 fsl,pins = <
436 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1
437 >;
438 };
439
440 pinctrl_emcon_irq_b: emconirqb {
441 fsl,pins = <
442 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1
443 >;
444 };
445
446 pinctrl_emcon_irq_c: emconirqc {
447 fsl,pins = <
448 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1
449 >;
450 };
451
452 pinctrl_emcon_irq_pwr: emconirqpwr {
453 fsl,pins = <
454 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1
455 >;
456 };
457
458 pinctrl_emcon_wake: emconwake {
459 fsl,pins = <
460 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1
461 >;
462 };
463
464 pinctrl_enet: enetgrp {
465 fsl,pins = <
466 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030
467 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030
468 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
469 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
470 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
471 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
472 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
473 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
474 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1
475 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
476 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
477 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
478 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
479 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
480 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
481 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058
482 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
483 >;
484 };
485
486 pinctrl_i2c1: i2c1grp {
487 fsl,pins = <
488 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
489 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
490 >;
491 };
492
493 pinctrl_i2c2: i2c2grp {
494 fsl,pins = <
495 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
496 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
497 >;
498 };
499
500 pinctrl_i2c3: i2c3grp {
501 fsl,pins = <
502 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070
503 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870
504 >;
505 };
506
507 pinctrl_irq_touch1: irqtouch1 {
508 fsl,pins = <
509 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1
510 >;
511 };
512
513 pinctrl_irq_touch2: irqtouch2 {
514 fsl,pins = <
515 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1
516 >;
517 };
518
519 pinctrl_lvds_bl: lvdsbacklightgrp {
520 fsl,pins = <
521 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1
522 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1
523 >;
524 };
525
526 pinctrl_lvds_reg: lvdsreggrp {
527 fsl,pins = <
528 MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1
529 >;
530 };
531
532
533 pinctrl_nor_flash: norflashgrp {
534 fsl,pins = <
535 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1
536 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
537 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
538 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
539 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1
540 >;
541 };
542
543 pinctrl_pcie_ctrl: pciegrp {
544 fsl,pins = <
545 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1
546 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1
547 >;
548 };
549
550 pinctrl_pmic: pmicgrp {
551 fsl,pins = <
552 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1
553 >;
554 };
555
556 pinctrl_pwm_fan: pwmfan {
557 fsl,pins = <
558 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1
559 >;
560 };
561
562 pinctrl_rgb_bl: rgbbacklightgrp {
563 fsl,pins = <
564 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1
565 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1
566 >;
567 };
568
569 pinctrl_rgb_bl_en: rgbenable {
570 fsl,pins = <
571 MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1
572 >;
573 };
574
575 pinctrl_rgb24_display: rgbgrp {
576 fsl,pins = <
577 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
578 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
579 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
580 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
581 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
582 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
583 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
584 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
585 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
586 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
587 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
588 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
589 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
590 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
591 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
592 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
593 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
594 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
595 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
596 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
597 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
598 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
599 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
600 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
601 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
602 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
603 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
604 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
605 >;
606 };
607
608 pinctrl_secure: securegrp {
609 fsl,pins = <
610 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
611 >;
612 };
613
614 pinctrl_som_leds: somledgrp {
615 fsl,pins = <
616 MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1
617 MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1
618 >;
619 };
620
621 pinctrl_spdif_in: spdifin {
622 fsl,pins = <
623 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
624 >;
625 };
626
627 pinctrl_spdif_out: spdifout {
628 fsl,pins = <
629 MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091
630 >;
631 };
632
633 pinctrl_uart1: uart1grp {
634 fsl,pins = <
635 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
636 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
637 >;
638 };
639
640 pinctrl_uart2: uart2grp {
641 fsl,pins = <
642 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
643 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
644 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
645 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
646 >;
647 };
648
649 pinctrl_uart3: uart3grp {
650 fsl,pins = <
651 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
652 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
653 >;
654 };
655
656 pinctrl_uart4: uart4grp {
657 fsl,pins = <
658 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
659 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
660 >;
661 };
662
663 pinctrl_uart5: uart5grp {
664 fsl,pins = <
665 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
666 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
667 >;
668 };
669
670 pinctrl_usb_host1: usbhgrp {
671 fsl,pins = <
672 MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058
673 MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058
674 >;
675 };
676
677 pinctrl_usb_otg: usbotggrp {
678 fsl,pins = <
679 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
680 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059
681 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059
682 >;
683 };
684
685 pinctrl_usdhc1: usdhc1grp {
686 fsl,pins = <
687 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
688 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
689 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
690 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
691 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
692 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
693 MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1
694 MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1
695 >;
696 };
697
698 pinctrl_usdhc2: usdhc2grp {
699 fsl,pins = <
700 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
701 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
702 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
703 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
704 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
705 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
706 MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1
707 MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1
708 >;
709 };
710
711 pinctrl_usdhc3: usdhc3grp {
712 fsl,pins = <
713 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
714 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
715 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
716 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
717 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
718 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
719 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
720 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
721 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
722 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
723 MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
724 >;
725 };
726};
727
728&ipu1_di0_disp0 {
729 remote-endpoint = <&rgb_encoder_in>;
730};
731
732&pcie {
733 pinctrl-names = "default";
734 pinctrl-0 = <&pinctrl_pcie_ctrl>;
735 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
736 disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>;
737};
738
739&pwm1 {
740 status = "okay";
741};
742
743&pwm3 {
744 status = "okay";
745};
746
747&pwm4 {
748 status = "okay";
749};
750
751&uart1 {
752 pinctrl-names = "default";
753 pinctrl-0 = <&pinctrl_uart1>;
754 status = "okay";
755};
756
757&uart2 {
758 pinctrl-names = "default";
759 pinctrl-0 = <&pinctrl_uart2>;
760};
761
762&uart3 {
763 pinctrl-names = "default";
764 pinctrl-0 = <&pinctrl_uart3>;
765};
766
767&uart4 {
768 pinctrl-names = "default";
769 pinctrl-0 = <&pinctrl_uart4>;
770};
771
772&uart5 {
773 pinctrl-names = "default";
774 pinctrl-0 = <&pinctrl_uart5>;
775};
776
777&usbh1 {
778 pinctrl-names = "default";
779 pinctrl-0 = <&pinctrl_usb_host1>;
780};
781
782&usbotg {
783 pinctrl-names = "default";
784 pinctrl-0 = <&pinctrl_usb_otg>;
785 vbus-supply = <&reg_usb_otg>;
786 dr_mode = "peripheral";
787};
788
789&usdhc1 {
790 pinctrl-names = "default";
791 pinctrl-0 = <&pinctrl_usdhc1>;
792 fsl,wp-controller;
793};
794
795&usdhc2 {
796 pinctrl-names = "default";
797 pinctrl-0 = <&pinctrl_usdhc2>;
798 fsl,wp-controller;
799};
800
801&usdhc3 {
802 pinctrl-names = "default";
803 pinctrl-0 = <&pinctrl_usdhc3>;
804 non-removable;
805 bus-width = <8>;
806 status = "okay";
807};
808
809/******device power Management*********/
810
811&cpu0 {
812 voltage-tolerance = <2>;
813};
814
815&reg_arm {
816 vin-supply = <&vddcore_reg>;
817};
818
819&reg_soc {
820 vin-supply = <&vddsoc_reg>;
821};
822
823&reg_pu {
824 vin-supply = <&vddsoc_reg>;
825};
826
827/*******Disabled HW following***********/
828
829&snvs_rtc {
830 status = "disabled";
831};
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