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e3946fe8 TH |
1 | /* |
2 | * Copyright 2013 Gateworks Corporation | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
326cdb16 TH |
12 | #include <dt-bindings/gpio/gpio.h> |
13 | ||
e3946fe8 TH |
14 | / { |
15 | /* these are used by bootloader for disabling nodes */ | |
16 | aliases { | |
e3946fe8 TH |
17 | ethernet1 = ð1; |
18 | led0 = &led0; | |
19 | led1 = &led1; | |
20 | led2 = &led2; | |
21 | nand = &gpmi; | |
e3946fe8 TH |
22 | ssi0 = &ssi1; |
23 | usb0 = &usbh1; | |
24 | usb1 = &usbotg; | |
e3946fe8 TH |
25 | }; |
26 | ||
27 | chosen { | |
28 | bootargs = "console=ttymxc1,115200"; | |
29 | }; | |
30 | ||
b3253241 TH |
31 | backlight { |
32 | compatible = "pwm-backlight"; | |
33 | pwms = <&pwm4 0 5000000>; | |
34 | brightness-levels = <0 4 8 16 32 64 128 255>; | |
35 | default-brightness-level = <7>; | |
36 | }; | |
37 | ||
e3946fe8 TH |
38 | leds { |
39 | compatible = "gpio-leds"; | |
b5f37b76 TH |
40 | pinctrl-names = "default"; |
41 | pinctrl-0 = <&pinctrl_gpio_leds>; | |
e3946fe8 TH |
42 | |
43 | led0: user1 { | |
44 | label = "user1"; | |
326cdb16 | 45 | gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ |
e3946fe8 TH |
46 | default-state = "on"; |
47 | linux,default-trigger = "heartbeat"; | |
48 | }; | |
49 | ||
50 | led1: user2 { | |
51 | label = "user2"; | |
326cdb16 | 52 | gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ |
e3946fe8 TH |
53 | default-state = "off"; |
54 | }; | |
55 | ||
56 | led2: user3 { | |
57 | label = "user3"; | |
326cdb16 | 58 | gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ |
e3946fe8 TH |
59 | default-state = "off"; |
60 | }; | |
61 | }; | |
62 | ||
63 | memory { | |
64 | reg = <0x10000000 0x40000000>; | |
65 | }; | |
66 | ||
67 | pps { | |
68 | compatible = "pps-gpio"; | |
b5f37b76 TH |
69 | pinctrl-names = "default"; |
70 | pinctrl-0 = <&pinctrl_pps>; | |
326cdb16 | 71 | gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; |
e3946fe8 TH |
72 | status = "okay"; |
73 | }; | |
74 | ||
75 | regulators { | |
76 | compatible = "simple-bus"; | |
77 | #address-cells = <1>; | |
78 | #size-cells = <0>; | |
79 | ||
80 | reg_1p0v: regulator@0 { | |
81 | compatible = "regulator-fixed"; | |
82 | reg = <0>; | |
83 | regulator-name = "1P0V"; | |
84 | regulator-min-microvolt = <1000000>; | |
85 | regulator-max-microvolt = <1000000>; | |
86 | regulator-always-on; | |
87 | }; | |
88 | ||
89 | /* remove when pmic 1p8 regulator available */ | |
90 | reg_1p8v: regulator@1 { | |
91 | compatible = "regulator-fixed"; | |
92 | reg = <1>; | |
93 | regulator-name = "1P8V"; | |
94 | regulator-min-microvolt = <1800000>; | |
95 | regulator-max-microvolt = <1800000>; | |
96 | regulator-always-on; | |
97 | }; | |
98 | ||
99 | reg_3p3v: regulator@2 { | |
100 | compatible = "regulator-fixed"; | |
101 | reg = <2>; | |
102 | regulator-name = "3P3V"; | |
103 | regulator-min-microvolt = <3300000>; | |
104 | regulator-max-microvolt = <3300000>; | |
105 | regulator-always-on; | |
106 | }; | |
107 | ||
108 | reg_usb_h1_vbus: regulator@3 { | |
109 | compatible = "regulator-fixed"; | |
110 | reg = <3>; | |
111 | regulator-name = "usb_h1_vbus"; | |
112 | regulator-min-microvolt = <5000000>; | |
113 | regulator-max-microvolt = <5000000>; | |
114 | regulator-always-on; | |
115 | }; | |
116 | ||
117 | reg_usb_otg_vbus: regulator@4 { | |
118 | compatible = "regulator-fixed"; | |
119 | reg = <4>; | |
120 | regulator-name = "usb_otg_vbus"; | |
121 | regulator-min-microvolt = <5000000>; | |
122 | regulator-max-microvolt = <5000000>; | |
326cdb16 | 123 | gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; |
e3946fe8 TH |
124 | enable-active-high; |
125 | }; | |
126 | }; | |
127 | ||
128 | sound { | |
b12d1e94 | 129 | compatible = "fsl,imx6q-ventana-sgtl5000", |
e3946fe8 | 130 | "fsl,imx-audio-sgtl5000"; |
b12d1e94 | 131 | model = "sgtl5000-audio"; |
e3946fe8 TH |
132 | ssi-controller = <&ssi1>; |
133 | audio-codec = <&codec>; | |
134 | audio-routing = | |
135 | "MIC_IN", "Mic Jack", | |
136 | "Mic Jack", "Mic Bias", | |
137 | "Headphone Jack", "HP_OUT"; | |
138 | mux-int-port = <1>; | |
139 | mux-ext-port = <4>; | |
140 | }; | |
141 | }; | |
142 | ||
143 | &audmux { | |
144 | pinctrl-names = "default"; | |
145 | pinctrl-0 = <&pinctrl_audmux>; | |
146 | status = "okay"; | |
147 | }; | |
148 | ||
149 | &can1 { | |
150 | pinctrl-names = "default"; | |
151 | pinctrl-0 = <&pinctrl_flexcan1>; | |
152 | status = "okay"; | |
153 | }; | |
154 | ||
e726a9fd TH |
155 | &clks { |
156 | assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, | |
157 | <&clks IMX6QDL_CLK_LDB_DI1_SEL>; | |
158 | assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, | |
159 | <&clks IMX6QDL_CLK_PLL3_USB_OTG>; | |
160 | }; | |
161 | ||
e3946fe8 TH |
162 | &fec { |
163 | pinctrl-names = "default"; | |
164 | pinctrl-0 = <&pinctrl_enet>; | |
3a35e470 | 165 | phy-mode = "rgmii-id"; |
326cdb16 | 166 | phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; |
e3946fe8 TH |
167 | status = "okay"; |
168 | }; | |
169 | ||
170 | &gpmi { | |
171 | pinctrl-names = "default"; | |
172 | pinctrl-0 = <&pinctrl_gpmi_nand>; | |
173 | status = "okay"; | |
174 | }; | |
175 | ||
aef15dba TH |
176 | &hdmi { |
177 | ddc-i2c-bus = <&i2c3>; | |
178 | status = "okay"; | |
179 | }; | |
180 | ||
e3946fe8 TH |
181 | &i2c1 { |
182 | clock-frequency = <100000>; | |
183 | pinctrl-names = "default"; | |
184 | pinctrl-0 = <&pinctrl_i2c1>; | |
185 | status = "okay"; | |
186 | ||
187 | eeprom1: eeprom@50 { | |
188 | compatible = "atmel,24c02"; | |
189 | reg = <0x50>; | |
190 | pagesize = <16>; | |
191 | }; | |
192 | ||
193 | eeprom2: eeprom@51 { | |
194 | compatible = "atmel,24c02"; | |
195 | reg = <0x51>; | |
196 | pagesize = <16>; | |
197 | }; | |
198 | ||
199 | eeprom3: eeprom@52 { | |
200 | compatible = "atmel,24c02"; | |
201 | reg = <0x52>; | |
202 | pagesize = <16>; | |
203 | }; | |
204 | ||
205 | eeprom4: eeprom@53 { | |
206 | compatible = "atmel,24c02"; | |
207 | reg = <0x53>; | |
208 | pagesize = <16>; | |
209 | }; | |
210 | ||
211 | gpio: pca9555@23 { | |
212 | compatible = "nxp,pca9555"; | |
213 | reg = <0x23>; | |
214 | gpio-controller; | |
215 | #gpio-cells = <2>; | |
216 | }; | |
217 | ||
e3946fe8 TH |
218 | rtc: ds1672@68 { |
219 | compatible = "dallas,ds1672"; | |
220 | reg = <0x68>; | |
221 | }; | |
222 | }; | |
223 | ||
224 | &i2c2 { | |
225 | clock-frequency = <100000>; | |
226 | pinctrl-names = "default"; | |
227 | pinctrl-0 = <&pinctrl_i2c2>; | |
228 | status = "okay"; | |
e3946fe8 TH |
229 | }; |
230 | ||
231 | &i2c3 { | |
232 | clock-frequency = <100000>; | |
233 | pinctrl-names = "default"; | |
234 | pinctrl-0 = <&pinctrl_i2c3>; | |
235 | status = "okay"; | |
236 | ||
e3946fe8 TH |
237 | codec: sgtl5000@0a { |
238 | compatible = "fsl,sgtl5000"; | |
239 | reg = <0x0a>; | |
240 | clocks = <&clks 201>; | |
241 | VDDA-supply = <®_1p8v>; | |
242 | VDDIO-supply = <®_3p3v>; | |
243 | }; | |
244 | ||
e3946fe8 TH |
245 | touchscreen: egalax_ts@04 { |
246 | compatible = "eeti,egalax_ts"; | |
247 | reg = <0x04>; | |
248 | interrupt-parent = <&gpio1>; | |
326cdb16 TH |
249 | interrupts = <11 2>; |
250 | wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; | |
e3946fe8 | 251 | }; |
e3946fe8 TH |
252 | }; |
253 | ||
b5f37b76 TH |
254 | &ldb { |
255 | status = "okay"; | |
e3946fe8 | 256 | |
a7668fda | 257 | lvds-channel@0 { |
b5f37b76 TH |
258 | fsl,data-mapping = "spwg"; |
259 | fsl,data-width = <18>; | |
260 | status = "okay"; | |
261 | ||
262 | display-timings { | |
263 | native-mode = <&timing0>; | |
264 | timing0: hsd100pxn1 { | |
265 | clock-frequency = <65000000>; | |
266 | hactive = <1024>; | |
267 | vactive = <768>; | |
268 | hback-porch = <220>; | |
269 | hfront-porch = <40>; | |
270 | vback-porch = <21>; | |
271 | vfront-porch = <7>; | |
272 | hsync-len = <60>; | |
273 | vsync-len = <10>; | |
274 | }; | |
e3946fe8 | 275 | }; |
b5f37b76 TH |
276 | }; |
277 | }; | |
278 | ||
279 | &pcie { | |
280 | pinctrl-names = "default"; | |
281 | pinctrl-0 = <&pinctrl_pcie>; | |
282 | reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; | |
283 | status = "okay"; | |
284 | ||
285 | eth1: sky2@8 { /* MAC/PHY on bus 8 */ | |
286 | compatible = "marvell,sky2"; | |
287 | }; | |
288 | }; | |
289 | ||
290 | &pwm4 { | |
291 | pinctrl-names = "default"; | |
292 | pinctrl-0 = <&pinctrl_pwm4>; | |
293 | status = "okay"; | |
294 | }; | |
295 | ||
296 | &ssi1 { | |
b5f37b76 TH |
297 | status = "okay"; |
298 | }; | |
e3946fe8 | 299 | |
b5f37b76 TH |
300 | &uart1 { |
301 | pinctrl-names = "default"; | |
302 | pinctrl-0 = <&pinctrl_uart1>; | |
303 | status = "okay"; | |
304 | }; | |
305 | ||
306 | &uart2 { | |
307 | pinctrl-names = "default"; | |
308 | pinctrl-0 = <&pinctrl_uart2>; | |
309 | status = "okay"; | |
310 | }; | |
311 | ||
312 | &uart5 { | |
313 | pinctrl-names = "default"; | |
314 | pinctrl-0 = <&pinctrl_uart5>; | |
315 | status = "okay"; | |
316 | }; | |
317 | ||
318 | &usbotg { | |
319 | vbus-supply = <®_usb_otg_vbus>; | |
320 | pinctrl-names = "default"; | |
321 | pinctrl-0 = <&pinctrl_usbotg>; | |
322 | disable-over-current; | |
323 | status = "okay"; | |
324 | }; | |
325 | ||
326 | &usbh1 { | |
327 | vbus-supply = <®_usb_h1_vbus>; | |
328 | status = "okay"; | |
329 | }; | |
330 | ||
331 | &usdhc3 { | |
3ee12d80 | 332 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
b5f37b76 | 333 | pinctrl-0 = <&pinctrl_usdhc3>; |
3ee12d80 TH |
334 | pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
335 | pinctrl-2 = <&pinctrl_usdhc3_200mhz>; | |
89c1a8cf | 336 | cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; |
b5f37b76 | 337 | vmmc-supply = <®_3p3v>; |
3ee12d80 | 338 | no-1-8-v; /* firmware will remove if board revision supports */ |
b5f37b76 TH |
339 | status = "okay"; |
340 | }; | |
341 | ||
342 | &iomuxc { | |
343 | imx6qdl-gw53xx { | |
e3946fe8 TH |
344 | pinctrl_audmux: audmuxgrp { |
345 | fsl,pins = < | |
346 | MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 | |
347 | MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 | |
348 | MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 | |
349 | MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 | |
b5f37b76 | 350 | MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ |
e3946fe8 TH |
351 | >; |
352 | }; | |
353 | ||
354 | pinctrl_enet: enetgrp { | |
355 | fsl,pins = < | |
356 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | |
357 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | |
358 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | |
359 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | |
360 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | |
361 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | |
362 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | |
363 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | |
364 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | |
365 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | |
366 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | |
367 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | |
368 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | |
369 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | |
370 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | |
371 | MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 | |
372 | >; | |
373 | }; | |
374 | ||
375 | pinctrl_flexcan1: flexcan1grp { | |
376 | fsl,pins = < | |
73e005c1 TH |
377 | MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 |
378 | MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 | |
b5f37b76 TH |
379 | MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ |
380 | >; | |
381 | }; | |
382 | ||
383 | pinctrl_gpio_leds: gpioledsgrp { | |
384 | fsl,pins = < | |
385 | MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 | |
386 | MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 | |
387 | MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 | |
e3946fe8 TH |
388 | >; |
389 | }; | |
390 | ||
391 | pinctrl_gpmi_nand: gpminandgrp { | |
392 | fsl,pins = < | |
393 | MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | |
394 | MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | |
395 | MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | |
396 | MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | |
397 | MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | |
e3946fe8 TH |
398 | MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 |
399 | MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | |
400 | MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | |
401 | MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | |
402 | MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | |
403 | MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | |
404 | MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | |
405 | MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | |
406 | MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | |
407 | MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | |
408 | >; | |
409 | }; | |
410 | ||
411 | pinctrl_i2c1: i2c1grp { | |
412 | fsl,pins = < | |
413 | MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 | |
414 | MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | |
415 | >; | |
416 | }; | |
417 | ||
418 | pinctrl_i2c2: i2c2grp { | |
419 | fsl,pins = < | |
420 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 | |
421 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 | |
422 | >; | |
423 | }; | |
424 | ||
425 | pinctrl_i2c3: i2c3grp { | |
426 | fsl,pins = < | |
427 | MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 | |
428 | MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 | |
429 | >; | |
430 | }; | |
431 | ||
b5f37b76 TH |
432 | pinctrl_pcie: pciegrp { |
433 | fsl,pins = < | |
434 | MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ | |
435 | MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ | |
436 | >; | |
437 | }; | |
438 | ||
439 | pinctrl_pps: ppsgrp { | |
440 | fsl,pins = < | |
441 | MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 | |
442 | >; | |
443 | }; | |
444 | ||
b3253241 TH |
445 | pinctrl_pwm4: pwm4grp { |
446 | fsl,pins = < | |
447 | MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 | |
448 | >; | |
449 | }; | |
450 | ||
e3946fe8 TH |
451 | pinctrl_uart1: uart1grp { |
452 | fsl,pins = < | |
453 | MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 | |
454 | MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 | |
455 | >; | |
456 | }; | |
457 | ||
458 | pinctrl_uart2: uart2grp { | |
459 | fsl,pins = < | |
460 | MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 | |
461 | MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 | |
462 | >; | |
463 | }; | |
464 | ||
465 | pinctrl_uart5: uart5grp { | |
466 | fsl,pins = < | |
467 | MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 | |
468 | MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 | |
469 | >; | |
470 | }; | |
471 | ||
472 | pinctrl_usbotg: usbotggrp { | |
473 | fsl,pins = < | |
474 | MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 | |
b5f37b76 TH |
475 | MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ |
476 | MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ | |
e3946fe8 TH |
477 | >; |
478 | }; | |
479 | ||
480 | pinctrl_usdhc3: usdhc3grp { | |
481 | fsl,pins = < | |
482 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 | |
483 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 | |
484 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | |
485 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | |
486 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | |
487 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | |
3ee12d80 TH |
488 | MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ |
489 | MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 | |
490 | >; | |
491 | }; | |
492 | ||
493 | pinctrl_usdhc3_100mhz: usdhc3grp100mhz { | |
494 | fsl,pins = < | |
495 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 | |
496 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 | |
497 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 | |
498 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 | |
499 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 | |
500 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 | |
501 | MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ | |
502 | MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 | |
503 | >; | |
504 | }; | |
505 | ||
506 | pinctrl_usdhc3_200mhz: usdhc3grp200mhz { | |
507 | fsl,pins = < | |
508 | MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 | |
509 | MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 | |
510 | MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 | |
511 | MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 | |
512 | MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 | |
513 | MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 | |
514 | MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ | |
515 | MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 | |
e3946fe8 TH |
516 | >; |
517 | }; | |
518 | }; | |
519 | }; |