[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx6qdl-icore-rqs.dtsi

/*
 * Copyright (C) 2015 Amarula Solutions B.V.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License
 *     version 2 as published by the Free Software Foundation.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>

/ {
	memory@10000000 {
		reg = <0x10000000 0x80000000>;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "1P8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_2p5v: regulator-2p5v {
		compatible = "regulator-fixed";
		regulator-name = "2P5V";
		regulator-min-microvolt = <2500000>;
		regulator-max-microvolt = <2500000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_sd3_vmmc: regulator-sd3-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "P3V3_SD3_SWITCHED";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
		enable-active-high;
	};

	reg_sd4_vmmc: regulator-sd4-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "P3V3_SD4_SWITCHED";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_usb_h1_vbus: regulator-usb-h1-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb_h1_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_usb_otg_vbus: regulator-usb-otg-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb_otg_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
		regulator-always-on;
	};

	usb_hub: usb-hub {
		compatible = "smsc,usb3503a";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbhub>;
		reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
		clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>;
		clock-names = "refclk";
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "imx6qdl-icore-rqs-sgtl5000";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&dailink_master>;
		simple-audio-card,frame-master = <&dailink_master>;
		simple-audio-card,widgets =
			"Microphone", "Mic Jack",
			"Headphone", "Headphone Jack",
			"Line", "Line In Jack",
			"Speaker", "Line Out Jack",
			"Speaker", "Ext Spk";
		simple-audio-card,routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";

		simple-audio-card,cpu {
			sound-dai = <&ssi1>;
		};

		dailink_master: simple-audio-card,codec {
			sound-dai = <&sgtl5000>;
		};
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";

	audmux_ssi1 {
		fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
		fsl,port-config = <
			(IMX_AUDMUX_V2_PTCR_TFSDIR |
			IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
			IMX_AUDMUX_V2_PTCR_TCLKDIR |
			IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
			IMX_AUDMUX_V2_PTCR_SYN)
			IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
		>;
	};

	audmux_aud4 {
		fsl,audmux-port = <MX51_AUDMUX_PORT4>;
		fsl,port-config = <
			IMX_AUDMUX_V2_PTCR_SYN
			IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
		>;
	};
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can1>;
	xceiver-supply = <&reg_3p3v>;
	status = "okay";
};

&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can2>;
	xceiver-supply = <&reg_3p3v>;
	status = "okay";
};

&clks {
	assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
	assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-handle = <&eth_phy>;
	phy-mode = "rgmii";
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		eth_phy: ethernet-phy@0 {
			reg = <0x0>;
			rxc-skew-ps = <1140>;
			txc-skew-ps = <1140>;
			txen-skew-ps = <600>;
			rxdv-skew-ps = <240>;
			rxd0-skew-ps = <420>;
			rxd1-skew-ps = <600>;
			rxd2-skew-ps = <420>;
			rxd3-skew-ps = <240>;
			txd0-skew-ps = <60>;
			txd1-skew-ps = <60>;
			txd2-skew-ps = <60>;
			txd3-skew-ps = <240>;
		};
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	sgtl5000: codec@a {
		#sound-dai-cells = <0>;
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		clocks = <&clks IMX6QDL_CLK_CKO>;
		VDDA-supply = <&reg_2p5v>;
		VDDIO-supply = <&reg_3p3v>;
		VDDD-supply = <&reg_1p8v>;
	};
};

&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&ssi1 {
	fsl,mode = "i2s-slave";
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usbh1 {
	vbus-supply = <&reg_usb_h1_vbus>;
	disable-over-current;
	clocks = <&clks IMX6QDL_CLK_USBOH3>;
	status = "okay";
};

&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	disable-over-current;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	no-1-8-v;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	vmcc-supply = <&reg_sd3_vmmc>;
	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
	bus-witdh = <4>;
	no-1-8-v;
	status = "okay";
};

&usdhc4 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc4>;
	pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
	vmcc-supply = <&reg_sd4_vmmc>;
	bus-witdh = <8>;
	no-1-8-v;
	non-removable;
	status = "okay";
};

&iomuxc {
	pinctrl_audmux: audmux {
		fsl,pins = <
			MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
			MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x110b0
			MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
			MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
		>;
	};

	pinctrl_enet: enetgrp {
		fsl,pins = <
			MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
			MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b030
			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b030
			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b030
			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b030
			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b030
			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030
			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030
			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030
			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030
			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030
			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
		>;
	};

	pinctrl_can1: can1grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
		>;
	};

	pinctrl_can2: can2grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
			MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
			MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
			MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
			MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
		>;
	};

	pinctrl_pcie: pciegrp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f059	/* PCIe Reset */
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
		>;
	};

	pinctrl_usbhub: usbhubgrp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_6__GPIO1_IO06  0x1f059	/* HUB USB Reset */
		>;
	};

	pinctrl_usbotg: usbotggrp {
		fsl,pins = <
			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
			MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
			MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
			MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17070
			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10070
			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070
			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070
			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070
			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
			MX6QDL_PAD_GPIO_1__GPIO1_IO01  0x1f059	/* CD */
			MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1f059	/* PWR */
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
		fsl,pins = <
			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170B1
			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100B1
			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B1
			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B1
			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B1
			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B1
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
		fsl,pins = <
			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x170F9
			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x100F9
			MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
			MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
			MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
			MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
		>;
	};

	pinctrl_usdhc4: usdhc4grp {
		fsl,pins = <
			MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17070
			MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10070
			MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070
			MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070
			MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070
			MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070
			MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070
			MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070
			MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070
			MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070
		>;
	};

	pinctrl_usdhc4_100mhz: usdhc4grp_100mhz {
		fsl,pins = <
			MX6QDL_PAD_SD4_CMD__SD4_CMD    0x170B1
			MX6QDL_PAD_SD4_CLK__SD4_CLK    0x100B1
			MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1
			MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1
			MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1
			MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1
			MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1
			MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1
			MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1
			MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1
		>;
	};

	pinctrl_usdhc4_200mhz: usdhc4grp_200mhz {
		fsl,pins = <
			MX6QDL_PAD_SD4_CMD__SD4_CMD    0x170F9
			MX6QDL_PAD_SD4_CLK__SD4_CLK    0x100F9
			MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9
			MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9
			MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9
			MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9
			MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9
			MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9
			MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9
			MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9
		>;
	};
};
Commit	Line	Data
cc42603d MT	1	/*
	2	* Copyright (C) 2015 Amarula Solutions B.V.
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* version 2 as published by the Free Software Foundation.
	12	*
13283626	13	* This file is distributed in the hope that it will be useful,
cc42603d MT	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
13283626	18	* Or, alternatively,
cc42603d MT	19	*
	20	* b) Permission is hereby granted, free of charge, to any person
	21	* obtaining a copy of this software and associated documentation
	22	* files (the "Software"), to deal in the Software without
13283626	23	* restriction, including without limitation the rights to use,
cc42603d MT	24	* copy, modify, merge, publish, distribute, sublicense, and/or
	25	* sell copies of the Software, and to permit persons to whom the
	26	* Software is furnished to do so, subject to the following
	27	* conditions:
	28	*
	29	* The above copyright notice and this permission notice shall be
	30	* included in all copies or substantial portions of the Software.
	31	*
13283626	32	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
cc42603d MT	33	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	34	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	35	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
13283626	36	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
cc42603d MT	37	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	38	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	39	* OTHER DEALINGS IN THE SOFTWARE.
	40	*/
	41
	42	#include <dt-bindings/gpio/gpio.h>
	43	#include <dt-bindings/clock/imx6qdl-clock.h>
b5307edb	44	#include <dt-bindings/sound/fsl-imx-audmux.h>
cc42603d MT	45
cc42603d MT	46	/ {
ad00e080	47	memory@10000000 {
cc42603d MT	48	reg = <0x10000000 0x80000000>;
	49	};
	50
	51	reg_1p8v: regulator-1p8v {
	52	compatible = "regulator-fixed";
	53	regulator-name = "1P8V";
	54	regulator-min-microvolt = <1800000>;
	55	regulator-max-microvolt = <1800000>;
	56	regulator-boot-on;
	57	regulator-always-on;
	58	};
	59
	60	reg_2p5v: regulator-2p5v {
	61	compatible = "regulator-fixed";
	62	regulator-name = "2P5V";
	63	regulator-min-microvolt = <2500000>;
	64	regulator-max-microvolt = <2500000>;
	65	regulator-boot-on;
	66	regulator-always-on;
	67	};
	68
	69	reg_3p3v: regulator-3p3v {
	70	compatible = "regulator-fixed";
	71	regulator-name = "3P3V";
	72	regulator-min-microvolt = <3300000>;
	73	regulator-max-microvolt = <3300000>;
	74	regulator-boot-on;
	75	regulator-always-on;
	76	};
	77
	78	reg_sd3_vmmc: regulator-sd3-vmmc {
	79	compatible = "regulator-fixed";
	80	regulator-name = "P3V3_SD3_SWITCHED";
	81	regulator-min-microvolt = <3300000>;
	82	regulator-max-microvolt = <3300000>;
	83	gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
	84	enable-active-high;
	85	};
	86
	87	reg_sd4_vmmc: regulator-sd4-vmmc {
	88	compatible = "regulator-fixed";
	89	regulator-name = "P3V3_SD4_SWITCHED";
	90	regulator-min-microvolt = <3300000>;
	91	regulator-max-microvolt = <3300000>;
	92	regulator-boot-on;
	93	regulator-always-on;
	94	};
	95
	96	reg_usb_h1_vbus: regulator-usb-h1-vbus {
	97	compatible = "regulator-fixed";
	98	regulator-name = "usb_h1_vbus";
	99	regulator-min-microvolt = <5000000>;
	100	regulator-max-microvolt = <5000000>;
	101	regulator-boot-on;
	102	regulator-always-on;
	103	};
	104
	105	reg_usb_otg_vbus: regulator-usb-otg-vbus {
	106	compatible = "regulator-fixed";
	107	regulator-name = "usb_otg_vbus";
	108	regulator-min-microvolt = <5000000>;
	109	regulator-max-microvolt = <5000000>;
	110	regulator-boot-on;
	111	regulator-always-on;
112	};
113
114	usb_hub: usb-hub {
115	compatible = "smsc,usb3503a";
116	pinctrl-names = "default";
117	pinctrl-0 = <&pinctrl_usbhub>;
118	reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
119	clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>;
120	clock-names = "refclk";
121	};
4f0c2c75 JT	122
4f0c2c75 JT	123	sound {
b5307edb JT	124	compatible = "simple-audio-card";
	125	simple-audio-card,name = "imx6qdl-icore-rqs-sgtl5000";
	126	simple-audio-card,format = "i2s";
	127	simple-audio-card,bitclock-master = <&dailink_master>;
	128	simple-audio-card,frame-master = <&dailink_master>;
	129	simple-audio-card,widgets =
	130	"Microphone", "Mic Jack",
	131	"Headphone", "Headphone Jack",
	132	"Line", "Line In Jack",
	133	"Speaker", "Line Out Jack",
	134	"Speaker", "Ext Spk";
	135	simple-audio-card,routing =
4f0c2c75 JT	136	"MIC_IN", "Mic Jack",
	137	"Mic Jack", "Mic Bias",
	138	"Headphone Jack", "HP_OUT";
cc42603d	139
b5307edb JT	140	simple-audio-card,cpu {
	141	sound-dai = <&ssi1>;
	142	};
	143
	144	dailink_master: simple-audio-card,codec {
	145	sound-dai = <&sgtl5000>;
	146	};
	147	};
cc42603d MT	148	};
	149
	150	&audmux {
	151	pinctrl-names = "default";
	152	pinctrl-0 = <&pinctrl_audmux>;
	153	status = "okay";
b5307edb JT	154
	155	audmux_ssi1 {
	156	fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
	157	fsl,port-config = <
	158	(IMX_AUDMUX_V2_PTCR_TFSDIR \|
	159	IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) \|
	160	IMX_AUDMUX_V2_PTCR_TCLKDIR \|
	161	IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) \|
	162	IMX_AUDMUX_V2_PTCR_SYN)
	163	IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
	164	>;
	165	};
	166
	167	audmux_aud4 {
	168	fsl,audmux-port = <MX51_AUDMUX_PORT4>;
	169	fsl,port-config = <
	170	IMX_AUDMUX_V2_PTCR_SYN
	171	IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
	172	>;
	173	};
	174	};
	175
0ec7a7d3 JT	176	&can1 {
	177	pinctrl-names = "default";
	178	pinctrl-0 = <&pinctrl_can1>;
	179	xceiver-supply = <&reg_3p3v>;
	180	status = "okay";
	181	};
	182
	183	&can2 {
	184	pinctrl-names = "default";
	185	pinctrl-0 = <&pinctrl_can2>;
	186	xceiver-supply = <&reg_3p3v>;
	187	status = "okay";
	188	};
	189
b5307edb JT	190	&clks {
	191	assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
	192	assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
cc42603d MT	193	};
	194
	195	&fec {
	196	pinctrl-names = "default";
	197	pinctrl-0 = <&pinctrl_enet>;
	198	phy-handle = <&eth_phy>;
	199	phy-mode = "rgmii";
	200	status = "okay";
	201
	202	mdio {
2f953ee9 SS	203	#address-cells = <1>;
	204	#size-cells = <0>;
	205
	206	eth_phy: ethernet-phy@0 {
	207	reg = <0x0>;
cc42603d MT	208	rxc-skew-ps = <1140>;
	209	txc-skew-ps = <1140>;
	210	txen-skew-ps = <600>;
	211	rxdv-skew-ps = <240>;
	212	rxd0-skew-ps = <420>;
	213	rxd1-skew-ps = <600>;
	214	rxd2-skew-ps = <420>;
	215	rxd3-skew-ps = <240>;
	216	txd0-skew-ps = <60>;
	217	txd1-skew-ps = <60>;
	218	txd2-skew-ps = <60>;
	219	txd3-skew-ps = <240>;
	220	};
	221	};
	222	};
	223
	224	&i2c1 {
	225	clock-frequency = <100000>;
	226	pinctrl-names = "default";
	227	pinctrl-0 = <&pinctrl_i2c1>;
	228	status = "okay";
	229	};
	230
	231	&i2c2 {
	232	clock-frequency = <100000>;
	233	pinctrl-names = "default";
	234	pinctrl-0 = <&pinctrl_i2c2>;
	235	status = "okay";
	236	};
	237
	238	&i2c3 {
	239	pinctrl-names = "default";
	240	pinctrl-0 = <&pinctrl_i2c3>;
	241	status = "okay";
4f0c2c75 JT	242
4f0c2c75 JT	243	sgtl5000: codec@a {
b5307edb	244	#sound-dai-cells = <0>;
4f0c2c75 JT	245	compatible = "fsl,sgtl5000";
	246	reg = <0x0a>;
	247	clocks = <&clks IMX6QDL_CLK_CKO>;
	248	VDDA-supply = <&reg_2p5v>;
	249	VDDIO-supply = <&reg_3p3v>;
	250	VDDD-supply = <&reg_1p8v>;
	251	};
cc42603d MT	252	};
	253
	254	&pcie {
	255	pinctrl-names = "default";
	256	pinctrl-0 = <&pinctrl_pcie>;
	257	reset-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>;
	258	status = "okay";
	259	};
	260
	261	&ssi1 {
b5307edb	262	fsl,mode = "i2s-slave";
cc42603d MT	263	status = "okay";
	264	};
	265
	266	&uart4 {
	267	pinctrl-names = "default";
	268	pinctrl-0 = <&pinctrl_uart4>;
	269	status = "okay";
	270	};
	271
	272	&usbh1 {
	273	vbus-supply = <&reg_usb_h1_vbus>;
	274	disable-over-current;
	275	clocks = <&clks IMX6QDL_CLK_USBOH3>;
	276	status = "okay";
	277	};
	278
	279	&usbotg {
	280	vbus-supply = <&reg_usb_otg_vbus>;
	281	pinctrl-names = "default";
	282	pinctrl-0 = <&pinctrl_usbotg>;
	283	disable-over-current;
	284	status = "okay";
	285	};
	286
	287	&usdhc1 {
	288	pinctrl-names = "default";
	289	pinctrl-0 = <&pinctrl_usdhc1>;
	290	no-1-8-v;
	291	status = "okay";
	292	};
	293
	294	&usdhc3 {
	295	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	296	pinctrl-0 = <&pinctrl_usdhc3>;
	297	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	298	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	299	vmcc-supply = <&reg_sd3_vmmc>;
	300	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
ca38f9cb	301	bus-witdh = <4>;
cc42603d MT	302	no-1-8-v;
	303	status = "okay";
	304	};
	305
	306	&usdhc4 {
	307	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	308	pinctrl-0 = <&pinctrl_usdhc4>;
	309	pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
	310	pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
	311	vmcc-supply = <&reg_sd4_vmmc>;
ca38f9cb	312	bus-witdh = <8>;
cc42603d MT	313	no-1-8-v;
	314	non-removable;
	315	status = "okay";
	316	};
	317
	318	&iomuxc {
	319	pinctrl_audmux: audmux {
	320	fsl,pins = <
	321	MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
	322	MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x110b0
	323	MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
	324	MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
	325	>;
	326	};
	327
	328	pinctrl_enet: enetgrp {
	329	fsl,pins = <
	330	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	331	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
c007b3a6 UKK	332	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
	333	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
	334	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
	335	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
	336	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
	337	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
cc42603d	338	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
c007b3a6 UKK	339	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
	340	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
	341	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
	342	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
	343	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
	344	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
cc42603d MT	345	MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
	346	>;
	347	};
	348
0ec7a7d3 JT	349	pinctrl_can1: can1grp {
	350	fsl,pins = <
	351	MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
	352	MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
	353	>;
	354	};
	355
	356	pinctrl_can2: can2grp {
	357	fsl,pins = <
	358	MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
	359	MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
	360	>;
	361	};
	362
cc42603d MT	363	pinctrl_i2c1: i2c1grp {
	364	fsl,pins = <
	365	MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
	366	MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
	367	>;
	368	};
	369
	370	pinctrl_i2c2: i2c2grp {
	371	fsl,pins = <
	372	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
	373	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	374	>;
	375	};
	376
	377	pinctrl_i2c3: i2c3grp {
	378	fsl,pins = <
	379	MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
	380	MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
	381	MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
	382	>;
	383	};
	384
	385	pinctrl_pcie: pciegrp {
	386	fsl,pins = <
	387	MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f059 /* PCIe Reset */
	388	>;
	389	};
	390
	391	pinctrl_uart4: uart4grp {
	392	fsl,pins = <
	393	MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
	394	MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
	395	>;
	396	};
	397
	398	pinctrl_usbhub: usbhubgrp {
	399	fsl,pins = <
	400	MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1f059 /* HUB USB Reset */
	401	>;
	402	};
	403
	404	pinctrl_usbotg: usbotggrp {
	405	fsl,pins = <
	406	MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
	407	>;
	408	};
	409
	410	pinctrl_usdhc1: usdhc1grp {
	411	fsl,pins = <
	412	MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
	413	MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
	414	MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
	415	MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
	416	MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
	417	MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
	418	>;
	419	};
	420
	421	pinctrl_usdhc3: usdhc3grp {
	422	fsl,pins = <
	423	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070
	424	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070
	425	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070
	426	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070
427	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070
428	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
429	MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1f059 /* CD */
430	MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f059 /* PWR */
431	>;
432	};
433
434	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
435	fsl,pins = <
436	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B1
437	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B1
438	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B1
439	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B1
440	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B1
441	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B1
442	>;
443	};
444
445	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
446	fsl,pins = <
447	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
448	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
449	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
450	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
451	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
452	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
453	>;
454	};
455
456	pinctrl_usdhc4: usdhc4grp {
457	fsl,pins = <
458	MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17070
459	MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10070
460	MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070
461	MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070
462	MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070
463	MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070
464	MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070
465	MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070
466	MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070
467	MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070
468	>;
469	};
470
471	pinctrl_usdhc4_100mhz: usdhc4grp_100mhz {
472	fsl,pins = <
473	MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170B1
474	MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100B1
475	MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1
476	MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1
477	MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1
478	MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1
479	MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1
480	MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1
481	MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1
482	MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1
483	>;
484	};
485
486	pinctrl_usdhc4_200mhz: usdhc4grp_200mhz {
487	fsl,pins = <
488	MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170F9
489	MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100F9
490	MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9
491	MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9
492	MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9
493	MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9
494	MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9
495	MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9
496	MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9
497	MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9
498	>;
499	};
500	};