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Merge branches 'for-5.1/upstream-fixes', 'for-5.2/core', 'for-5.2/ish', 'for-5.2...
[mirror_ubuntu-kernels.git] / arch / arm / boot / dts / imx6qdl-phytec-pfla02.dtsi
CommitLineData
4fe69a93
PZ		 1/*
2 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
26888190
PZ		 12#include <dt-bindings/gpio/gpio.h>
13
4fe69a93 14/ {
a452afa3 15 model = "Phytec phyFLEX-i.MX6 Quad";
4fe69a93
PZ		 16 compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
17
ad00e080 18 memory@10000000 {
404c0c93 19 device_type = "memory";
4fe69a93
PZ		 20 reg = <0x10000000 0x80000000>;
21 };
22
23 regulators {
24 compatible = "simple-bus";
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 reg_usb_otg_vbus: regulator@0 {
29 compatible = "regulator-fixed";
30 reg = <0>;
31 regulator-name = "usb_otg_vbus";
32 regulator-min-microvolt = <5000000>;
33 regulator-max-microvolt = <5000000>;
34 gpio = <&gpio4 15 0>;
7f8d49dc 35 enable-active-high;
4fe69a93
PZ		 36 };
37
38 reg_usb_h1_vbus: regulator@1 {
39 compatible = "regulator-fixed";
40 reg = <1>;
41 regulator-name = "usb_h1_vbus";
42 regulator-min-microvolt = <5000000>;
43 regulator-max-microvolt = <5000000>;
44 gpio = <&gpio1 0 0>;
7f8d49dc 45 enable-active-high;
4fe69a93
PZ		 46 };
47 };
94a1bbf8
PZ		 48
49 gpio_leds: leds {
50 compatible = "gpio-leds";
51
52 green {
53 label = "phyflex:green";
54 gpios = <&gpio1 30 0>;
55 };
56
57 red {
58 label = "phyflex:red";
59 gpios = <&gpio2 31 0>;
60 };
61 };
4fe69a93
PZ		 62};
63
8fa91c8e
DL		 64&audmux {
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_audmux>;
67 status = "disabled";
68};
69
1b61feea
CH		 70&can1 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_flexcan1>;
73 status = "disabled";
74};
75
4fe69a93
PZ		 76&ecspi3 {
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_ecspi3>;
79 status = "okay";
4fe69a93
PZ		 80 cs-gpios = <&gpio4 24 0>;
81
82 flash@0 {
79826ac6 83 compatible = "m25p80", "jedec,spi-nor";
4fe69a93
PZ		 84 spi-max-frequency = <20000000>;
85 reg = <0>;
86 };
87};
88
35008832
CH		 89&fec {
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_enet>;
8de81c89 92 phy-handle = <&ethphy>;
35008832 93 phy-mode = "rgmii";
032f85c9 94 phy-reset-duration = <10>; /* in msecs */
35008832
CH		 95 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
96 phy-supply = <&vdd_eth_io_reg>;
97 status = "disabled";
8de81c89
PZ		 98
99 fec_mdio: mdio {
100 #address-cells = <1>;
101 #size-cells = <0>;
102
103 ethphy: ethernet-phy@0 {
104 compatible = "ethernet-phy-ieee802.3-c22";
105 reg = <0>;
106 txc-skew-ps = <1680>;
107 rxc-skew-ps = <1860>;
108 };
109 };
35008832
CH		 110};
111
112&gpmi {
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_gpmi_nand>;
115 nand-on-flash-bbt;
0019d182 116 status = "okay";
35008832
CH		 117};
118
4fe69a93
PZ		 119&i2c1 {
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_i2c1>;
122 status = "okay";
123
124 eeprom@50 {
125 compatible = "atmel,24c32";
126 reg = <0x50>;
127 };
128
129 pmic@58 {
bd597f47 130 compatible = "dlg,da9063";
4fe69a93 131 reg = <0x58>;
c082fd42 132 interrupt-parent = <&gpio2>;
8bf48e74 133 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
bffe0d85 134 interrupt-controller;
4fe69a93
PZ		 135
136 regulators {
137 vddcore_reg: bcore1 {
138 regulator-min-microvolt = <730000>;
139 regulator-max-microvolt = <1380000>;
140 regulator-always-on;
141 };
142
143 vddsoc_reg: bcore2 {
144 regulator-min-microvolt = <730000>;
145 regulator-max-microvolt = <1380000>;
146 regulator-always-on;
147 };
148
149 vdd_ddr3_reg: bpro {
150 regulator-min-microvolt = <1500000>;
151 regulator-max-microvolt = <1500000>;
152 regulator-always-on;
153 };
154
155 vdd_3v3_reg: bperi {
156 regulator-min-microvolt = <3300000>;
157 regulator-max-microvolt = <3300000>;
158 regulator-always-on;
159 };
160
161 vdd_buckmem_reg: bmem {
162 regulator-min-microvolt = <3300000>;
163 regulator-max-microvolt = <3300000>;
164 regulator-always-on;
165 };
166
167 vdd_eth_reg: bio {
168 regulator-min-microvolt = <1200000>;
169 regulator-max-microvolt = <1200000>;
170 regulator-always-on;
171 };
172
173 vdd_eth_io_reg: ldo4 {
174 regulator-min-microvolt = <2500000>;
175 regulator-max-microvolt = <2500000>;
176 regulator-always-on;
177 };
178
179 vdd_mx6_snvs_reg: ldo5 {
180 regulator-min-microvolt = <3000000>;
181 regulator-max-microvolt = <3000000>;
182 regulator-always-on;
183 };
184
185 vdd_3v3_pmic_io_reg: ldo6 {
186 regulator-min-microvolt = <3300000>;
187 regulator-max-microvolt = <3300000>;
188 regulator-always-on;
189 };
190
191 vdd_sd0_reg: ldo9 {
192 regulator-min-microvolt = <3300000>;
193 regulator-max-microvolt = <3300000>;
194 };
195
196 vdd_sd1_reg: ldo10 {
197 regulator-min-microvolt = <3300000>;
198 regulator-max-microvolt = <3300000>;
199 };
200
201 vdd_mx6_high_reg: ldo11 {
202 regulator-min-microvolt = <3000000>;
203 regulator-max-microvolt = <3000000>;
204 regulator-always-on;
205 };
206 };
207 };
208};
209
d76fab80
DL		 210&i2c2 {
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_i2c2>;
213 clock-frequency = <100000>;
214};
215
216&i2c3 {
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_i2c3>;
219 clock-frequency = <100000>;
220};
221
4fe69a93
PZ		 222&iomuxc {
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_hog>;
225
226 imx6q-phytec-pfla02 {
227 pinctrl_hog: hoggrp {
228 fsl,pins = <
229 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
230 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
c082fd42 231 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* PMIC interrupt */
94a1bbf8
PZ		 232 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
233 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
4fe69a93
PZ		 234 >;
235 };
236
237 pinctrl_ecspi3: ecspi3grp {
238 fsl,pins = <
239 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
240 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
241 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
242 >;
243 };
244
245 pinctrl_enet: enetgrp {
246 fsl,pins = <
247 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
248 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
c007b3a6
UKK		 249 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
250 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
251 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
252 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
253 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
254 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
4fe69a93 255 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
c007b3a6
UKK		 256 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
257 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
258 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
259 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
260 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
261 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
4fe69a93
PZ		 262 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
263 >;
264 };
265
1b61feea
CH		 266 pinctrl_flexcan1: flexcan1grp {
267 fsl,pins = <
268 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
269 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
270 >;
271 };
272
4fe69a93
PZ		 273 pinctrl_gpmi_nand: gpminandgrp {
274 fsl,pins = <
275 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
276 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
277 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
278 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
279 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
280 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
281 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
282 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
283 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
284 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
285 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
286 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
287 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
288 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
289 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
290 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
291 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
292 >;
293 };
294
295 pinctrl_i2c1: i2c1grp {
296 fsl,pins = <
297 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
298 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
299 >;
300 };
301
d76fab80
DL		 302 pinctrl_i2c2: i2c2grp {
303 fsl,pins = <
304 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
305 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
306 >;
307 };
308
309 pinctrl_i2c3: i2c3grp {
310 fsl,pins = <
311 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
312 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
313 >;
314 };
315
9924546b
CH		 316 pinctrl_pcie: pciegrp {
317 fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>;
318 };
319
14e2833d
PZ		 320 pinctrl_uart3: uart3grp {
321 fsl,pins = <
322 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
323 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
324 MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1
325 MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
326 >;
327 };
328
4fe69a93
PZ		 329 pinctrl_uart4: uart4grp {
330 fsl,pins = <
331 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
332 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
333 >;
334 };
335
336 pinctrl_usbh1: usbh1grp {
337 fsl,pins = <
338 MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000
339 >;
340 };
341
342 pinctrl_usbotg: usbotggrp {
343 fsl,pins = <
344 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
345 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
346 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
347 >;
348 };
349
350 pinctrl_usdhc2: usdhc2grp {
351 fsl,pins = <
352 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
353 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
354 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
355 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
356 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
357 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
358 >;
359 };
360
361 pinctrl_usdhc3: usdhc3grp {
362 fsl,pins = <
363 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
364 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
365 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
366 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
367 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
368 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
369 >;
370 };
371
372 pinctrl_usdhc3_cdwp: usdhc3cdwp {
373 fsl,pins = <
374 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
375 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
376 >;
377 };
8fa91c8e
DL		 378
379 pinctrl_audmux: audmuxgrp {
380 fsl,pins = <
381 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
382 MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0
383 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
384 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
385 >;
386 };
4fe69a93
PZ		 387 };
388};
389
9924546b 390&pcie {
a452afa3 391 pinctrl-names = "default";
9924546b 392 pinctrl-0 = <&pinctrl_pcie>;
cc20028f 393 reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
9924546b
CH		 394 status = "disabled";
395};
396
942526c3
SH		 397&reg_arm {
398 vin-supply = <&vddcore_reg>;
399};
400
401&reg_pu {
402 vin-supply = <&vddsoc_reg>;
403};
404
405&reg_soc {
406 vin-supply = <&vddsoc_reg>;
407};
408
14e2833d
PZ		 409&uart3 {
410 pinctrl-names = "default";
411 pinctrl-0 = <&pinctrl_uart3>;
412 status = "disabled";
413};
414
4fe69a93
PZ		 415&uart4 {
416 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_uart4>;
418 status = "disabled";
419};
420
421&usbh1 {
422 vbus-supply = <&reg_usb_h1_vbus>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&pinctrl_usbh1>;
425 status = "disabled";
426};
427
428&usbotg {
429 vbus-supply = <&reg_usb_otg_vbus>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_usbotg>;
432 disable-over-current;
433 status = "disabled";
434};
435
436&usdhc2 {
437 pinctrl-names = "default";
438 pinctrl-0 = <&pinctrl_usdhc2>;
89c1a8cf
DA		 439 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
440 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
4fe69a93
PZ		 441 status = "disabled";
442};
443
444&usdhc3 {
bf5393c5
JT		 445 pinctrl-names = "default";
446 pinctrl-0 = <&pinctrl_usdhc3
4fe69a93 447 &pinctrl_usdhc3_cdwp>;
89c1a8cf
DA		 448 cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
449 wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
bf5393c5 450 status = "disabled";
4fe69a93 451};
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