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ARM: dts: pfla02: Add GPIO LEDs
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / boot / dts / imx6qdl-phytec-pfla02.dtsi
CommitLineData
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PZ		 1/*
2 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/ {
13 model = "Phytec phyFLEX-i.MX6 Ouad";
14 compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
15
16 memory {
17 reg = <0x10000000 0x80000000>;
18 };
19
20 regulators {
21 compatible = "simple-bus";
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 reg_usb_otg_vbus: regulator@0 {
26 compatible = "regulator-fixed";
27 reg = <0>;
28 regulator-name = "usb_otg_vbus";
29 regulator-min-microvolt = <5000000>;
30 regulator-max-microvolt = <5000000>;
31 gpio = <&gpio4 15 0>;
32 };
33
34 reg_usb_h1_vbus: regulator@1 {
35 compatible = "regulator-fixed";
36 reg = <1>;
37 regulator-name = "usb_h1_vbus";
38 regulator-min-microvolt = <5000000>;
39 regulator-max-microvolt = <5000000>;
40 gpio = <&gpio1 0 0>;
41 };
42 };
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PZ		 43
44 gpio_leds: leds {
45 compatible = "gpio-leds";
46
47 green {
48 label = "phyflex:green";
49 gpios = <&gpio1 30 0>;
50 };
51
52 red {
53 label = "phyflex:red";
54 gpios = <&gpio2 31 0>;
55 };
56 };
4fe69a93
PZ		 57};
58
59&ecspi3 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_ecspi3>;
62 status = "okay";
63 fsl,spi-num-chipselects = <1>;
64 cs-gpios = <&gpio4 24 0>;
65
66 flash@0 {
67 compatible = "m25p80";
68 spi-max-frequency = <20000000>;
69 reg = <0>;
70 };
71};
72
73&i2c1 {
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_i2c1>;
76 status = "okay";
77
78 eeprom@50 {
79 compatible = "atmel,24c32";
80 reg = <0x50>;
81 };
82
83 pmic@58 {
84 compatible = "dialog,da9063";
85 reg = <0x58>;
86 interrupt-parent = <&gpio4>;
87 interrupts = <17 0x8>; /* active-low GPIO4_17 */
88
89 regulators {
90 vddcore_reg: bcore1 {
91 regulator-min-microvolt = <730000>;
92 regulator-max-microvolt = <1380000>;
93 regulator-always-on;
94 };
95
96 vddsoc_reg: bcore2 {
97 regulator-min-microvolt = <730000>;
98 regulator-max-microvolt = <1380000>;
99 regulator-always-on;
100 };
101
102 vdd_ddr3_reg: bpro {
103 regulator-min-microvolt = <1500000>;
104 regulator-max-microvolt = <1500000>;
105 regulator-always-on;
106 };
107
108 vdd_3v3_reg: bperi {
109 regulator-min-microvolt = <3300000>;
110 regulator-max-microvolt = <3300000>;
111 regulator-always-on;
112 };
113
114 vdd_buckmem_reg: bmem {
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 regulator-always-on;
118 };
119
120 vdd_eth_reg: bio {
121 regulator-min-microvolt = <1200000>;
122 regulator-max-microvolt = <1200000>;
123 regulator-always-on;
124 };
125
126 vdd_eth_io_reg: ldo4 {
127 regulator-min-microvolt = <2500000>;
128 regulator-max-microvolt = <2500000>;
129 regulator-always-on;
130 };
131
132 vdd_mx6_snvs_reg: ldo5 {
133 regulator-min-microvolt = <3000000>;
134 regulator-max-microvolt = <3000000>;
135 regulator-always-on;
136 };
137
138 vdd_3v3_pmic_io_reg: ldo6 {
139 regulator-min-microvolt = <3300000>;
140 regulator-max-microvolt = <3300000>;
141 regulator-always-on;
142 };
143
144 vdd_sd0_reg: ldo9 {
145 regulator-min-microvolt = <3300000>;
146 regulator-max-microvolt = <3300000>;
147 };
148
149 vdd_sd1_reg: ldo10 {
150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>;
152 };
153
154 vdd_mx6_high_reg: ldo11 {
155 regulator-min-microvolt = <3000000>;
156 regulator-max-microvolt = <3000000>;
157 regulator-always-on;
158 };
159 };
160 };
161};
162
163&iomuxc {
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_hog>;
166
167 imx6q-phytec-pfla02 {
168 pinctrl_hog: hoggrp {
169 fsl,pins = <
170 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
171 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
172 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */
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PZ		 173 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
174 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
4fe69a93
PZ		 175 >;
176 };
177
178 pinctrl_ecspi3: ecspi3grp {
179 fsl,pins = <
180 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
181 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
182 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
183 >;
184 };
185
186 pinctrl_enet: enetgrp {
187 fsl,pins = <
188 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
189 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
190 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
191 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
192 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
193 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
194 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
195 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
196 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
197 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
198 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
199 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
200 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
201 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
202 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
203 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
204 >;
205 };
206
207 pinctrl_gpmi_nand: gpminandgrp {
208 fsl,pins = <
209 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
210 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
211 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
212 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
213 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
214 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
215 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
216 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
217 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
218 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
219 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
220 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
221 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
222 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
223 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
224 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
225 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
226 >;
227 };
228
229 pinctrl_i2c1: i2c1grp {
230 fsl,pins = <
231 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
232 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
233 >;
234 };
235
236 pinctrl_uart4: uart4grp {
237 fsl,pins = <
238 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
239 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
240 >;
241 };
242
243 pinctrl_usbh1: usbh1grp {
244 fsl,pins = <
245 MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000
246 >;
247 };
248
249 pinctrl_usbotg: usbotggrp {
250 fsl,pins = <
251 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
252 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
253 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
254 >;
255 };
256
257 pinctrl_usdhc2: usdhc2grp {
258 fsl,pins = <
259 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
260 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
261 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
262 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
263 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
264 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
265 >;
266 };
267
268 pinctrl_usdhc3: usdhc3grp {
269 fsl,pins = <
270 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
271 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
272 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
273 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
274 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
275 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
276 >;
277 };
278
279 pinctrl_usdhc3_cdwp: usdhc3cdwp {
280 fsl,pins = <
281 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
282 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
283 >;
284 };
285 };
286};
287
288&fec {
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_enet>;
291 phy-mode = "rgmii";
292 phy-reset-gpios = <&gpio3 23 0>;
293 status = "disabled";
294};
295
296&gpmi {
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_gpmi_nand>;
299 nand-on-flash-bbt;
300 status = "disabled";
301};
302
303&uart4 {
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_uart4>;
306 status = "disabled";
307};
308
309&usbh1 {
310 vbus-supply = <&reg_usb_h1_vbus>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_usbh1>;
313 status = "disabled";
314};
315
316&usbotg {
317 vbus-supply = <&reg_usb_otg_vbus>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_usbotg>;
320 disable-over-current;
321 status = "disabled";
322};
323
324&usdhc2 {
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_usdhc2>;
327 cd-gpios = <&gpio1 4 0>;
328 wp-gpios = <&gpio1 2 0>;
329 status = "disabled";
330};
331
332&usdhc3 {
333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_usdhc3
335 &pinctrl_usdhc3_cdwp>;
336 cd-gpios = <&gpio1 27 0>;
337 wp-gpios = <&gpio1 29 0>;
338 status = "disabled";
339};
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