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BCM270X: Enable the DSI panel node in the VC4 overlay.
[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / imx6qdl-tx6.dtsi
CommitLineData
c8787bae 1/*
e06dd630 2 * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
c8787bae 3 *
e06dd630
LW		 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
c8787bae 8 *
e06dd630
LW		 9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
c8787bae
LW		 40 */
41
42#include <dt-bindings/gpio/gpio.h>
43#include <dt-bindings/input/input.h>
09bb4319 44#include <dt-bindings/interrupt-controller/irq.h>
c8787bae
LW		 45#include <dt-bindings/pwm/pwm.h>
46
47/ {
48 aliases {
49 can0 = &can2;
50 can1 = &can1;
51 ethernet0 = &fec;
52 lcdif_23bit_pins_a = &pinctrl_disp0_1;
53 lcdif_24bit_pins_a = &pinctrl_disp0_2;
54 pwm0 = &pwm1;
55 pwm1 = &pwm2;
56 reg_can_xcvr = &reg_can_xcvr;
57 stk5led = &user_led;
58 usbotg = &usbotg;
59 sdhc0 = &usdhc1;
60 sdhc1 = &usdhc2;
61 };
62
63 memory {
64 reg = <0 0>; /* will be filled by U-Boot */
65 };
66
67 clocks {
68 #address-cells = <1>;
69 #size-cells = <0>;
abe3e2b9 70
c8787bae
LW		 71 mclk: clock@0 {
72 compatible = "fixed-clock";
73 reg = <0>;
74 #clock-cells = <0>;
43ffc19e 75 clock-frequency = <26000000>;
c8787bae
LW		 76 };
77 };
78
79 gpio-keys {
80 compatible = "gpio-keys";
81
82 power {
83 label = "Power Button";
84 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
85 linux,code = <KEY_POWER>;
26cefdd1 86 wakeup-source;
c8787bae
LW		 87 };
88 };
89
90 leds {
91 compatible = "gpio-leds";
92
93 user_led: user {
94 label = "Heartbeat";
96de0367
LW		 95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_user_led>;
c8787bae
LW		 97 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
98 linux,default-trigger = "heartbeat";
99 };
100 };
101
7281795f
LW		 102 reg_3v3_etn: regulator-3v3-etn {
103 compatible = "regulator-fixed";
104 regulator-name = "3V3_ETN";
105 regulator-min-microvolt = <3300000>;
106 regulator-max-microvolt = <3300000>;
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_etnphy_power>;
109 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
110 enable-active-high;
111 };
c8787bae 112
7281795f
LW		 113 reg_2v5: regulator-2v5 {
114 compatible = "regulator-fixed";
115 regulator-name = "2V5";
116 regulator-min-microvolt = <2500000>;
117 regulator-max-microvolt = <2500000>;
118 regulator-always-on;
119 };
c8787bae 120
7281795f
LW		 121 reg_3v3: regulator-3v3 {
122 compatible = "regulator-fixed";
123 regulator-name = "3V3";
124 regulator-min-microvolt = <3300000>;
125 regulator-max-microvolt = <3300000>;
126 regulator-always-on;
127 };
c8787bae 128
7281795f
LW		 129 reg_can_xcvr: regulator-can-xcvr {
130 compatible = "regulator-fixed";
131 regulator-name = "CAN XCVR";
132 regulator-min-microvolt = <3300000>;
133 regulator-max-microvolt = <3300000>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
136 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
137 enable-active-low;
138 };
c8787bae 139
7281795f
LW		 140 reg_lcd0_pwr: regulator-lcd0-pwr {
141 compatible = "regulator-fixed";
142 regulator-name = "LCD0 POWER";
143 regulator-min-microvolt = <3300000>;
144 regulator-max-microvolt = <3300000>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_lcd0_pwr>;
147 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
148 enable-active-high;
149 regulator-boot-on;
150 };
c8787bae 151
7281795f
LW		 152 reg_lcd1_pwr: regulator-lcd1-pwr {
153 compatible = "regulator-fixed";
154 regulator-name = "LCD1 POWER";
155 regulator-min-microvolt = <3300000>;
156 regulator-max-microvolt = <3300000>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_lcd1_pwr>;
159 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
160 enable-active-high;
161 regulator-boot-on;
162 };
c8787bae 163
7281795f
LW		 164 reg_usbh1_vbus: regulator-usbh1-vbus {
165 compatible = "regulator-fixed";
166 regulator-name = "usbh1_vbus";
167 regulator-min-microvolt = <5000000>;
168 regulator-max-microvolt = <5000000>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_usbh1_vbus>;
171 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
172 enable-active-high;
173 };
c8787bae 174
7281795f
LW		 175 reg_usbotg_vbus: regulator-usbotg-vbus {
176 compatible = "regulator-fixed";
177 regulator-name = "usbotg_vbus";
178 regulator-min-microvolt = <5000000>;
179 regulator-max-microvolt = <5000000>;
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_usbotg_vbus>;
182 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
183 enable-active-high;
c8787bae
LW		 184 };
185
186 sound {
187 compatible = "karo,imx6qdl-tx6qdl-sgtl5000",
188 "fsl,imx-audio-sgtl5000";
189 model = "sgtl5000-audio";
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_audmux>;
192 ssi-controller = <&ssi1>;
193 audio-codec = <&sgtl5000>;
194 audio-routing =
195 "MIC_IN", "Mic Jack",
196 "Mic Jack", "Mic Bias",
197 "Headphone Jack", "HP_OUT";
198 mux-int-port = <1>;
199 mux-ext-port = <5>;
200 };
201};
202
203&audmux {
204 status = "okay";
205};
206
207&can1 {
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_flexcan1>;
210 xceiver-supply = <&reg_can_xcvr>;
211 status = "okay";
212};
213
214&can2 {
215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_flexcan2>;
217 xceiver-supply = <&reg_can_xcvr>;
218 status = "okay";
219};
220
221&ecspi1 {
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_ecspi1>;
224 fsl,spi-num-chipselects = <2>;
225 cs-gpios = <
226 &gpio2 30 GPIO_ACTIVE_HIGH
227 &gpio3 19 GPIO_ACTIVE_HIGH
228 >;
0fd646d0 229 status = "disabled";
c8787bae
LW		 230
231 spidev0: spi@0 {
232 compatible = "spidev";
233 reg = <0>;
234 spi-max-frequency = <54000000>;
235 };
236
237 spidev1: spi@1 {
238 compatible = "spidev";
239 reg = <1>;
240 spi-max-frequency = <54000000>;
241 };
242};
243
244&fec {
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_enet>;
76591910
LW		 247 clocks = <&clks IMX6QDL_CLK_ENET>,
248 <&clks IMX6QDL_CLK_ENET>,
249 <&clks IMX6QDL_CLK_ENET_REF>,
250 <&clks IMX6QDL_CLK_ENET_REF>;
251 clock-names = "ipg", "ahb", "ptp", "enet_out";
c8787bae
LW		 252 phy-mode = "rmii";
253 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
9cbda37b 254 phy-handle = <&etnphy>;
c8787bae
LW		 255 phy-supply = <&reg_3v3_etn>;
256 status = "okay";
9cbda37b
LW		 257
258 mdio {
259 #address-cells = <1>;
260 #size-cells = <0>;
261
262 etnphy: ethernet-phy@0 {
263 compatible = "ethernet-phy-ieee802.3-c22";
264 reg = <0>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_enet_mdio>;
267 interrupts-extended = <&gpio7 1 IRQ_TYPE_EDGE_FALLING>;
268 };
269 };
c8787bae
LW		 270};
271
272&gpmi {
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_gpmi_nand>;
275 nand-on-flash-bbt;
276 fsl,no-blockmark-swap;
277 status = "okay";
278};
279
280&i2c1 {
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_i2c1>;
283 clock-frequency = <400000>;
284 status = "okay";
285
286 ds1339: rtc@68 {
287 compatible = "dallas,ds1339";
288 reg = <0x68>;
289 };
290};
291
292&i2c3 {
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_i2c3>;
295 clock-frequency = <400000>;
296 status = "okay";
297
298 sgtl5000: sgtl5000@0a {
299 compatible = "fsl,sgtl5000";
300 reg = <0x0a>;
301 VDDA-supply = <&reg_2v5>;
302 VDDIO-supply = <&reg_3v3>;
303 clocks = <&mclk>;
304 };
305
306 polytouch: edt-ft5x06@38 {
307 compatible = "edt,edt-ft5x06";
308 reg = <0x38>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_edt_ft5x06>;
311 interrupt-parent = <&gpio6>;
09bb4319 312 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
c8787bae
LW		 313 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
314 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
26cefdd1 315 wakeup-source;
c8787bae
LW		 316 };
317
318 touchscreen: tsc2007@48 {
319 compatible = "ti,tsc2007";
320 reg = <0x48>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_tsc2007>;
323 interrupt-parent = <&gpio3>;
324 interrupts = <26 0>;
325 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
326 ti,x-plate-ohms = <660>;
26cefdd1 327 wakeup-source;
c8787bae
LW		 328 };
329};
330
331&iomuxc {
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_hog>;
334
c4aca663
LW		 335 pinctrl_hog: hoggrp {
336 fsl,pins = <
c4aca663
LW		 337 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
338 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
339 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
340 >;
341 };
c8787bae 342
c4aca663
LW		 343 pinctrl_audmux: audmuxgrp {
344 fsl,pins = <
345 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */
346 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */
347 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */
348 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */
349 >;
350 };
c8787bae 351
c4aca663
LW		 352 pinctrl_disp0_1: disp0grp-1 {
353 fsl,pins = <
354 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
355 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
356 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
357 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
358 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
359 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
360 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
361 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
362 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
363 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
364 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
365 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
366 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
367 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
368 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
369 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
370 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
371 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
372 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
373 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
374 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
375 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
376 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
377 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
378 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
379 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
380 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
381 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
382 >;
383 };
c8787bae 384
c4aca663
LW		 385 pinctrl_disp0_2: disp0grp-2 {
386 fsl,pins = <
387 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
388 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
389 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
390 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
391 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
392 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
393 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
394 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
395 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
396 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
397 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
398 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
399 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
400 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
401 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
402 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
403 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
404 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
405 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
406 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
407 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
408 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
409 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
410 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
411 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
412 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
413 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
414 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
415 >;
416 };
c8787bae 417
c4aca663
LW		 418 pinctrl_ecspi1: ecspi1grp {
419 fsl,pins = <
420 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0
421 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0
422 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0
423 MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
424 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */
425 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
426 >;
427 };
c8787bae 428
c4aca663
LW		 429 pinctrl_edt_ft5x06: edt-ft5x06grp {
430 fsl,pins = <
431 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
05c183e4
JT		 432 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
433 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
c4aca663
LW		 434 >;
435 };
c8787bae 436
c4aca663
LW		 437 pinctrl_enet: enetgrp {
438 fsl,pins = <
439 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
440 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
441 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
442 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
443 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
444 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
445 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
446 >;
447 };
c8787bae 448
c4aca663
LW		 449 pinctrl_enet_mdio: enet-mdiogrp {
450 fsl,pins = <
451 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
452 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
453 >;
454 };
c8787bae 455
c4aca663
LW		 456 pinctrl_etnphy_power: etnphy-pwrgrp {
457 fsl,pins = <
458 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
459 >;
460 };
c8787bae 461
c4aca663
LW		 462 pinctrl_flexcan1: flexcan1grp {
463 fsl,pins = <
464 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
465 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
466 >;
467 };
c8787bae 468
c4aca663
LW		 469 pinctrl_flexcan2: flexcan2grp {
470 fsl,pins = <
471 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
472 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
473 >;
474 };
c8787bae 475
c4aca663
LW		 476 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
477 fsl,pins = <
478 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
479 >;
480 };
c8787bae 481
c4aca663
LW		 482 pinctrl_gpmi_nand: gpminandgrp {
483 fsl,pins = <
05c183e4
JT		 484 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
485 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
486 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
c4aca663 487 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
05c183e4
JT		 488 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
489 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
490 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
491 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
492 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
493 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
494 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
495 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
496 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
497 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
498 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
c4aca663
LW		 499 >;
500 };
c8787bae 501
c4aca663
LW		 502 pinctrl_i2c1: i2c1grp {
503 fsl,pins = <
504 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
505 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
506 >;
507 };
c8787bae 508
c4aca663
LW		 509 pinctrl_i2c3: i2c3grp {
510 fsl,pins = <
511 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
512 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
513 >;
514 };
c8787bae 515
c4aca663
LW		 516 pinctrl_kpp: kppgrp {
517 fsl,pins = <
518 MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
519 MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
520 MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
521 MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
522 MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
523 MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
524 MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
525 MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
526 >;
527 };
c8787bae 528
c4aca663
LW		 529 pinctrl_lcd0_pwr: lcd0-pwrgrp {
530 fsl,pins = <
531 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
532 >;
533 };
c8787bae 534
c4aca663
LW		 535 pinctrl_lcd1_pwr: lcd-pwrgrp {
536 fsl,pins = <
537 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
538 >;
539 };
c8787bae 540
c4aca663
LW		 541 pinctrl_pwm1: pwm1grp {
542 fsl,pins = <
543 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
544 >;
545 };
c8787bae 546
c4aca663
LW		 547 pinctrl_pwm2: pwm2grp {
548 fsl,pins = <
549 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
550 >;
551 };
c8787bae 552
c4aca663
LW		 553 pinctrl_tsc2007: tsc2007grp {
554 fsl,pins = <
555 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
556 >;
557 };
c8787bae 558
c4aca663
LW		 559 pinctrl_uart1: uart1grp {
560 fsl,pins = <
561 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
562 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
563 >;
564 };
c8787bae 565
c4aca663
LW		 566 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
567 fsl,pins = <
568 MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1
569 MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1
570 >;
571 };
c8787bae 572
c4aca663
LW		 573 pinctrl_uart2: uart2grp {
574 fsl,pins = <
575 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
576 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
577 >;
578 };
c8787bae 579
c4aca663
LW		 580 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
581 fsl,pins = <
582 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
583 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
584 >;
585 };
c8787bae 586
c4aca663
LW		 587 pinctrl_uart3: uart3grp {
588 fsl,pins = <
589 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
590 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
591 >;
592 };
c8787bae 593
c4aca663
LW		 594 pinctrl_uart3_rtscts: uart3_rtsctsgrp {
595 fsl,pins = <
596 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1
597 MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1
598 >;
599 };
c8787bae 600
c4aca663
LW		 601 pinctrl_usbh1_vbus: usbh1-vbusgrp {
602 fsl,pins = <
603 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
604 >;
605 };
c8787bae 606
c4aca663
LW		 607 pinctrl_usbotg: usbotggrp {
608 fsl,pins = <
609 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
610 >;
611 };
c8787bae 612
c4aca663
LW		 613 pinctrl_usbotg_vbus: usbotg-vbusgrp {
614 fsl,pins = <
615 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
616 >;
617 };
c8787bae 618
c4aca663
LW		 619 pinctrl_usdhc1: usdhc1grp {
620 fsl,pins = <
621 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
622 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
623 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
624 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
625 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
626 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
627 MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
628 >;
629 };
630
631 pinctrl_usdhc2: usdhc2grp {
632 fsl,pins = <
633 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1
634 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1
635 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1
636 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1
637 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1
638 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1
639 MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */
640 >;
c8787bae 641 };
96de0367
LW		 642
643 pinctrl_user_led: user-ledgrp {
644 fsl,pins = <
645 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
646 >;
647 };
c8787bae
LW		 648};
649
650&kpp {
651 pinctrl-names = "default";
652 pinctrl-0 = <&pinctrl_kpp>;
653 /* sample keymap */
654 /* row/col 0,1 are mapped to KPP row/col 6,7 */
655 linux,keymap = <
656 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
657 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
658 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
659 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
660 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
661 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
662 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
663 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
664 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
665 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
666 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
667 >;
1b6f2368 668 status = "okay";
c8787bae
LW		 669};
670
671&pwm1 {
672 pinctrl-names = "default";
673 pinctrl-0 = <&pinctrl_pwm1>;
674 #pwm-cells = <3>;
675 status = "disabled";
676};
677
678&pwm2 {
679 pinctrl-names = "default";
680 pinctrl-0 = <&pinctrl_pwm2>;
681 #pwm-cells = <3>;
682 status = "okay";
683};
684
685&ssi1 {
c8787bae
LW		 686 status = "okay";
687};
688
689&uart1 {
690 pinctrl-names = "default";
720f4340 691 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
2e7c416c 692 uart-has-rtscts;
c8787bae
LW		 693 status = "okay";
694};
695
696&uart2 {
697 pinctrl-names = "default";
698 pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
2e7c416c 699 uart-has-rtscts;
c8787bae
LW		 700 status = "okay";
701};
702
703&uart3 {
704 pinctrl-names = "default";
705 pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
2e7c416c 706 uart-has-rtscts;
c8787bae
LW		 707 status = "okay";
708};
709
710&usbh1 {
711 vbus-supply = <&reg_usbh1_vbus>;
712 dr_mode = "host";
713 disable-over-current;
714 status = "okay";
715};
716
717&usbotg {
718 vbus-supply = <&reg_usbotg_vbus>;
719 pinctrl-names = "default";
720 pinctrl-0 = <&pinctrl_usbotg>;
721 dr_mode = "peripheral";
722 disable-over-current;
723 status = "okay";
724};
725
726&usdhc1 {
727 pinctrl-names = "default";
728 pinctrl-0 = <&pinctrl_usdhc1>;
729 bus-width = <4>;
730 no-1-8-v;
89c1a8cf 731 cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
c8787bae
LW		 732 fsl,wp-controller;
733 status = "okay";
734};
735
736&usdhc2 {
737 pinctrl-names = "default";
738 pinctrl-0 = <&pinctrl_usdhc2>;
739 bus-width = <4>;
740 no-1-8-v;
89c1a8cf 741 cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
c8787bae
LW		 742 fsl,wp-controller;
743 status = "okay";
744};
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