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ARM: dts: imx6-tx6: remove regulator bus
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / imx6qdl-tx6.dtsi
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c8787bae 1/*
e06dd630 2 * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
c8787bae 3 *
e06dd630
LW		 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
c8787bae 8 *
e06dd630
LW		 9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
c8787bae
LW		 40 */
41
42#include <dt-bindings/gpio/gpio.h>
43#include <dt-bindings/input/input.h>
09bb4319 44#include <dt-bindings/interrupt-controller/irq.h>
c8787bae
LW		 45#include <dt-bindings/pwm/pwm.h>
46
47/ {
48 aliases {
49 can0 = &can2;
50 can1 = &can1;
51 ethernet0 = &fec;
52 lcdif_23bit_pins_a = &pinctrl_disp0_1;
53 lcdif_24bit_pins_a = &pinctrl_disp0_2;
54 pwm0 = &pwm1;
55 pwm1 = &pwm2;
56 reg_can_xcvr = &reg_can_xcvr;
57 stk5led = &user_led;
58 usbotg = &usbotg;
59 sdhc0 = &usdhc1;
60 sdhc1 = &usdhc2;
61 };
62
63 memory {
64 reg = <0 0>; /* will be filled by U-Boot */
65 };
66
67 clocks {
68 #address-cells = <1>;
69 #size-cells = <0>;
abe3e2b9 70
c8787bae
LW		 71 mclk: clock@0 {
72 compatible = "fixed-clock";
73 reg = <0>;
74 #clock-cells = <0>;
43ffc19e 75 clock-frequency = <26000000>;
c8787bae
LW		 76 };
77 };
78
79 gpio-keys {
80 compatible = "gpio-keys";
81
82 power {
83 label = "Power Button";
84 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
85 linux,code = <KEY_POWER>;
26cefdd1 86 wakeup-source;
c8787bae
LW		 87 };
88 };
89
90 leds {
91 compatible = "gpio-leds";
92
93 user_led: user {
94 label = "Heartbeat";
95 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
96 linux,default-trigger = "heartbeat";
97 };
98 };
99
7281795f
LW		 100 reg_3v3_etn: regulator-3v3-etn {
101 compatible = "regulator-fixed";
102 regulator-name = "3V3_ETN";
103 regulator-min-microvolt = <3300000>;
104 regulator-max-microvolt = <3300000>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_etnphy_power>;
107 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
108 enable-active-high;
109 };
c8787bae 110
7281795f
LW		 111 reg_2v5: regulator-2v5 {
112 compatible = "regulator-fixed";
113 regulator-name = "2V5";
114 regulator-min-microvolt = <2500000>;
115 regulator-max-microvolt = <2500000>;
116 regulator-always-on;
117 };
c8787bae 118
7281795f
LW		 119 reg_3v3: regulator-3v3 {
120 compatible = "regulator-fixed";
121 regulator-name = "3V3";
122 regulator-min-microvolt = <3300000>;
123 regulator-max-microvolt = <3300000>;
124 regulator-always-on;
125 };
c8787bae 126
7281795f
LW		 127 reg_can_xcvr: regulator-can-xcvr {
128 compatible = "regulator-fixed";
129 regulator-name = "CAN XCVR";
130 regulator-min-microvolt = <3300000>;
131 regulator-max-microvolt = <3300000>;
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
134 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
135 enable-active-low;
136 };
c8787bae 137
7281795f
LW		 138 reg_lcd0_pwr: regulator-lcd0-pwr {
139 compatible = "regulator-fixed";
140 regulator-name = "LCD0 POWER";
141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <3300000>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_lcd0_pwr>;
145 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
146 enable-active-high;
147 regulator-boot-on;
148 };
c8787bae 149
7281795f
LW		 150 reg_lcd1_pwr: regulator-lcd1-pwr {
151 compatible = "regulator-fixed";
152 regulator-name = "LCD1 POWER";
153 regulator-min-microvolt = <3300000>;
154 regulator-max-microvolt = <3300000>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_lcd1_pwr>;
157 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
158 enable-active-high;
159 regulator-boot-on;
160 };
c8787bae 161
7281795f
LW		 162 reg_usbh1_vbus: regulator-usbh1-vbus {
163 compatible = "regulator-fixed";
164 regulator-name = "usbh1_vbus";
165 regulator-min-microvolt = <5000000>;
166 regulator-max-microvolt = <5000000>;
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_usbh1_vbus>;
169 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
170 enable-active-high;
171 };
c8787bae 172
7281795f
LW		 173 reg_usbotg_vbus: regulator-usbotg-vbus {
174 compatible = "regulator-fixed";
175 regulator-name = "usbotg_vbus";
176 regulator-min-microvolt = <5000000>;
177 regulator-max-microvolt = <5000000>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_usbotg_vbus>;
180 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
181 enable-active-high;
c8787bae
LW		 182 };
183
184 sound {
185 compatible = "karo,imx6qdl-tx6qdl-sgtl5000",
186 "fsl,imx-audio-sgtl5000";
187 model = "sgtl5000-audio";
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_audmux>;
190 ssi-controller = <&ssi1>;
191 audio-codec = <&sgtl5000>;
192 audio-routing =
193 "MIC_IN", "Mic Jack",
194 "Mic Jack", "Mic Bias",
195 "Headphone Jack", "HP_OUT";
196 mux-int-port = <1>;
197 mux-ext-port = <5>;
198 };
199};
200
201&audmux {
202 status = "okay";
203};
204
205&can1 {
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_flexcan1>;
208 xceiver-supply = <&reg_can_xcvr>;
209 status = "okay";
210};
211
212&can2 {
213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_flexcan2>;
215 xceiver-supply = <&reg_can_xcvr>;
216 status = "okay";
217};
218
219&ecspi1 {
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_ecspi1>;
222 fsl,spi-num-chipselects = <2>;
223 cs-gpios = <
224 &gpio2 30 GPIO_ACTIVE_HIGH
225 &gpio3 19 GPIO_ACTIVE_HIGH
226 >;
0fd646d0 227 status = "disabled";
c8787bae
LW		 228
229 spidev0: spi@0 {
230 compatible = "spidev";
231 reg = <0>;
232 spi-max-frequency = <54000000>;
233 };
234
235 spidev1: spi@1 {
236 compatible = "spidev";
237 reg = <1>;
238 spi-max-frequency = <54000000>;
239 };
240};
241
242&fec {
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_enet>;
76591910
LW		 245 clocks = <&clks IMX6QDL_CLK_ENET>,
246 <&clks IMX6QDL_CLK_ENET>,
247 <&clks IMX6QDL_CLK_ENET_REF>,
248 <&clks IMX6QDL_CLK_ENET_REF>;
249 clock-names = "ipg", "ahb", "ptp", "enet_out";
c8787bae
LW		 250 phy-mode = "rmii";
251 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
9cbda37b 252 phy-handle = <&etnphy>;
c8787bae
LW		 253 phy-supply = <&reg_3v3_etn>;
254 status = "okay";
9cbda37b
LW		 255
256 mdio {
257 #address-cells = <1>;
258 #size-cells = <0>;
259
260 etnphy: ethernet-phy@0 {
261 compatible = "ethernet-phy-ieee802.3-c22";
262 reg = <0>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_enet_mdio>;
265 interrupts-extended = <&gpio7 1 IRQ_TYPE_EDGE_FALLING>;
266 };
267 };
c8787bae
LW		 268};
269
270&gpmi {
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_gpmi_nand>;
273 nand-on-flash-bbt;
274 fsl,no-blockmark-swap;
275 status = "okay";
276};
277
278&i2c1 {
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_i2c1>;
281 clock-frequency = <400000>;
282 status = "okay";
283
284 ds1339: rtc@68 {
285 compatible = "dallas,ds1339";
286 reg = <0x68>;
287 };
288};
289
290&i2c3 {
291 pinctrl-names = "default";
292 pinctrl-0 = <&pinctrl_i2c3>;
293 clock-frequency = <400000>;
294 status = "okay";
295
296 sgtl5000: sgtl5000@0a {
297 compatible = "fsl,sgtl5000";
298 reg = <0x0a>;
299 VDDA-supply = <&reg_2v5>;
300 VDDIO-supply = <&reg_3v3>;
301 clocks = <&mclk>;
302 };
303
304 polytouch: edt-ft5x06@38 {
305 compatible = "edt,edt-ft5x06";
306 reg = <0x38>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_edt_ft5x06>;
309 interrupt-parent = <&gpio6>;
09bb4319 310 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
c8787bae
LW		 311 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
312 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
26cefdd1 313 wakeup-source;
c8787bae
LW		 314 };
315
316 touchscreen: tsc2007@48 {
317 compatible = "ti,tsc2007";
318 reg = <0x48>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_tsc2007>;
321 interrupt-parent = <&gpio3>;
322 interrupts = <26 0>;
323 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
324 ti,x-plate-ohms = <660>;
26cefdd1 325 wakeup-source;
c8787bae
LW		 326 };
327};
328
329&iomuxc {
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_hog>;
332
c4aca663
LW		 333 pinctrl_hog: hoggrp {
334 fsl,pins = <
335 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
336 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
337 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
338 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
339 >;
340 };
c8787bae 341
c4aca663
LW		 342 pinctrl_audmux: audmuxgrp {
343 fsl,pins = <
344 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */
345 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */
346 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */
347 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */
348 >;
349 };
c8787bae 350
c4aca663
LW		 351 pinctrl_disp0_1: disp0grp-1 {
352 fsl,pins = <
353 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
354 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
355 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
356 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
357 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
358 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
359 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
360 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
361 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
362 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
363 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
364 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
365 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
366 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
367 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
368 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
369 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
370 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
371 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
372 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
373 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
374 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
375 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
376 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
377 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
378 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
379 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
380 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
381 >;
382 };
c8787bae 383
c4aca663
LW		 384 pinctrl_disp0_2: disp0grp-2 {
385 fsl,pins = <
386 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
387 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
388 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
389 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
390 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
391 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
392 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
393 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
394 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
395 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
396 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
397 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
398 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
399 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
400 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
401 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
402 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
403 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
404 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
405 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
406 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
407 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
408 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
409 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
410 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
411 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
412 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
413 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
414 >;
415 };
c8787bae 416
c4aca663
LW		 417 pinctrl_ecspi1: ecspi1grp {
418 fsl,pins = <
419 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0
420 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0
421 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0
422 MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
423 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */
424 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
425 >;
426 };
c8787bae 427
c4aca663
LW		 428 pinctrl_edt_ft5x06: edt-ft5x06grp {
429 fsl,pins = <
430 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
431 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
432 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
433 >;
434 };
c8787bae 435
c4aca663
LW		 436 pinctrl_enet: enetgrp {
437 fsl,pins = <
438 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
439 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
440 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
441 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
442 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
443 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
444 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
445 >;
446 };
c8787bae 447
c4aca663
LW		 448 pinctrl_enet_mdio: enet-mdiogrp {
449 fsl,pins = <
450 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
451 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
452 >;
453 };
c8787bae 454
c4aca663
LW		 455 pinctrl_etnphy_power: etnphy-pwrgrp {
456 fsl,pins = <
457 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
458 >;
459 };
c8787bae 460
c4aca663
LW		 461 pinctrl_flexcan1: flexcan1grp {
462 fsl,pins = <
463 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
464 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
465 >;
466 };
c8787bae 467
c4aca663
LW		 468 pinctrl_flexcan2: flexcan2grp {
469 fsl,pins = <
470 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
471 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
472 >;
473 };
c8787bae 474
c4aca663
LW		 475 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
476 fsl,pins = <
477 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
478 >;
479 };
c8787bae 480
c4aca663
LW		 481 pinctrl_gpmi_nand: gpminandgrp {
482 fsl,pins = <
483 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
484 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
485 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
486 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
487 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
488 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
489 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
490 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
491 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
492 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
493 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
494 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
495 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
496 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
497 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
498 >;
499 };
c8787bae 500
c4aca663
LW		 501 pinctrl_i2c1: i2c1grp {
502 fsl,pins = <
503 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
504 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
505 >;
506 };
c8787bae 507
c4aca663
LW		 508 pinctrl_i2c3: i2c3grp {
509 fsl,pins = <
510 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
511 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
512 >;
513 };
c8787bae 514
c4aca663
LW		 515 pinctrl_kpp: kppgrp {
516 fsl,pins = <
517 MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
518 MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
519 MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
520 MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
521 MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
522 MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
523 MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
524 MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
525 >;
526 };
c8787bae 527
c4aca663
LW		 528 pinctrl_lcd0_pwr: lcd0-pwrgrp {
529 fsl,pins = <
530 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
531 >;
532 };
c8787bae 533
c4aca663
LW		 534 pinctrl_lcd1_pwr: lcd-pwrgrp {
535 fsl,pins = <
536 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
537 >;
538 };
c8787bae 539
c4aca663
LW		 540 pinctrl_pwm1: pwm1grp {
541 fsl,pins = <
542 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
543 >;
544 };
c8787bae 545
c4aca663
LW		 546 pinctrl_pwm2: pwm2grp {
547 fsl,pins = <
548 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
549 >;
550 };
c8787bae 551
c4aca663
LW		 552 pinctrl_tsc2007: tsc2007grp {
553 fsl,pins = <
554 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
555 >;
556 };
c8787bae 557
c4aca663
LW		 558 pinctrl_uart1: uart1grp {
559 fsl,pins = <
560 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
561 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
562 >;
563 };
c8787bae 564
c4aca663
LW		 565 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
566 fsl,pins = <
567 MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1
568 MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1
569 >;
570 };
c8787bae 571
c4aca663
LW		 572 pinctrl_uart2: uart2grp {
573 fsl,pins = <
574 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
575 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
576 >;
577 };
c8787bae 578
c4aca663
LW		 579 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
580 fsl,pins = <
581 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
582 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
583 >;
584 };
c8787bae 585
c4aca663
LW		 586 pinctrl_uart3: uart3grp {
587 fsl,pins = <
588 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
589 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
590 >;
591 };
c8787bae 592
c4aca663
LW		 593 pinctrl_uart3_rtscts: uart3_rtsctsgrp {
594 fsl,pins = <
595 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1
596 MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1
597 >;
598 };
c8787bae 599
c4aca663
LW		 600 pinctrl_usbh1_vbus: usbh1-vbusgrp {
601 fsl,pins = <
602 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
603 >;
604 };
c8787bae 605
c4aca663
LW		 606 pinctrl_usbotg: usbotggrp {
607 fsl,pins = <
608 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
609 >;
610 };
c8787bae 611
c4aca663
LW		 612 pinctrl_usbotg_vbus: usbotg-vbusgrp {
613 fsl,pins = <
614 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
615 >;
616 };
c8787bae 617
c4aca663
LW		 618 pinctrl_usdhc1: usdhc1grp {
619 fsl,pins = <
620 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
621 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
622 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
623 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
624 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
625 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
626 MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
627 >;
628 };
629
630 pinctrl_usdhc2: usdhc2grp {
631 fsl,pins = <
632 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1
633 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1
634 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1
635 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1
636 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1
637 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1
638 MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */
639 >;
c8787bae
LW		 640 };
641};
642
643&kpp {
644 pinctrl-names = "default";
645 pinctrl-0 = <&pinctrl_kpp>;
646 /* sample keymap */
647 /* row/col 0,1 are mapped to KPP row/col 6,7 */
648 linux,keymap = <
649 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
650 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
651 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
652 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
653 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
654 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
655 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
656 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
657 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
658 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
659 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
660 >;
1b6f2368 661 status = "okay";
c8787bae
LW		 662};
663
664&pwm1 {
665 pinctrl-names = "default";
666 pinctrl-0 = <&pinctrl_pwm1>;
667 #pwm-cells = <3>;
668 status = "disabled";
669};
670
671&pwm2 {
672 pinctrl-names = "default";
673 pinctrl-0 = <&pinctrl_pwm2>;
674 #pwm-cells = <3>;
675 status = "okay";
676};
677
678&ssi1 {
c8787bae
LW		 679 status = "okay";
680};
681
682&uart1 {
683 pinctrl-names = "default";
684 pinctrl-0 = <&pinctrl_uart1>;
685 status = "okay";
686};
687
688&uart2 {
689 pinctrl-names = "default";
690 pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
691 status = "okay";
692};
693
694&uart3 {
695 pinctrl-names = "default";
696 pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
697 status = "okay";
698};
699
700&usbh1 {
701 vbus-supply = <&reg_usbh1_vbus>;
702 dr_mode = "host";
703 disable-over-current;
704 status = "okay";
705};
706
707&usbotg {
708 vbus-supply = <&reg_usbotg_vbus>;
709 pinctrl-names = "default";
710 pinctrl-0 = <&pinctrl_usbotg>;
711 dr_mode = "peripheral";
712 disable-over-current;
713 status = "okay";
714};
715
716&usdhc1 {
717 pinctrl-names = "default";
718 pinctrl-0 = <&pinctrl_usdhc1>;
719 bus-width = <4>;
720 no-1-8-v;
89c1a8cf 721 cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
c8787bae
LW		 722 fsl,wp-controller;
723 status = "okay";
724};
725
726&usdhc2 {
727 pinctrl-names = "default";
728 pinctrl-0 = <&pinctrl_usdhc2>;
729 bus-width = <4>;
730 no-1-8-v;
89c1a8cf 731 cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
c8787bae
LW		 732 fsl,wp-controller;
733 status = "okay";
734};
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