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ARM: dts: imx6-tx6: remove container node around pinctrl nodes
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx6qdl-tx6.dtsi
CommitLineData
c8787bae 1/*
e06dd630 2 * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de>
c8787bae 3 *
e06dd630
LW		 4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
c8787bae 8 *
e06dd630
LW		 9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
c8787bae
LW		 40 */
41
42#include <dt-bindings/gpio/gpio.h>
43#include <dt-bindings/input/input.h>
09bb4319 44#include <dt-bindings/interrupt-controller/irq.h>
c8787bae
LW		 45#include <dt-bindings/pwm/pwm.h>
46
47/ {
48 aliases {
49 can0 = &can2;
50 can1 = &can1;
51 ethernet0 = &fec;
52 lcdif_23bit_pins_a = &pinctrl_disp0_1;
53 lcdif_24bit_pins_a = &pinctrl_disp0_2;
54 pwm0 = &pwm1;
55 pwm1 = &pwm2;
56 reg_can_xcvr = &reg_can_xcvr;
57 stk5led = &user_led;
58 usbotg = &usbotg;
59 sdhc0 = &usdhc1;
60 sdhc1 = &usdhc2;
61 };
62
63 memory {
64 reg = <0 0>; /* will be filled by U-Boot */
65 };
66
67 clocks {
68 #address-cells = <1>;
69 #size-cells = <0>;
abe3e2b9 70
c8787bae
LW		 71 mclk: clock@0 {
72 compatible = "fixed-clock";
73 reg = <0>;
74 #clock-cells = <0>;
43ffc19e 75 clock-frequency = <26000000>;
c8787bae
LW		 76 };
77 };
78
79 gpio-keys {
80 compatible = "gpio-keys";
81
82 power {
83 label = "Power Button";
84 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
85 linux,code = <KEY_POWER>;
26cefdd1 86 wakeup-source;
c8787bae
LW		 87 };
88 };
89
90 leds {
91 compatible = "gpio-leds";
92
93 user_led: user {
94 label = "Heartbeat";
95 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
96 linux,default-trigger = "heartbeat";
97 };
98 };
99
100 regulators {
101 compatible = "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <0>;
104
105 reg_3v3_etn: regulator@0 {
106 compatible = "regulator-fixed";
107 reg = <0>;
108 regulator-name = "3V3_ETN";
109 regulator-min-microvolt = <3300000>;
110 regulator-max-microvolt = <3300000>;
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_etnphy_power>;
113 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
114 enable-active-high;
115 };
116
117 reg_2v5: regulator@1 {
118 compatible = "regulator-fixed";
119 reg = <1>;
120 regulator-name = "2V5";
121 regulator-min-microvolt = <2500000>;
122 regulator-max-microvolt = <2500000>;
123 regulator-always-on;
124 };
125
126 reg_3v3: regulator@2 {
127 compatible = "regulator-fixed";
128 reg = <2>;
129 regulator-name = "3V3";
130 regulator-min-microvolt = <3300000>;
131 regulator-max-microvolt = <3300000>;
132 regulator-always-on;
133 };
134
135 reg_can_xcvr: regulator@3 {
136 compatible = "regulator-fixed";
137 reg = <3>;
138 regulator-name = "CAN XCVR";
139 regulator-min-microvolt = <3300000>;
140 regulator-max-microvolt = <3300000>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
143 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
144 enable-active-low;
145 };
146
147 reg_lcd0_pwr: regulator@4 {
148 compatible = "regulator-fixed";
149 reg = <4>;
150 regulator-name = "LCD0 POWER";
151 regulator-min-microvolt = <3300000>;
152 regulator-max-microvolt = <3300000>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_lcd0_pwr>;
155 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
156 enable-active-high;
157 regulator-boot-on;
158 regulator-always-on;
159 };
160
161 reg_lcd1_pwr: regulator@5 {
162 compatible = "regulator-fixed";
163 reg = <5>;
164 regulator-name = "LCD1 POWER";
165 regulator-min-microvolt = <3300000>;
166 regulator-max-microvolt = <3300000>;
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_lcd1_pwr>;
169 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
170 enable-active-high;
171 regulator-boot-on;
172 regulator-always-on;
173 };
174
175 reg_usbh1_vbus: regulator@6 {
176 compatible = "regulator-fixed";
177 reg = <6>;
178 regulator-name = "usbh1_vbus";
179 regulator-min-microvolt = <5000000>;
180 regulator-max-microvolt = <5000000>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_usbh1_vbus>;
183 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
184 enable-active-high;
185 };
186
187 reg_usbotg_vbus: regulator@7 {
188 compatible = "regulator-fixed";
189 reg = <7>;
190 regulator-name = "usbotg_vbus";
191 regulator-min-microvolt = <5000000>;
192 regulator-max-microvolt = <5000000>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_usbotg_vbus>;
195 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
196 enable-active-high;
197 };
198 };
199
200 sound {
201 compatible = "karo,imx6qdl-tx6qdl-sgtl5000",
202 "fsl,imx-audio-sgtl5000";
203 model = "sgtl5000-audio";
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_audmux>;
206 ssi-controller = <&ssi1>;
207 audio-codec = <&sgtl5000>;
208 audio-routing =
209 "MIC_IN", "Mic Jack",
210 "Mic Jack", "Mic Bias",
211 "Headphone Jack", "HP_OUT";
212 mux-int-port = <1>;
213 mux-ext-port = <5>;
214 };
215};
216
217&audmux {
218 status = "okay";
219};
220
221&can1 {
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_flexcan1>;
224 xceiver-supply = <&reg_can_xcvr>;
225 status = "okay";
226};
227
228&can2 {
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_flexcan2>;
231 xceiver-supply = <&reg_can_xcvr>;
232 status = "okay";
233};
234
235&ecspi1 {
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_ecspi1>;
238 fsl,spi-num-chipselects = <2>;
239 cs-gpios = <
240 &gpio2 30 GPIO_ACTIVE_HIGH
241 &gpio3 19 GPIO_ACTIVE_HIGH
242 >;
0fd646d0 243 status = "disabled";
c8787bae
LW		 244
245 spidev0: spi@0 {
246 compatible = "spidev";
247 reg = <0>;
248 spi-max-frequency = <54000000>;
249 };
250
251 spidev1: spi@1 {
252 compatible = "spidev";
253 reg = <1>;
254 spi-max-frequency = <54000000>;
255 };
256};
257
258&fec {
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_enet>;
76591910
LW		 261 clocks = <&clks IMX6QDL_CLK_ENET>,
262 <&clks IMX6QDL_CLK_ENET>,
263 <&clks IMX6QDL_CLK_ENET_REF>,
264 <&clks IMX6QDL_CLK_ENET_REF>;
265 clock-names = "ipg", "ahb", "ptp", "enet_out";
c8787bae
LW		 266 phy-mode = "rmii";
267 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
268 phy-supply = <&reg_3v3_etn>;
269 status = "okay";
270};
271
272&gpmi {
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_gpmi_nand>;
275 nand-on-flash-bbt;
276 fsl,no-blockmark-swap;
277 status = "okay";
278};
279
280&i2c1 {
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_i2c1>;
283 clock-frequency = <400000>;
284 status = "okay";
285
286 ds1339: rtc@68 {
287 compatible = "dallas,ds1339";
288 reg = <0x68>;
289 };
290};
291
292&i2c3 {
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_i2c3>;
295 clock-frequency = <400000>;
296 status = "okay";
297
298 sgtl5000: sgtl5000@0a {
299 compatible = "fsl,sgtl5000";
300 reg = <0x0a>;
301 VDDA-supply = <&reg_2v5>;
302 VDDIO-supply = <&reg_3v3>;
303 clocks = <&mclk>;
304 };
305
306 polytouch: edt-ft5x06@38 {
307 compatible = "edt,edt-ft5x06";
308 reg = <0x38>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_edt_ft5x06>;
311 interrupt-parent = <&gpio6>;
09bb4319 312 interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
c8787bae
LW		 313 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
314 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
26cefdd1 315 wakeup-source;
c8787bae
LW		 316 };
317
318 touchscreen: tsc2007@48 {
319 compatible = "ti,tsc2007";
320 reg = <0x48>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_tsc2007>;
323 interrupt-parent = <&gpio3>;
324 interrupts = <26 0>;
325 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
326 ti,x-plate-ohms = <660>;
26cefdd1 327 wakeup-source;
c8787bae
LW		 328 };
329};
330
331&iomuxc {
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_hog>;
334
c4aca663
LW		 335 pinctrl_hog: hoggrp {
336 fsl,pins = <
337 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
338 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
339 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
340 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
341 >;
342 };
c8787bae 343
c4aca663
LW		 344 pinctrl_audmux: audmuxgrp {
345 fsl,pins = <
346 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */
347 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */
348 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */
349 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */
350 >;
351 };
c8787bae 352
c4aca663
LW		 353 pinctrl_disp0_1: disp0grp-1 {
354 fsl,pins = <
355 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
356 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
357 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
358 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
359 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
360 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
361 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
362 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
363 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
364 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
365 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
366 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
367 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
368 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
369 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
370 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
371 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
372 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
373 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
374 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
375 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
376 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
377 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
378 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
379 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
380 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
381 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
382 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
383 >;
384 };
c8787bae 385
c4aca663
LW		 386 pinctrl_disp0_2: disp0grp-2 {
387 fsl,pins = <
388 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
389 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
390 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
391 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
392 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
393 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
394 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
395 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
396 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
397 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
398 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
399 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
400 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
401 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
402 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
403 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
404 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
405 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
406 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
407 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
408 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
409 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
410 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
411 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
412 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
413 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
414 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
415 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
416 >;
417 };
c8787bae 418
c4aca663
LW		 419 pinctrl_ecspi1: ecspi1grp {
420 fsl,pins = <
421 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0
422 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0
423 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0
424 MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
425 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */
426 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
427 >;
428 };
c8787bae 429
c4aca663
LW		 430 pinctrl_edt_ft5x06: edt-ft5x06grp {
431 fsl,pins = <
432 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
433 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
434 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
435 >;
436 };
c8787bae 437
c4aca663
LW		 438 pinctrl_enet: enetgrp {
439 fsl,pins = <
440 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
441 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
442 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
443 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
444 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
445 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
446 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
447 >;
448 };
c8787bae 449
c4aca663
LW		 450 pinctrl_enet_mdio: enet-mdiogrp {
451 fsl,pins = <
452 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
453 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
454 >;
455 };
c8787bae 456
c4aca663
LW		 457 pinctrl_etnphy_power: etnphy-pwrgrp {
458 fsl,pins = <
459 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
460 >;
461 };
c8787bae 462
c4aca663
LW		 463 pinctrl_flexcan1: flexcan1grp {
464 fsl,pins = <
465 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
466 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
467 >;
468 };
c8787bae 469
c4aca663
LW		 470 pinctrl_flexcan2: flexcan2grp {
471 fsl,pins = <
472 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
473 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
474 >;
475 };
c8787bae 476
c4aca663
LW		 477 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
478 fsl,pins = <
479 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
480 >;
481 };
c8787bae 482
c4aca663
LW		 483 pinctrl_gpmi_nand: gpminandgrp {
484 fsl,pins = <
485 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
486 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
487 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
488 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
489 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
490 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
491 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
492 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
493 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
494 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
495 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
496 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
497 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
498 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
499 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
500 >;
501 };
c8787bae 502
c4aca663
LW		 503 pinctrl_i2c1: i2c1grp {
504 fsl,pins = <
505 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
506 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
507 >;
508 };
c8787bae 509
c4aca663
LW		 510 pinctrl_i2c3: i2c3grp {
511 fsl,pins = <
512 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
513 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
514 >;
515 };
c8787bae 516
c4aca663
LW		 517 pinctrl_kpp: kppgrp {
518 fsl,pins = <
519 MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
520 MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
521 MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
522 MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
523 MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
524 MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
525 MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
526 MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
527 >;
528 };
c8787bae 529
c4aca663
LW		 530 pinctrl_lcd0_pwr: lcd0-pwrgrp {
531 fsl,pins = <
532 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
533 >;
534 };
c8787bae 535
c4aca663
LW		 536 pinctrl_lcd1_pwr: lcd-pwrgrp {
537 fsl,pins = <
538 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
539 >;
540 };
c8787bae 541
c4aca663
LW		 542 pinctrl_pwm1: pwm1grp {
543 fsl,pins = <
544 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
545 >;
546 };
c8787bae 547
c4aca663
LW		 548 pinctrl_pwm2: pwm2grp {
549 fsl,pins = <
550 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
551 >;
552 };
c8787bae 553
c4aca663
LW		 554 pinctrl_tsc2007: tsc2007grp {
555 fsl,pins = <
556 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
557 >;
558 };
c8787bae 559
c4aca663
LW		 560 pinctrl_uart1: uart1grp {
561 fsl,pins = <
562 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
563 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
564 >;
565 };
c8787bae 566
c4aca663
LW		 567 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
568 fsl,pins = <
569 MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1
570 MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1
571 >;
572 };
c8787bae 573
c4aca663
LW		 574 pinctrl_uart2: uart2grp {
575 fsl,pins = <
576 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
577 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
578 >;
579 };
c8787bae 580
c4aca663
LW		 581 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
582 fsl,pins = <
583 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
584 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
585 >;
586 };
c8787bae 587
c4aca663
LW		 588 pinctrl_uart3: uart3grp {
589 fsl,pins = <
590 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
591 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
592 >;
593 };
c8787bae 594
c4aca663
LW		 595 pinctrl_uart3_rtscts: uart3_rtsctsgrp {
596 fsl,pins = <
597 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1
598 MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1
599 >;
600 };
c8787bae 601
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LW		 602 pinctrl_usbh1_vbus: usbh1-vbusgrp {
603 fsl,pins = <
604 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
605 >;
606 };
c8787bae 607
c4aca663
LW		 608 pinctrl_usbotg: usbotggrp {
609 fsl,pins = <
610 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
611 >;
612 };
c8787bae 613
c4aca663
LW		 614 pinctrl_usbotg_vbus: usbotg-vbusgrp {
615 fsl,pins = <
616 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
617 >;
618 };
c8787bae 619
c4aca663
LW		 620 pinctrl_usdhc1: usdhc1grp {
621 fsl,pins = <
622 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
623 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
624 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
625 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
626 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
627 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
628 MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
629 >;
630 };
631
632 pinctrl_usdhc2: usdhc2grp {
633 fsl,pins = <
634 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1
635 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1
636 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1
637 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1
638 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1
639 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1
640 MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */
641 >;
c8787bae
LW		 642 };
643};
644
645&kpp {
646 pinctrl-names = "default";
647 pinctrl-0 = <&pinctrl_kpp>;
648 /* sample keymap */
649 /* row/col 0,1 are mapped to KPP row/col 6,7 */
650 linux,keymap = <
651 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
652 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
653 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
654 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
655 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
656 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
657 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
658 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
659 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
660 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
661 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
662 >;
1b6f2368 663 status = "okay";
c8787bae
LW		 664};
665
666&pwm1 {
667 pinctrl-names = "default";
668 pinctrl-0 = <&pinctrl_pwm1>;
669 #pwm-cells = <3>;
670 status = "disabled";
671};
672
673&pwm2 {
674 pinctrl-names = "default";
675 pinctrl-0 = <&pinctrl_pwm2>;
676 #pwm-cells = <3>;
677 status = "okay";
678};
679
680&ssi1 {
c8787bae
LW		 681 status = "okay";
682};
683
684&uart1 {
685 pinctrl-names = "default";
686 pinctrl-0 = <&pinctrl_uart1>;
687 status = "okay";
688};
689
690&uart2 {
691 pinctrl-names = "default";
692 pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
693 status = "okay";
694};
695
696&uart3 {
697 pinctrl-names = "default";
698 pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
699 status = "okay";
700};
701
702&usbh1 {
703 vbus-supply = <&reg_usbh1_vbus>;
704 dr_mode = "host";
705 disable-over-current;
706 status = "okay";
707};
708
709&usbotg {
710 vbus-supply = <&reg_usbotg_vbus>;
711 pinctrl-names = "default";
712 pinctrl-0 = <&pinctrl_usbotg>;
713 dr_mode = "peripheral";
714 disable-over-current;
715 status = "okay";
716};
717
718&usdhc1 {
719 pinctrl-names = "default";
720 pinctrl-0 = <&pinctrl_usdhc1>;
721 bus-width = <4>;
722 no-1-8-v;
89c1a8cf 723 cd-gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
c8787bae
LW		 724 fsl,wp-controller;
725 status = "okay";
726};
727
728&usdhc2 {
729 pinctrl-names = "default";
730 pinctrl-0 = <&pinctrl_usdhc2>;
731 bus-width = <4>;
732 no-1-8-v;
89c1a8cf 733 cd-gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
c8787bae
LW		 734 fsl,wp-controller;
735 status = "okay";
736};
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