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Commit | Line | Data |
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241f76b2 FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // | |
3 | // Copyright 2011 Freescale Semiconductor, Inc. | |
4 | // Copyright 2011 Linaro Ltd. | |
7d740f87 | 5 | |
8888f651 | 6 | #include <dt-bindings/clock/imx6qdl-clock.h> |
768b525e | 7 | #include <dt-bindings/input/input.h> |
07134a36 LS |
8 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
9 | ||
7d740f87 | 10 | / { |
7f107887 FE |
11 | #address-cells = <1>; |
12 | #size-cells = <1>; | |
a971c554 FE |
13 | /* |
14 | * The decompressor and also some bootloaders rely on a | |
15 | * pre-existing /chosen node to be available to insert the | |
16 | * command line and merge other ATAGS info. | |
a971c554 FE |
17 | */ |
18 | chosen {}; | |
7f107887 | 19 | |
7d740f87 | 20 | aliases { |
22970070 | 21 | ethernet0 = &fec; |
5f8fbc2c LW |
22 | can0 = &can1; |
23 | can1 = &can2; | |
5230f8fe SG |
24 | gpio0 = &gpio1; |
25 | gpio1 = &gpio2; | |
26 | gpio2 = &gpio3; | |
27 | gpio3 = &gpio4; | |
28 | gpio4 = &gpio5; | |
29 | gpio5 = &gpio6; | |
30 | gpio6 = &gpio7; | |
80fa0584 SH |
31 | i2c0 = &i2c1; |
32 | i2c1 = &i2c2; | |
33 | i2c2 = &i2c3; | |
41beef39 | 34 | ipu0 = &ipu1; |
fb06d65c SH |
35 | mmc0 = &usdhc1; |
36 | mmc1 = &usdhc2; | |
37 | mmc2 = &usdhc3; | |
38 | mmc3 = &usdhc4; | |
80fa0584 SH |
39 | serial0 = &uart1; |
40 | serial1 = &uart2; | |
41 | serial2 = &uart3; | |
42 | serial3 = &uart4; | |
43 | serial4 = &uart5; | |
44 | spi0 = &ecspi1; | |
45 | spi1 = &ecspi2; | |
46 | spi2 = &ecspi3; | |
47 | spi3 = &ecspi4; | |
8189c51f PC |
48 | usbphy0 = &usbphy1; |
49 | usbphy1 = &usbphy2; | |
7d740f87 SG |
50 | }; |
51 | ||
7d740f87 | 52 | clocks { |
7d740f87 SG |
53 | ckil { |
54 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
4b2b4043 | 55 | #clock-cells = <0>; |
7d740f87 SG |
56 | clock-frequency = <32768>; |
57 | }; | |
58 | ||
59 | ckih1 { | |
60 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
4b2b4043 | 61 | #clock-cells = <0>; |
7d740f87 SG |
62 | clock-frequency = <0>; |
63 | }; | |
64 | ||
65 | osc { | |
66 | compatible = "fsl,imx-osc", "fixed-clock"; | |
4b2b4043 | 67 | #clock-cells = <0>; |
7d740f87 SG |
68 | clock-frequency = <24000000>; |
69 | }; | |
70 | }; | |
71 | ||
1e989603 FE |
72 | tempmon: tempmon { |
73 | compatible = "fsl,imx6q-tempmon"; | |
74 | interrupt-parent = <&gpc>; | |
75 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; | |
76 | fsl,tempmon = <&anatop>; | |
77 | fsl,tempmon-data = <&ocotp>; | |
78 | clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; | |
4951c2da | 79 | #thermal-sensor-cells = <0>; |
1e989603 FE |
80 | }; |
81 | ||
82 | ldb: ldb { | |
83 | #address-cells = <1>; | |
84 | #size-cells = <0>; | |
85 | compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; | |
86 | gpr = <&gpr>; | |
87 | status = "disabled"; | |
88 | ||
89 | lvds-channel@0 { | |
90 | #address-cells = <1>; | |
91 | #size-cells = <0>; | |
92 | reg = <0>; | |
93 | status = "disabled"; | |
94 | ||
95 | port@0 { | |
96 | reg = <0>; | |
97 | ||
98 | lvds0_mux_0: endpoint { | |
99 | remote-endpoint = <&ipu1_di0_lvds0>; | |
100 | }; | |
101 | }; | |
102 | ||
103 | port@1 { | |
104 | reg = <1>; | |
105 | ||
106 | lvds0_mux_1: endpoint { | |
107 | remote-endpoint = <&ipu1_di1_lvds0>; | |
108 | }; | |
109 | }; | |
110 | }; | |
111 | ||
112 | lvds-channel@1 { | |
113 | #address-cells = <1>; | |
114 | #size-cells = <0>; | |
115 | reg = <1>; | |
116 | status = "disabled"; | |
117 | ||
118 | port@0 { | |
119 | reg = <0>; | |
120 | ||
121 | lvds1_mux_0: endpoint { | |
122 | remote-endpoint = <&ipu1_di0_lvds1>; | |
123 | }; | |
124 | }; | |
125 | ||
126 | port@1 { | |
127 | reg = <1>; | |
128 | ||
129 | lvds1_mux_1: endpoint { | |
130 | remote-endpoint = <&ipu1_di1_lvds1>; | |
131 | }; | |
132 | }; | |
133 | }; | |
134 | }; | |
135 | ||
10fff259 | 136 | pmu: pmu { |
1e989603 FE |
137 | compatible = "arm,cortex-a9-pmu"; |
138 | interrupt-parent = <&gpc>; | |
139 | interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; | |
140 | }; | |
141 | ||
4ca7dbdb FS |
142 | usbphynop1: usbphynop1 { |
143 | compatible = "usb-nop-xceiv"; | |
144 | #phy-cells = <0>; | |
145 | }; | |
146 | ||
147 | usbphynop2: usbphynop2 { | |
148 | compatible = "usb-nop-xceiv"; | |
149 | #phy-cells = <0>; | |
150 | }; | |
151 | ||
7d740f87 SG |
152 | soc { |
153 | #address-cells = <1>; | |
154 | #size-cells = <1>; | |
155 | compatible = "simple-bus"; | |
b923ff6a | 156 | interrupt-parent = <&gpc>; |
7d740f87 SG |
157 | ranges; |
158 | ||
df5cc9d0 | 159 | dma_apbh: dma-apbh@110000 { |
e5d0f9f5 HS |
160 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; |
161 | reg = <0x00110000 0x2000>; | |
275c08b5 TK |
162 | interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, |
163 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
164 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
165 | <0 13 IRQ_TYPE_LEVEL_HIGH>; | |
f30fb03d SG |
166 | interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; |
167 | #dma-cells = <1>; | |
168 | dma-channels = <4>; | |
8888f651 | 169 | clocks = <&clks IMX6QDL_CLK_APBH_DMA>; |
e5d0f9f5 HS |
170 | }; |
171 | ||
df5cc9d0 | 172 | gpmi: gpmi-nand@112000 { |
0e87e043 SG |
173 | compatible = "fsl,imx6q-gpmi-nand"; |
174 | #address-cells = <1>; | |
175 | #size-cells = <1>; | |
176 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; | |
177 | reg-names = "gpmi-nand", "bch"; | |
275c08b5 | 178 | interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; |
c7aa12a6 | 179 | interrupt-names = "bch"; |
8888f651 SG |
180 | clocks = <&clks IMX6QDL_CLK_GPMI_IO>, |
181 | <&clks IMX6QDL_CLK_GPMI_APB>, | |
182 | <&clks IMX6QDL_CLK_GPMI_BCH>, | |
183 | <&clks IMX6QDL_CLK_GPMI_BCH_APB>, | |
184 | <&clks IMX6QDL_CLK_PER1_BCH>; | |
0e87e043 SG |
185 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", |
186 | "gpmi_bch_apb", "per1_bch"; | |
f30fb03d SG |
187 | dmas = <&dma_apbh 0>; |
188 | dma-names = "rx-tx"; | |
0e87e043 | 189 | status = "disabled"; |
cf922fa8 HS |
190 | }; |
191 | ||
df5cc9d0 | 192 | hdmi: hdmi@120000 { |
ac4af82b LS |
193 | #address-cells = <1>; |
194 | #size-cells = <0>; | |
195 | reg = <0x00120000 0x9000>; | |
196 | interrupts = <0 115 0x04>; | |
197 | gpr = <&gpr>; | |
198 | clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, | |
199 | <&clks IMX6QDL_CLK_HDMI_ISFR>; | |
200 | clock-names = "iahb", "isfr"; | |
201 | status = "disabled"; | |
202 | ||
203 | port@0 { | |
204 | reg = <0>; | |
205 | ||
206 | hdmi_mux_0: endpoint { | |
207 | remote-endpoint = <&ipu1_di0_hdmi>; | |
208 | }; | |
209 | }; | |
210 | ||
211 | port@1 { | |
212 | reg = <1>; | |
213 | ||
214 | hdmi_mux_1: endpoint { | |
215 | remote-endpoint = <&ipu1_di1_hdmi>; | |
216 | }; | |
217 | }; | |
218 | }; | |
219 | ||
df5cc9d0 | 220 | gpu_3d: gpu@130000 { |
419e202b LS |
221 | compatible = "vivante,gc"; |
222 | reg = <0x00130000 0x4000>; | |
223 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; | |
224 | clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, | |
225 | <&clks IMX6QDL_CLK_GPU3D_CORE>, | |
226 | <&clks IMX6QDL_CLK_GPU3D_SHADER>; | |
227 | clock-names = "bus", "core", "shader"; | |
e761b82e | 228 | power-domains = <&pd_pu>; |
4951c2da | 229 | #cooling-cells = <2>; |
419e202b LS |
230 | }; |
231 | ||
df5cc9d0 | 232 | gpu_2d: gpu@134000 { |
419e202b LS |
233 | compatible = "vivante,gc"; |
234 | reg = <0x00134000 0x4000>; | |
235 | interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; | |
236 | clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, | |
237 | <&clks IMX6QDL_CLK_GPU2D_CORE>; | |
238 | clock-names = "bus", "core"; | |
e761b82e | 239 | power-domains = <&pd_pu>; |
4951c2da | 240 | #cooling-cells = <2>; |
419e202b LS |
241 | }; |
242 | ||
df5cc9d0 | 243 | timer@a00600 { |
58458e03 MZ |
244 | compatible = "arm,cortex-a9-twd-timer"; |
245 | reg = <0x00a00600 0x20>; | |
246 | interrupts = <1 13 0xf01>; | |
b923ff6a | 247 | interrupt-parent = <&intc>; |
8888f651 | 248 | clocks = <&clks IMX6QDL_CLK_TWD>; |
7d740f87 SG |
249 | }; |
250 | ||
df5cc9d0 | 251 | intc: interrupt-controller@a01000 { |
67157882 LS |
252 | compatible = "arm,cortex-a9-gic"; |
253 | #interrupt-cells = <3>; | |
254 | interrupt-controller; | |
255 | reg = <0x00a01000 0x1000>, | |
256 | <0x00a00100 0x100>; | |
257 | interrupt-parent = <&intc>; | |
258 | }; | |
259 | ||
df5cc9d0 | 260 | L2: l2-cache@a02000 { |
7d740f87 SG |
261 | compatible = "arm,pl310-cache"; |
262 | reg = <0x00a02000 0x1000>; | |
275c08b5 | 263 | interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
264 | cache-unified; |
265 | cache-level = <2>; | |
5a5ca56e DB |
266 | arm,tag-latency = <4 2 3>; |
267 | arm,data-latency = <4 2 3>; | |
74332d75 | 268 | arm,shared-override; |
7d740f87 SG |
269 | }; |
270 | ||
3e1b8577 | 271 | pcie: pcie@1ffc000 { |
3a57291f | 272 | compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; |
fcd17303 LS |
273 | reg = <0x01ffc000 0x04000>, |
274 | <0x01f00000 0x80000>; | |
275 | reg-names = "dbi", "config"; | |
3a57291f SC |
276 | #address-cells = <3>; |
277 | #size-cells = <2>; | |
278 | device_type = "pci"; | |
3e1b8577 | 279 | bus-range = <0x00 0xff>; |
d9cf0a12 | 280 | ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ |
3a57291f SC |
281 | 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ |
282 | num-lanes = <1>; | |
87fd3ce2 | 283 | num-viewport = <4>; |
92a7eb7c LS |
284 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
285 | interrupt-names = "msi"; | |
07134a36 LS |
286 | #interrupt-cells = <1>; |
287 | interrupt-map-mask = <0 0 0 0x7>; | |
1a9fa190 | 288 | interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
bf5393c5 JT |
289 | <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, |
290 | <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
291 | <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; | |
8888f651 SG |
292 | clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, |
293 | <&clks IMX6QDL_CLK_LVDS1_GATE>, | |
294 | <&clks IMX6QDL_CLK_PCIE_REF_125M>; | |
92a7eb7c | 295 | clock-names = "pcie", "pcie_bus", "pcie_phy"; |
3a57291f SC |
296 | status = "disabled"; |
297 | }; | |
298 | ||
df5cc9d0 | 299 | aips-bus@2000000 { /* AIPS1 */ |
7d740f87 SG |
300 | compatible = "fsl,aips-bus", "simple-bus"; |
301 | #address-cells = <1>; | |
302 | #size-cells = <1>; | |
303 | reg = <0x02000000 0x100000>; | |
304 | ranges; | |
305 | ||
df5cc9d0 | 306 | spba-bus@2000000 { |
7d740f87 SG |
307 | compatible = "fsl,spba-bus", "simple-bus"; |
308 | #address-cells = <1>; | |
309 | #size-cells = <1>; | |
310 | reg = <0x02000000 0x40000>; | |
311 | ranges; | |
312 | ||
df5cc9d0 | 313 | spdif: spdif@2004000 { |
c9d96df2 | 314 | compatible = "fsl,imx35-spdif"; |
7d740f87 | 315 | reg = <0x02004000 0x4000>; |
275c08b5 | 316 | interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; |
c9d96df2 FE |
317 | dmas = <&sdma 14 18 0>, |
318 | <&sdma 15 18 0>; | |
319 | dma-names = "rx", "tx"; | |
833f2cbf SW |
320 | clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, |
321 | <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, | |
322 | <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, | |
f065e9e4 | 323 | <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, |
833f2cbf | 324 | <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; |
c9d96df2 FE |
325 | clock-names = "core", "rxtx0", |
326 | "rxtx1", "rxtx2", | |
327 | "rxtx3", "rxtx4", | |
328 | "rxtx5", "rxtx6", | |
09d3059a | 329 | "rxtx7", "spba"; |
c9d96df2 | 330 | status = "disabled"; |
7d740f87 SG |
331 | }; |
332 | ||
5a2ecf0d | 333 | ecspi1: spi@2008000 { |
7d740f87 SG |
334 | #address-cells = <1>; |
335 | #size-cells = <0>; | |
336 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
337 | reg = <0x02008000 0x4000>; | |
275c08b5 | 338 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
339 | clocks = <&clks IMX6QDL_CLK_ECSPI1>, |
340 | <&clks IMX6QDL_CLK_ECSPI1>; | |
0e87e043 | 341 | clock-names = "ipg", "per"; |
dd4b487b | 342 | dmas = <&sdma 3 8 1>, <&sdma 4 8 2>; |
b3810c3d | 343 | dma-names = "rx", "tx"; |
7d740f87 SG |
344 | status = "disabled"; |
345 | }; | |
346 | ||
5a2ecf0d | 347 | ecspi2: spi@200c000 { |
7d740f87 SG |
348 | #address-cells = <1>; |
349 | #size-cells = <0>; | |
350 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
351 | reg = <0x0200c000 0x4000>; | |
275c08b5 | 352 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
353 | clocks = <&clks IMX6QDL_CLK_ECSPI2>, |
354 | <&clks IMX6QDL_CLK_ECSPI2>; | |
0e87e043 | 355 | clock-names = "ipg", "per"; |
dd4b487b | 356 | dmas = <&sdma 5 8 1>, <&sdma 6 8 2>; |
b3810c3d | 357 | dma-names = "rx", "tx"; |
7d740f87 SG |
358 | status = "disabled"; |
359 | }; | |
360 | ||
5a2ecf0d | 361 | ecspi3: spi@2010000 { |
7d740f87 SG |
362 | #address-cells = <1>; |
363 | #size-cells = <0>; | |
364 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
365 | reg = <0x02010000 0x4000>; | |
275c08b5 | 366 | interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
367 | clocks = <&clks IMX6QDL_CLK_ECSPI3>, |
368 | <&clks IMX6QDL_CLK_ECSPI3>; | |
0e87e043 | 369 | clock-names = "ipg", "per"; |
dd4b487b | 370 | dmas = <&sdma 7 8 1>, <&sdma 8 8 2>; |
b3810c3d | 371 | dma-names = "rx", "tx"; |
7d740f87 SG |
372 | status = "disabled"; |
373 | }; | |
374 | ||
5a2ecf0d | 375 | ecspi4: spi@2014000 { |
7d740f87 SG |
376 | #address-cells = <1>; |
377 | #size-cells = <0>; | |
378 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
379 | reg = <0x02014000 0x4000>; | |
275c08b5 | 380 | interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
381 | clocks = <&clks IMX6QDL_CLK_ECSPI4>, |
382 | <&clks IMX6QDL_CLK_ECSPI4>; | |
0e87e043 | 383 | clock-names = "ipg", "per"; |
dd4b487b | 384 | dmas = <&sdma 9 8 1>, <&sdma 10 8 2>; |
b3810c3d | 385 | dma-names = "rx", "tx"; |
7d740f87 SG |
386 | status = "disabled"; |
387 | }; | |
388 | ||
df5cc9d0 | 389 | uart1: serial@2020000 { |
7d740f87 SG |
390 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
391 | reg = <0x02020000 0x4000>; | |
275c08b5 | 392 | interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
393 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
394 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 395 | clock-names = "ipg", "per"; |
72a5cebf HS |
396 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; |
397 | dma-names = "rx", "tx"; | |
7d740f87 SG |
398 | status = "disabled"; |
399 | }; | |
400 | ||
df5cc9d0 | 401 | esai: esai@2024000 { |
97dae859 SW |
402 | #sound-dai-cells = <0>; |
403 | compatible = "fsl,imx35-esai"; | |
7d740f87 | 404 | reg = <0x02024000 0x4000>; |
275c08b5 | 405 | interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; |
97dae859 SW |
406 | clocks = <&clks IMX6QDL_CLK_ESAI_IPG>, |
407 | <&clks IMX6QDL_CLK_ESAI_MEM>, | |
408 | <&clks IMX6QDL_CLK_ESAI_EXTAL>, | |
409 | <&clks IMX6QDL_CLK_ESAI_IPG>, | |
410 | <&clks IMX6QDL_CLK_SPBA>; | |
09d3059a | 411 | clock-names = "core", "mem", "extal", "fsys", "spba"; |
97dae859 SW |
412 | dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; |
413 | dma-names = "rx", "tx"; | |
414 | status = "disabled"; | |
7d740f87 SG |
415 | }; |
416 | ||
df5cc9d0 | 417 | ssi1: ssi@2028000 { |
6ff7f51e | 418 | #sound-dai-cells = <0>; |
98ea6ad2 | 419 | compatible = "fsl,imx6q-ssi", |
4c03527e | 420 | "fsl,imx51-ssi"; |
7d740f87 | 421 | reg = <0x02028000 0x4000>; |
275c08b5 | 422 | interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; |
935632e9 SW |
423 | clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, |
424 | <&clks IMX6QDL_CLK_SSI1>; | |
425 | clock-names = "ipg", "baud"; | |
5da826ab SG |
426 | dmas = <&sdma 37 1 0>, |
427 | <&sdma 38 1 0>; | |
428 | dma-names = "rx", "tx"; | |
b1a5da8e | 429 | fsl,fifo-depth = <15>; |
b1a5da8e | 430 | status = "disabled"; |
7d740f87 SG |
431 | }; |
432 | ||
df5cc9d0 | 433 | ssi2: ssi@202c000 { |
6ff7f51e | 434 | #sound-dai-cells = <0>; |
98ea6ad2 | 435 | compatible = "fsl,imx6q-ssi", |
4c03527e | 436 | "fsl,imx51-ssi"; |
7d740f87 | 437 | reg = <0x0202c000 0x4000>; |
275c08b5 | 438 | interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; |
935632e9 SW |
439 | clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, |
440 | <&clks IMX6QDL_CLK_SSI2>; | |
441 | clock-names = "ipg", "baud"; | |
5da826ab SG |
442 | dmas = <&sdma 41 1 0>, |
443 | <&sdma 42 1 0>; | |
444 | dma-names = "rx", "tx"; | |
b1a5da8e | 445 | fsl,fifo-depth = <15>; |
b1a5da8e | 446 | status = "disabled"; |
7d740f87 SG |
447 | }; |
448 | ||
df5cc9d0 | 449 | ssi3: ssi@2030000 { |
6ff7f51e | 450 | #sound-dai-cells = <0>; |
98ea6ad2 | 451 | compatible = "fsl,imx6q-ssi", |
4c03527e | 452 | "fsl,imx51-ssi"; |
7d740f87 | 453 | reg = <0x02030000 0x4000>; |
275c08b5 | 454 | interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; |
935632e9 SW |
455 | clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, |
456 | <&clks IMX6QDL_CLK_SSI3>; | |
457 | clock-names = "ipg", "baud"; | |
5da826ab SG |
458 | dmas = <&sdma 45 1 0>, |
459 | <&sdma 46 1 0>; | |
460 | dma-names = "rx", "tx"; | |
b1a5da8e | 461 | fsl,fifo-depth = <15>; |
b1a5da8e | 462 | status = "disabled"; |
7d740f87 SG |
463 | }; |
464 | ||
df5cc9d0 | 465 | asrc: asrc@2034000 { |
97dae859 | 466 | compatible = "fsl,imx53-asrc"; |
7d740f87 | 467 | reg = <0x02034000 0x4000>; |
275c08b5 | 468 | interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; |
97dae859 SW |
469 | clocks = <&clks IMX6QDL_CLK_ASRC_IPG>, |
470 | <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>, | |
471 | <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, | |
472 | <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, | |
473 | <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, | |
474 | <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>, | |
475 | <&clks IMX6QDL_CLK_SPBA>; | |
476 | clock-names = "mem", "ipg", "asrck_0", | |
477 | "asrck_1", "asrck_2", "asrck_3", "asrck_4", | |
478 | "asrck_5", "asrck_6", "asrck_7", "asrck_8", | |
479 | "asrck_9", "asrck_a", "asrck_b", "asrck_c", | |
09d3059a | 480 | "asrck_d", "asrck_e", "asrck_f", "spba"; |
97dae859 SW |
481 | dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, |
482 | <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; | |
483 | dma-names = "rxa", "rxb", "rxc", | |
484 | "txa", "txb", "txc"; | |
485 | fsl,asrc-rate = <48000>; | |
486 | fsl,asrc-width = <16>; | |
487 | status = "okay"; | |
7d740f87 SG |
488 | }; |
489 | ||
df5cc9d0 | 490 | spba@203c000 { |
7d740f87 SG |
491 | reg = <0x0203c000 0x4000>; |
492 | }; | |
493 | }; | |
494 | ||
df5cc9d0 | 495 | vpu: vpu@2040000 { |
a04a0b6f | 496 | compatible = "cnm,coda960"; |
7d740f87 | 497 | reg = <0x02040000 0x3c000>; |
b2faf1a1 PZ |
498 | interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, |
499 | <0 3 IRQ_TYPE_LEVEL_HIGH>; | |
a04a0b6f PZ |
500 | interrupt-names = "bit", "jpeg"; |
501 | clocks = <&clks IMX6QDL_CLK_VPU_AXI>, | |
c9997ba2 FE |
502 | <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; |
503 | clock-names = "per", "ahb"; | |
e761b82e | 504 | power-domains = <&pd_pu>; |
a04a0b6f PZ |
505 | resets = <&src 1>; |
506 | iram = <&ocram>; | |
7d740f87 SG |
507 | }; |
508 | ||
df5cc9d0 | 509 | aipstz@207c000 { /* AIPSTZ1 */ |
7d740f87 SG |
510 | reg = <0x0207c000 0x4000>; |
511 | }; | |
512 | ||
df5cc9d0 | 513 | pwm1: pwm@2080000 { |
33b38587 SH |
514 | #pwm-cells = <2>; |
515 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 | 516 | reg = <0x02080000 0x4000>; |
275c08b5 | 517 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
518 | clocks = <&clks IMX6QDL_CLK_IPG>, |
519 | <&clks IMX6QDL_CLK_PWM1>; | |
33b38587 | 520 | clock-names = "ipg", "per"; |
e2675266 | 521 | status = "disabled"; |
7d740f87 SG |
522 | }; |
523 | ||
df5cc9d0 | 524 | pwm2: pwm@2084000 { |
33b38587 SH |
525 | #pwm-cells = <2>; |
526 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 | 527 | reg = <0x02084000 0x4000>; |
275c08b5 | 528 | interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
529 | clocks = <&clks IMX6QDL_CLK_IPG>, |
530 | <&clks IMX6QDL_CLK_PWM2>; | |
33b38587 | 531 | clock-names = "ipg", "per"; |
e2675266 | 532 | status = "disabled"; |
7d740f87 SG |
533 | }; |
534 | ||
df5cc9d0 | 535 | pwm3: pwm@2088000 { |
33b38587 SH |
536 | #pwm-cells = <2>; |
537 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 | 538 | reg = <0x02088000 0x4000>; |
275c08b5 | 539 | interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
540 | clocks = <&clks IMX6QDL_CLK_IPG>, |
541 | <&clks IMX6QDL_CLK_PWM3>; | |
33b38587 | 542 | clock-names = "ipg", "per"; |
e2675266 | 543 | status = "disabled"; |
7d740f87 SG |
544 | }; |
545 | ||
df5cc9d0 | 546 | pwm4: pwm@208c000 { |
33b38587 SH |
547 | #pwm-cells = <2>; |
548 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 | 549 | reg = <0x0208c000 0x4000>; |
275c08b5 | 550 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
551 | clocks = <&clks IMX6QDL_CLK_IPG>, |
552 | <&clks IMX6QDL_CLK_PWM4>; | |
33b38587 | 553 | clock-names = "ipg", "per"; |
e2675266 | 554 | status = "disabled"; |
7d740f87 SG |
555 | }; |
556 | ||
df5cc9d0 | 557 | can1: flexcan@2090000 { |
0f225212 | 558 | compatible = "fsl,imx6q-flexcan"; |
7d740f87 | 559 | reg = <0x02090000 0x4000>; |
275c08b5 | 560 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
561 | clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, |
562 | <&clks IMX6QDL_CLK_CAN1_SERIAL>; | |
0f225212 | 563 | clock-names = "ipg", "per"; |
d2463e86 | 564 | fsl,stop-mode = <&gpr 0x34 28 0x10 17>; |
a1135337 | 565 | status = "disabled"; |
7d740f87 SG |
566 | }; |
567 | ||
df5cc9d0 | 568 | can2: flexcan@2094000 { |
0f225212 | 569 | compatible = "fsl,imx6q-flexcan"; |
7d740f87 | 570 | reg = <0x02094000 0x4000>; |
275c08b5 | 571 | interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
572 | clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, |
573 | <&clks IMX6QDL_CLK_CAN2_SERIAL>; | |
0f225212 | 574 | clock-names = "ipg", "per"; |
d2463e86 | 575 | fsl,stop-mode = <&gpr 0x34 29 0x10 18>; |
a1135337 | 576 | status = "disabled"; |
7d740f87 SG |
577 | }; |
578 | ||
df5cc9d0 | 579 | gpt: gpt@2098000 { |
97b108f9 | 580 | compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; |
7d740f87 | 581 | reg = <0x02098000 0x4000>; |
275c08b5 | 582 | interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 583 | clocks = <&clks IMX6QDL_CLK_GPT_IPG>, |
2b2244a3 AH |
584 | <&clks IMX6QDL_CLK_GPT_IPG_PER>, |
585 | <&clks IMX6QDL_CLK_GPT_3M>; | |
586 | clock-names = "ipg", "per", "osc_per"; | |
7d740f87 SG |
587 | }; |
588 | ||
df5cc9d0 | 589 | gpio1: gpio@209c000 { |
aeb27748 | 590 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 591 | reg = <0x0209c000 0x4000>; |
275c08b5 TK |
592 | interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, |
593 | <0 67 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
594 | gpio-controller; |
595 | #gpio-cells = <2>; | |
596 | interrupt-controller; | |
88cde8b7 | 597 | #interrupt-cells = <2>; |
7d740f87 SG |
598 | }; |
599 | ||
df5cc9d0 | 600 | gpio2: gpio@20a0000 { |
aeb27748 | 601 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 602 | reg = <0x020a0000 0x4000>; |
275c08b5 TK |
603 | interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, |
604 | <0 69 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
605 | gpio-controller; |
606 | #gpio-cells = <2>; | |
607 | interrupt-controller; | |
88cde8b7 | 608 | #interrupt-cells = <2>; |
7d740f87 SG |
609 | }; |
610 | ||
df5cc9d0 | 611 | gpio3: gpio@20a4000 { |
aeb27748 | 612 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 613 | reg = <0x020a4000 0x4000>; |
275c08b5 TK |
614 | interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, |
615 | <0 71 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
616 | gpio-controller; |
617 | #gpio-cells = <2>; | |
618 | interrupt-controller; | |
88cde8b7 | 619 | #interrupt-cells = <2>; |
7d740f87 SG |
620 | }; |
621 | ||
df5cc9d0 | 622 | gpio4: gpio@20a8000 { |
aeb27748 | 623 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 624 | reg = <0x020a8000 0x4000>; |
275c08b5 TK |
625 | interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, |
626 | <0 73 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
627 | gpio-controller; |
628 | #gpio-cells = <2>; | |
629 | interrupt-controller; | |
88cde8b7 | 630 | #interrupt-cells = <2>; |
7d740f87 SG |
631 | }; |
632 | ||
df5cc9d0 | 633 | gpio5: gpio@20ac000 { |
aeb27748 | 634 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 635 | reg = <0x020ac000 0x4000>; |
275c08b5 TK |
636 | interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, |
637 | <0 75 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
638 | gpio-controller; |
639 | #gpio-cells = <2>; | |
640 | interrupt-controller; | |
88cde8b7 | 641 | #interrupt-cells = <2>; |
7d740f87 SG |
642 | }; |
643 | ||
df5cc9d0 | 644 | gpio6: gpio@20b0000 { |
aeb27748 | 645 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 646 | reg = <0x020b0000 0x4000>; |
275c08b5 TK |
647 | interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, |
648 | <0 77 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
649 | gpio-controller; |
650 | #gpio-cells = <2>; | |
651 | interrupt-controller; | |
88cde8b7 | 652 | #interrupt-cells = <2>; |
7d740f87 SG |
653 | }; |
654 | ||
df5cc9d0 | 655 | gpio7: gpio@20b4000 { |
aeb27748 | 656 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 657 | reg = <0x020b4000 0x4000>; |
275c08b5 TK |
658 | interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, |
659 | <0 79 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
660 | gpio-controller; |
661 | #gpio-cells = <2>; | |
662 | interrupt-controller; | |
88cde8b7 | 663 | #interrupt-cells = <2>; |
7d740f87 SG |
664 | }; |
665 | ||
df5cc9d0 | 666 | kpp: kpp@20b8000 { |
36d3a8f0 | 667 | compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; |
7d740f87 | 668 | reg = <0x020b8000 0x4000>; |
275c08b5 | 669 | interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 670 | clocks = <&clks IMX6QDL_CLK_IPG>; |
1b6f2368 | 671 | status = "disabled"; |
7d740f87 SG |
672 | }; |
673 | ||
df5cc9d0 | 674 | wdog1: wdog@20bc000 { |
7d740f87 SG |
675 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
676 | reg = <0x020bc000 0x4000>; | |
275c08b5 | 677 | interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 678 | clocks = <&clks IMX6QDL_CLK_DUMMY>; |
7d740f87 SG |
679 | }; |
680 | ||
df5cc9d0 | 681 | wdog2: wdog@20c0000 { |
7d740f87 SG |
682 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
683 | reg = <0x020c0000 0x4000>; | |
275c08b5 | 684 | interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 685 | clocks = <&clks IMX6QDL_CLK_DUMMY>; |
7d740f87 SG |
686 | status = "disabled"; |
687 | }; | |
688 | ||
df5cc9d0 | 689 | clks: ccm@20c4000 { |
7d740f87 SG |
690 | compatible = "fsl,imx6q-ccm"; |
691 | reg = <0x020c4000 0x4000>; | |
275c08b5 TK |
692 | interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, |
693 | <0 88 IRQ_TYPE_LEVEL_HIGH>; | |
0e87e043 | 694 | #clock-cells = <1>; |
7d740f87 SG |
695 | }; |
696 | ||
df5cc9d0 | 697 | anatop: anatop@20c8000 { |
baa64151 | 698 | compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; |
7d740f87 | 699 | reg = <0x020c8000 0x1000>; |
275c08b5 TK |
700 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, |
701 | <0 54 IRQ_TYPE_LEVEL_HIGH>, | |
702 | <0 127 IRQ_TYPE_LEVEL_HIGH>; | |
a1e327e6 | 703 | |
71db3948 | 704 | regulator-1p1 { |
a1e327e6 YCLP |
705 | compatible = "fsl,anatop-regulator"; |
706 | regulator-name = "vdd1p1"; | |
ecbf5e70 LS |
707 | regulator-min-microvolt = <1000000>; |
708 | regulator-max-microvolt = <1200000>; | |
a1e327e6 YCLP |
709 | regulator-always-on; |
710 | anatop-reg-offset = <0x110>; | |
711 | anatop-vol-bit-shift = <8>; | |
712 | anatop-vol-bit-width = <5>; | |
713 | anatop-min-bit-val = <4>; | |
714 | anatop-min-voltage = <800000>; | |
715 | anatop-max-voltage = <1375000>; | |
38281a47 | 716 | anatop-enable-bit = <0>; |
a1e327e6 YCLP |
717 | }; |
718 | ||
71db3948 | 719 | regulator-3p0 { |
a1e327e6 YCLP |
720 | compatible = "fsl,anatop-regulator"; |
721 | regulator-name = "vdd3p0"; | |
722 | regulator-min-microvolt = <2800000>; | |
723 | regulator-max-microvolt = <3150000>; | |
724 | regulator-always-on; | |
725 | anatop-reg-offset = <0x120>; | |
726 | anatop-vol-bit-shift = <8>; | |
727 | anatop-vol-bit-width = <5>; | |
728 | anatop-min-bit-val = <0>; | |
729 | anatop-min-voltage = <2625000>; | |
730 | anatop-max-voltage = <3400000>; | |
38281a47 | 731 | anatop-enable-bit = <0>; |
a1e327e6 YCLP |
732 | }; |
733 | ||
71db3948 | 734 | regulator-2p5 { |
a1e327e6 YCLP |
735 | compatible = "fsl,anatop-regulator"; |
736 | regulator-name = "vdd2p5"; | |
ecbf5e70 | 737 | regulator-min-microvolt = <2250000>; |
a1e327e6 YCLP |
738 | regulator-max-microvolt = <2750000>; |
739 | regulator-always-on; | |
740 | anatop-reg-offset = <0x130>; | |
741 | anatop-vol-bit-shift = <8>; | |
742 | anatop-vol-bit-width = <5>; | |
743 | anatop-min-bit-val = <0>; | |
993051b2 LS |
744 | anatop-min-voltage = <2100000>; |
745 | anatop-max-voltage = <2875000>; | |
38281a47 | 746 | anatop-enable-bit = <0>; |
a1e327e6 YCLP |
747 | }; |
748 | ||
71db3948 | 749 | reg_arm: regulator-vddcore { |
a1e327e6 | 750 | compatible = "fsl,anatop-regulator"; |
118c98a6 | 751 | regulator-name = "vddarm"; |
a1e327e6 YCLP |
752 | regulator-min-microvolt = <725000>; |
753 | regulator-max-microvolt = <1450000>; | |
754 | regulator-always-on; | |
755 | anatop-reg-offset = <0x140>; | |
756 | anatop-vol-bit-shift = <0>; | |
757 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
758 | anatop-delay-reg-offset = <0x170>; |
759 | anatop-delay-bit-shift = <24>; | |
760 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
761 | anatop-min-bit-val = <1>; |
762 | anatop-min-voltage = <725000>; | |
763 | anatop-max-voltage = <1450000>; | |
764 | }; | |
765 | ||
71db3948 | 766 | reg_pu: regulator-vddpu { |
a1e327e6 YCLP |
767 | compatible = "fsl,anatop-regulator"; |
768 | regulator-name = "vddpu"; | |
769 | regulator-min-microvolt = <725000>; | |
770 | regulator-max-microvolt = <1450000>; | |
40130d32 | 771 | regulator-enable-ramp-delay = <150>; |
a1e327e6 YCLP |
772 | anatop-reg-offset = <0x140>; |
773 | anatop-vol-bit-shift = <9>; | |
774 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
775 | anatop-delay-reg-offset = <0x170>; |
776 | anatop-delay-bit-shift = <26>; | |
777 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
778 | anatop-min-bit-val = <1>; |
779 | anatop-min-voltage = <725000>; | |
780 | anatop-max-voltage = <1450000>; | |
781 | }; | |
782 | ||
71db3948 | 783 | reg_soc: regulator-vddsoc { |
a1e327e6 YCLP |
784 | compatible = "fsl,anatop-regulator"; |
785 | regulator-name = "vddsoc"; | |
786 | regulator-min-microvolt = <725000>; | |
787 | regulator-max-microvolt = <1450000>; | |
788 | regulator-always-on; | |
789 | anatop-reg-offset = <0x140>; | |
790 | anatop-vol-bit-shift = <18>; | |
791 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
792 | anatop-delay-reg-offset = <0x170>; |
793 | anatop-delay-bit-shift = <28>; | |
794 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
795 | anatop-min-bit-val = <1>; |
796 | anatop-min-voltage = <725000>; | |
797 | anatop-max-voltage = <1450000>; | |
798 | }; | |
7d740f87 SG |
799 | }; |
800 | ||
df5cc9d0 | 801 | usbphy1: usbphy@20c9000 { |
74bd88f7 | 802 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; |
7d740f87 | 803 | reg = <0x020c9000 0x1000>; |
275c08b5 | 804 | interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 805 | clocks = <&clks IMX6QDL_CLK_USBPHY1>; |
76a38855 | 806 | fsl,anatop = <&anatop>; |
7d740f87 SG |
807 | }; |
808 | ||
df5cc9d0 | 809 | usbphy2: usbphy@20ca000 { |
74bd88f7 | 810 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; |
7d740f87 | 811 | reg = <0x020ca000 0x1000>; |
275c08b5 | 812 | interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 813 | clocks = <&clks IMX6QDL_CLK_USBPHY2>; |
76a38855 | 814 | fsl,anatop = <&anatop>; |
7d740f87 SG |
815 | }; |
816 | ||
df5cc9d0 | 817 | snvs: snvs@20cc000 { |
95d739b5 FL |
818 | compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; |
819 | reg = <0x020cc000 0x4000>; | |
c9250388 | 820 | |
95d739b5 | 821 | snvs_rtc: snvs-rtc-lp { |
c9250388 | 822 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
95d739b5 FL |
823 | regmap = <&snvs>; |
824 | offset = <0x34>; | |
275c08b5 TK |
825 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, |
826 | <0 20 IRQ_TYPE_LEVEL_HIGH>; | |
c9250388 | 827 | }; |
422b0676 | 828 | |
95d739b5 FL |
829 | snvs_poweroff: snvs-poweroff { |
830 | compatible = "syscon-poweroff"; | |
831 | regmap = <&snvs>; | |
832 | offset = <0x38>; | |
87a84c62 | 833 | value = <0x60>; |
95d739b5 | 834 | mask = <0x60>; |
422b0676 RG |
835 | status = "disabled"; |
836 | }; | |
a53745d1 | 837 | |
768b525e AF |
838 | snvs_pwrkey: snvs-powerkey { |
839 | compatible = "fsl,sec-v4.0-pwrkey"; | |
840 | regmap = <&snvs>; | |
841 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
842 | linux,keycode = <KEY_POWER>; | |
843 | wakeup-source; | |
844 | }; | |
845 | ||
a53745d1 OR |
846 | snvs_lpgpr: snvs-lpgpr { |
847 | compatible = "fsl,imx6q-snvs-lpgpr"; | |
848 | }; | |
7d740f87 SG |
849 | }; |
850 | ||
df5cc9d0 | 851 | epit1: epit@20d0000 { /* EPIT1 */ |
7d740f87 | 852 | reg = <0x020d0000 0x4000>; |
275c08b5 | 853 | interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
854 | }; |
855 | ||
df5cc9d0 | 856 | epit2: epit@20d4000 { /* EPIT2 */ |
7d740f87 | 857 | reg = <0x020d4000 0x4000>; |
275c08b5 | 858 | interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
859 | }; |
860 | ||
df5cc9d0 | 861 | src: src@20d8000 { |
bd3d924d | 862 | compatible = "fsl,imx6q-src", "fsl,imx51-src"; |
7d740f87 | 863 | reg = <0x020d8000 0x4000>; |
275c08b5 TK |
864 | interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, |
865 | <0 96 IRQ_TYPE_LEVEL_HIGH>; | |
09ebf366 | 866 | #reset-cells = <1>; |
7d740f87 SG |
867 | }; |
868 | ||
df5cc9d0 | 869 | gpc: gpc@20dc000 { |
7d740f87 SG |
870 | compatible = "fsl,imx6q-gpc"; |
871 | reg = <0x020dc000 0x4000>; | |
b923ff6a MZ |
872 | interrupt-controller; |
873 | #interrupt-cells = <3>; | |
275c08b5 TK |
874 | interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, |
875 | <0 90 IRQ_TYPE_LEVEL_HIGH>; | |
b923ff6a | 876 | interrupt-parent = <&intc>; |
e761b82e LS |
877 | clocks = <&clks IMX6QDL_CLK_IPG>; |
878 | clock-names = "ipg"; | |
879 | ||
880 | pgc { | |
881 | #address-cells = <1>; | |
882 | #size-cells = <0>; | |
883 | ||
884 | power-domain@0 { | |
885 | reg = <0>; | |
886 | #power-domain-cells = <0>; | |
887 | }; | |
888 | pd_pu: power-domain@1 { | |
889 | reg = <1>; | |
890 | #power-domain-cells = <0>; | |
891 | power-supply = <®_pu>; | |
892 | clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, | |
893 | <&clks IMX6QDL_CLK_GPU3D_SHADER>, | |
894 | <&clks IMX6QDL_CLK_GPU2D_CORE>, | |
895 | <&clks IMX6QDL_CLK_GPU2D_AXI>, | |
896 | <&clks IMX6QDL_CLK_OPENVG_AXI>, | |
897 | <&clks IMX6QDL_CLK_VPU_AXI>; | |
898 | }; | |
899 | }; | |
7d740f87 SG |
900 | }; |
901 | ||
df5cc9d0 | 902 | gpr: iomuxc-gpr@20e0000 { |
bc97e88e | 903 | compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; |
df5cc9d0 | 904 | reg = <0x20e0000 0x38>; |
bc97e88e PZ |
905 | |
906 | mux: mux-controller { | |
907 | compatible = "mmio-mux"; | |
908 | #mux-control-cells = <1>; | |
909 | }; | |
df37e0c0 DA |
910 | }; |
911 | ||
df5cc9d0 | 912 | iomuxc: iomuxc@20e0000 { |
c56009b2 | 913 | compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; |
df5cc9d0 | 914 | reg = <0x20e0000 0x4000>; |
c56009b2 SG |
915 | }; |
916 | ||
df5cc9d0 | 917 | dcic1: dcic@20e4000 { |
7d740f87 | 918 | reg = <0x020e4000 0x4000>; |
275c08b5 | 919 | interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
920 | }; |
921 | ||
df5cc9d0 | 922 | dcic2: dcic@20e8000 { |
7d740f87 | 923 | reg = <0x020e8000 0x4000>; |
275c08b5 | 924 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
925 | }; |
926 | ||
df5cc9d0 | 927 | sdma: sdma@20ec000 { |
7d740f87 SG |
928 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
929 | reg = <0x020ec000 0x4000>; | |
275c08b5 | 930 | interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; |
b14c872e | 931 | clocks = <&clks IMX6QDL_CLK_IPG>, |
8888f651 | 932 | <&clks IMX6QDL_CLK_SDMA>; |
0e87e043 | 933 | clock-names = "ipg", "ahb"; |
fb72bb21 | 934 | #dma-cells = <3>; |
d6b9c591 | 935 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
7d740f87 SG |
936 | }; |
937 | }; | |
938 | ||
df5cc9d0 | 939 | aips-bus@2100000 { /* AIPS2 */ |
7d740f87 SG |
940 | compatible = "fsl,aips-bus", "simple-bus"; |
941 | #address-cells = <1>; | |
942 | #size-cells = <1>; | |
943 | reg = <0x02100000 0x100000>; | |
944 | ranges; | |
945 | ||
d462ce99 VM |
946 | crypto: caam@2100000 { |
947 | compatible = "fsl,sec-v4.0"; | |
d462ce99 VM |
948 | #address-cells = <1>; |
949 | #size-cells = <1>; | |
950 | reg = <0x2100000 0x10000>; | |
951 | ranges = <0 0x2100000 0x10000>; | |
d462ce99 VM |
952 | clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, |
953 | <&clks IMX6QDL_CLK_CAAM_ACLK>, | |
954 | <&clks IMX6QDL_CLK_CAAM_IPG>, | |
955 | <&clks IMX6QDL_CLK_EIM_SLOW>; | |
956 | clock-names = "mem", "aclk", "ipg", "emi_slow"; | |
957 | ||
958 | sec_jr0: jr0@1000 { | |
959 | compatible = "fsl,sec-v4.0-job-ring"; | |
960 | reg = <0x1000 0x1000>; | |
961 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; | |
962 | }; | |
963 | ||
964 | sec_jr1: jr1@2000 { | |
965 | compatible = "fsl,sec-v4.0-job-ring"; | |
966 | reg = <0x2000 0x1000>; | |
967 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; | |
968 | }; | |
7d740f87 SG |
969 | }; |
970 | ||
df5cc9d0 | 971 | aipstz@217c000 { /* AIPSTZ2 */ |
7d740f87 SG |
972 | reg = <0x0217c000 0x4000>; |
973 | }; | |
974 | ||
df5cc9d0 | 975 | usbotg: usb@2184000 { |
74bd88f7 RZ |
976 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
977 | reg = <0x02184000 0x200>; | |
275c08b5 | 978 | interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 979 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
74bd88f7 | 980 | fsl,usbphy = <&usbphy1>; |
28342c61 | 981 | fsl,usbmisc = <&usbmisc 0>; |
9493bf54 | 982 | ahb-burst-config = <0x0>; |
2b1a40e8 PC |
983 | tx-burst-size-dword = <0x10>; |
984 | rx-burst-size-dword = <0x10>; | |
74bd88f7 RZ |
985 | status = "disabled"; |
986 | }; | |
987 | ||
df5cc9d0 | 988 | usbh1: usb@2184200 { |
74bd88f7 RZ |
989 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
990 | reg = <0x02184200 0x200>; | |
275c08b5 | 991 | interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 992 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
74bd88f7 | 993 | fsl,usbphy = <&usbphy2>; |
28342c61 | 994 | fsl,usbmisc = <&usbmisc 1>; |
3ec481ed | 995 | dr_mode = "host"; |
9493bf54 | 996 | ahb-burst-config = <0x0>; |
2b1a40e8 PC |
997 | tx-burst-size-dword = <0x10>; |
998 | rx-burst-size-dword = <0x10>; | |
74bd88f7 RZ |
999 | status = "disabled"; |
1000 | }; | |
1001 | ||
df5cc9d0 | 1002 | usbh2: usb@2184400 { |
74bd88f7 RZ |
1003 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
1004 | reg = <0x02184400 0x200>; | |
275c08b5 | 1005 | interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 1006 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
4ca7dbdb FS |
1007 | fsl,usbphy = <&usbphynop1>; |
1008 | phy_type = "hsic"; | |
28342c61 | 1009 | fsl,usbmisc = <&usbmisc 2>; |
3ec481ed | 1010 | dr_mode = "host"; |
9493bf54 | 1011 | ahb-burst-config = <0x0>; |
2b1a40e8 PC |
1012 | tx-burst-size-dword = <0x10>; |
1013 | rx-burst-size-dword = <0x10>; | |
74bd88f7 RZ |
1014 | status = "disabled"; |
1015 | }; | |
1016 | ||
df5cc9d0 | 1017 | usbh3: usb@2184600 { |
74bd88f7 RZ |
1018 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
1019 | reg = <0x02184600 0x200>; | |
275c08b5 | 1020 | interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 1021 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
4ca7dbdb FS |
1022 | fsl,usbphy = <&usbphynop2>; |
1023 | phy_type = "hsic"; | |
28342c61 | 1024 | fsl,usbmisc = <&usbmisc 3>; |
3ec481ed | 1025 | dr_mode = "host"; |
9493bf54 | 1026 | ahb-burst-config = <0x0>; |
2b1a40e8 PC |
1027 | tx-burst-size-dword = <0x10>; |
1028 | rx-burst-size-dword = <0x10>; | |
74bd88f7 RZ |
1029 | status = "disabled"; |
1030 | }; | |
1031 | ||
df5cc9d0 | 1032 | usbmisc: usbmisc@2184800 { |
28342c61 RZ |
1033 | #index-cells = <1>; |
1034 | compatible = "fsl,imx6q-usbmisc"; | |
1035 | reg = <0x02184800 0x200>; | |
8888f651 | 1036 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
28342c61 RZ |
1037 | }; |
1038 | ||
df5cc9d0 | 1039 | fec: ethernet@2188000 { |
7d740f87 SG |
1040 | compatible = "fsl,imx6q-fec"; |
1041 | reg = <0x02188000 0x4000>; | |
e94a2309 | 1042 | interrupt-names = "int0", "pps"; |
454cf8f5 TK |
1043 | interrupts-extended = |
1044 | <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, | |
1045 | <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; | |
8888f651 SG |
1046 | clocks = <&clks IMX6QDL_CLK_ENET>, |
1047 | <&clks IMX6QDL_CLK_ENET>, | |
1048 | <&clks IMX6QDL_CLK_ENET_REF>; | |
7629838c | 1049 | clock-names = "ipg", "ahb", "ptp"; |
7d740f87 SG |
1050 | status = "disabled"; |
1051 | }; | |
1052 | ||
df5cc9d0 | 1053 | mlb@218c000 { |
7d740f87 | 1054 | reg = <0x0218c000 0x4000>; |
275c08b5 TK |
1055 | interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, |
1056 | <0 117 IRQ_TYPE_LEVEL_HIGH>, | |
1057 | <0 126 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
1058 | }; |
1059 | ||
df5cc9d0 | 1060 | usdhc1: usdhc@2190000 { |
7d740f87 SG |
1061 | compatible = "fsl,imx6q-usdhc"; |
1062 | reg = <0x02190000 0x4000>; | |
275c08b5 | 1063 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1064 | clocks = <&clks IMX6QDL_CLK_USDHC1>, |
1065 | <&clks IMX6QDL_CLK_USDHC1>, | |
1066 | <&clks IMX6QDL_CLK_USDHC1>; | |
0e87e043 | 1067 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 1068 | bus-width = <4>; |
7d740f87 SG |
1069 | status = "disabled"; |
1070 | }; | |
1071 | ||
df5cc9d0 | 1072 | usdhc2: usdhc@2194000 { |
7d740f87 SG |
1073 | compatible = "fsl,imx6q-usdhc"; |
1074 | reg = <0x02194000 0x4000>; | |
275c08b5 | 1075 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1076 | clocks = <&clks IMX6QDL_CLK_USDHC2>, |
1077 | <&clks IMX6QDL_CLK_USDHC2>, | |
1078 | <&clks IMX6QDL_CLK_USDHC2>; | |
0e87e043 | 1079 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 1080 | bus-width = <4>; |
7d740f87 SG |
1081 | status = "disabled"; |
1082 | }; | |
1083 | ||
df5cc9d0 | 1084 | usdhc3: usdhc@2198000 { |
7d740f87 SG |
1085 | compatible = "fsl,imx6q-usdhc"; |
1086 | reg = <0x02198000 0x4000>; | |
275c08b5 | 1087 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1088 | clocks = <&clks IMX6QDL_CLK_USDHC3>, |
1089 | <&clks IMX6QDL_CLK_USDHC3>, | |
1090 | <&clks IMX6QDL_CLK_USDHC3>; | |
0e87e043 | 1091 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 1092 | bus-width = <4>; |
7d740f87 SG |
1093 | status = "disabled"; |
1094 | }; | |
1095 | ||
df5cc9d0 | 1096 | usdhc4: usdhc@219c000 { |
7d740f87 SG |
1097 | compatible = "fsl,imx6q-usdhc"; |
1098 | reg = <0x0219c000 0x4000>; | |
275c08b5 | 1099 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1100 | clocks = <&clks IMX6QDL_CLK_USDHC4>, |
1101 | <&clks IMX6QDL_CLK_USDHC4>, | |
1102 | <&clks IMX6QDL_CLK_USDHC4>; | |
0e87e043 | 1103 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 1104 | bus-width = <4>; |
7d740f87 SG |
1105 | status = "disabled"; |
1106 | }; | |
1107 | ||
df5cc9d0 | 1108 | i2c1: i2c@21a0000 { |
7d740f87 SG |
1109 | #address-cells = <1>; |
1110 | #size-cells = <0>; | |
5bdfba29 | 1111 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 | 1112 | reg = <0x021a0000 0x4000>; |
275c08b5 | 1113 | interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 1114 | clocks = <&clks IMX6QDL_CLK_I2C1>; |
7d740f87 SG |
1115 | status = "disabled"; |
1116 | }; | |
1117 | ||
df5cc9d0 | 1118 | i2c2: i2c@21a4000 { |
7d740f87 SG |
1119 | #address-cells = <1>; |
1120 | #size-cells = <0>; | |
5bdfba29 | 1121 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 | 1122 | reg = <0x021a4000 0x4000>; |
275c08b5 | 1123 | interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 1124 | clocks = <&clks IMX6QDL_CLK_I2C2>; |
7d740f87 SG |
1125 | status = "disabled"; |
1126 | }; | |
1127 | ||
df5cc9d0 | 1128 | i2c3: i2c@21a8000 { |
7d740f87 SG |
1129 | #address-cells = <1>; |
1130 | #size-cells = <0>; | |
5bdfba29 | 1131 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 | 1132 | reg = <0x021a8000 0x4000>; |
275c08b5 | 1133 | interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 1134 | clocks = <&clks IMX6QDL_CLK_I2C3>; |
7d740f87 SG |
1135 | status = "disabled"; |
1136 | }; | |
1137 | ||
df5cc9d0 | 1138 | romcp@21ac000 { |
7d740f87 SG |
1139 | reg = <0x021ac000 0x4000>; |
1140 | }; | |
1141 | ||
476f6e53 | 1142 | mmdc0: memory-controller@21b0000 { /* MMDC0 */ |
7d740f87 SG |
1143 | compatible = "fsl,imx6q-mmdc"; |
1144 | reg = <0x021b0000 0x4000>; | |
39db0e13 | 1145 | clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; |
7d740f87 SG |
1146 | }; |
1147 | ||
476f6e53 | 1148 | mmdc1: memory-controller@21b4000 { /* MMDC1 */ |
3a1a67b1 | 1149 | compatible = "fsl,imx6q-mmdc"; |
7d740f87 | 1150 | reg = <0x021b4000 0x4000>; |
3a1a67b1 | 1151 | status = "disabled"; |
7d740f87 SG |
1152 | }; |
1153 | ||
df5cc9d0 | 1154 | weim: weim@21b8000 { |
1be81ea5 JC |
1155 | #address-cells = <2>; |
1156 | #size-cells = <1>; | |
05e3f8e7 | 1157 | compatible = "fsl,imx6q-weim"; |
7d740f87 | 1158 | reg = <0x021b8000 0x4000>; |
275c08b5 | 1159 | interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 1160 | clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; |
1be81ea5 | 1161 | fsl,weim-cs-gpr = <&gpr>; |
116dad7d | 1162 | status = "disabled"; |
7d740f87 SG |
1163 | }; |
1164 | ||
df5cc9d0 | 1165 | ocotp: ocotp@21bc000 { |
3fe6373b | 1166 | compatible = "fsl,imx6q-ocotp", "syscon"; |
7d740f87 | 1167 | reg = <0x021bc000 0x4000>; |
b8ecd889 | 1168 | clocks = <&clks IMX6QDL_CLK_IIM>; |
7d740f87 SG |
1169 | }; |
1170 | ||
df5cc9d0 | 1171 | tzasc@21d0000 { /* TZASC1 */ |
7d740f87 | 1172 | reg = <0x021d0000 0x4000>; |
275c08b5 | 1173 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
1174 | }; |
1175 | ||
df5cc9d0 | 1176 | tzasc@21d4000 { /* TZASC2 */ |
7d740f87 | 1177 | reg = <0x021d4000 0x4000>; |
275c08b5 | 1178 | interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
1179 | }; |
1180 | ||
df5cc9d0 | 1181 | audmux: audmux@21d8000 { |
f965cd55 | 1182 | compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; |
7d740f87 | 1183 | reg = <0x021d8000 0x4000>; |
f965cd55 | 1184 | status = "disabled"; |
7d740f87 SG |
1185 | }; |
1186 | ||
df5cc9d0 | 1187 | mipi_csi: mipi@21dc000 { |
b0cb1bd4 | 1188 | compatible = "fsl,imx6-mipi-csi2"; |
7d740f87 | 1189 | reg = <0x021dc000 0x4000>; |
2539f517 PZ |
1190 | #address-cells = <1>; |
1191 | #size-cells = <0>; | |
b0cb1bd4 SL |
1192 | interrupts = <0 100 0x04>, <0 101 0x04>; |
1193 | clocks = <&clks IMX6QDL_CLK_HSI_TX>, | |
1194 | <&clks IMX6QDL_CLK_VIDEO_27M>, | |
1195 | <&clks IMX6QDL_CLK_EIM_PODF>; | |
1196 | clock-names = "dphy", "ref", "pix"; | |
1197 | status = "disabled"; | |
7d740f87 SG |
1198 | }; |
1199 | ||
df5cc9d0 | 1200 | mipi_dsi: mipi@21e0000 { |
7d740f87 | 1201 | reg = <0x021e0000 0x4000>; |
4520e692 PZ |
1202 | status = "disabled"; |
1203 | ||
70c2652c LY |
1204 | ports { |
1205 | #address-cells = <1>; | |
1206 | #size-cells = <0>; | |
1207 | ||
1208 | port@0 { | |
1209 | reg = <0>; | |
4520e692 | 1210 | |
70c2652c LY |
1211 | mipi_mux_0: endpoint { |
1212 | remote-endpoint = <&ipu1_di0_mipi>; | |
1213 | }; | |
4520e692 | 1214 | }; |
4520e692 | 1215 | |
70c2652c LY |
1216 | port@1 { |
1217 | reg = <1>; | |
4520e692 | 1218 | |
70c2652c LY |
1219 | mipi_mux_1: endpoint { |
1220 | remote-endpoint = <&ipu1_di1_mipi>; | |
1221 | }; | |
4520e692 PZ |
1222 | }; |
1223 | }; | |
7d740f87 SG |
1224 | }; |
1225 | ||
df5cc9d0 | 1226 | vdoa@21e4000 { |
67c59006 | 1227 | compatible = "fsl,imx6q-vdoa"; |
7d740f87 | 1228 | reg = <0x021e4000 0x4000>; |
275c08b5 | 1229 | interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; |
67c59006 | 1230 | clocks = <&clks IMX6QDL_CLK_VDOA>; |
7d740f87 SG |
1231 | }; |
1232 | ||
df5cc9d0 | 1233 | uart2: serial@21e8000 { |
7d740f87 SG |
1234 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1235 | reg = <0x021e8000 0x4000>; | |
275c08b5 | 1236 | interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1237 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
1238 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 1239 | clock-names = "ipg", "per"; |
72a5cebf HS |
1240 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; |
1241 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1242 | status = "disabled"; |
1243 | }; | |
1244 | ||
df5cc9d0 | 1245 | uart3: serial@21ec000 { |
7d740f87 SG |
1246 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1247 | reg = <0x021ec000 0x4000>; | |
275c08b5 | 1248 | interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1249 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
1250 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 1251 | clock-names = "ipg", "per"; |
72a5cebf HS |
1252 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; |
1253 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1254 | status = "disabled"; |
1255 | }; | |
1256 | ||
df5cc9d0 | 1257 | uart4: serial@21f0000 { |
7d740f87 SG |
1258 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1259 | reg = <0x021f0000 0x4000>; | |
275c08b5 | 1260 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1261 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
1262 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 1263 | clock-names = "ipg", "per"; |
72a5cebf HS |
1264 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; |
1265 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1266 | status = "disabled"; |
1267 | }; | |
1268 | ||
df5cc9d0 | 1269 | uart5: serial@21f4000 { |
7d740f87 SG |
1270 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1271 | reg = <0x021f4000 0x4000>; | |
275c08b5 | 1272 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1273 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
1274 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 1275 | clock-names = "ipg", "per"; |
72a5cebf HS |
1276 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; |
1277 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1278 | status = "disabled"; |
1279 | }; | |
1280 | }; | |
91660d74 | 1281 | |
df5cc9d0 | 1282 | ipu1: ipu@2400000 { |
4520e692 PZ |
1283 | #address-cells = <1>; |
1284 | #size-cells = <0>; | |
91660d74 SH |
1285 | compatible = "fsl,imx6q-ipu"; |
1286 | reg = <0x02400000 0x400000>; | |
275c08b5 TK |
1287 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, |
1288 | <0 5 IRQ_TYPE_LEVEL_HIGH>; | |
8888f651 SG |
1289 | clocks = <&clks IMX6QDL_CLK_IPU1>, |
1290 | <&clks IMX6QDL_CLK_IPU1_DI0>, | |
1291 | <&clks IMX6QDL_CLK_IPU1_DI1>; | |
91660d74 | 1292 | clock-names = "bus", "di0", "di1"; |
09ebf366 | 1293 | resets = <&src 2>; |
4520e692 | 1294 | |
c0470c38 PZ |
1295 | ipu1_csi0: port@0 { |
1296 | reg = <0>; | |
2539f517 PZ |
1297 | |
1298 | ipu1_csi0_from_ipu1_csi0_mux: endpoint { | |
1299 | remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>; | |
1300 | }; | |
c0470c38 PZ |
1301 | }; |
1302 | ||
1303 | ipu1_csi1: port@1 { | |
1304 | reg = <1>; | |
1305 | }; | |
1306 | ||
4520e692 PZ |
1307 | ipu1_di0: port@2 { |
1308 | #address-cells = <1>; | |
1309 | #size-cells = <0>; | |
1310 | reg = <2>; | |
1311 | ||
f457be77 RH |
1312 | ipu1_di0_disp0: endpoint@0 { |
1313 | reg = <0>; | |
4520e692 PZ |
1314 | }; |
1315 | ||
f457be77 RH |
1316 | ipu1_di0_hdmi: endpoint@1 { |
1317 | reg = <1>; | |
4520e692 PZ |
1318 | remote-endpoint = <&hdmi_mux_0>; |
1319 | }; | |
1320 | ||
f457be77 RH |
1321 | ipu1_di0_mipi: endpoint@2 { |
1322 | reg = <2>; | |
4520e692 PZ |
1323 | remote-endpoint = <&mipi_mux_0>; |
1324 | }; | |
1325 | ||
f457be77 RH |
1326 | ipu1_di0_lvds0: endpoint@3 { |
1327 | reg = <3>; | |
4520e692 PZ |
1328 | remote-endpoint = <&lvds0_mux_0>; |
1329 | }; | |
1330 | ||
f457be77 RH |
1331 | ipu1_di0_lvds1: endpoint@4 { |
1332 | reg = <4>; | |
4520e692 PZ |
1333 | remote-endpoint = <&lvds1_mux_0>; |
1334 | }; | |
1335 | }; | |
1336 | ||
1337 | ipu1_di1: port@3 { | |
1338 | #address-cells = <1>; | |
1339 | #size-cells = <0>; | |
1340 | reg = <3>; | |
1341 | ||
f457be77 RH |
1342 | ipu1_di1_disp1: endpoint@0 { |
1343 | reg = <0>; | |
4520e692 PZ |
1344 | }; |
1345 | ||
f457be77 RH |
1346 | ipu1_di1_hdmi: endpoint@1 { |
1347 | reg = <1>; | |
4520e692 PZ |
1348 | remote-endpoint = <&hdmi_mux_1>; |
1349 | }; | |
1350 | ||
f457be77 RH |
1351 | ipu1_di1_mipi: endpoint@2 { |
1352 | reg = <2>; | |
4520e692 PZ |
1353 | remote-endpoint = <&mipi_mux_1>; |
1354 | }; | |
1355 | ||
f457be77 RH |
1356 | ipu1_di1_lvds0: endpoint@3 { |
1357 | reg = <3>; | |
4520e692 PZ |
1358 | remote-endpoint = <&lvds0_mux_1>; |
1359 | }; | |
1360 | ||
f457be77 RH |
1361 | ipu1_di1_lvds1: endpoint@4 { |
1362 | reg = <4>; | |
4520e692 PZ |
1363 | remote-endpoint = <&lvds1_mux_1>; |
1364 | }; | |
1365 | }; | |
91660d74 | 1366 | }; |
7d740f87 SG |
1367 | }; |
1368 | }; |