projects / mirror_ubuntu-zesty-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 7d740f87 SG |
1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
| 3 | * Copyright 2011 Linaro Ltd. | |
| 4 | * | |
| 5 | * The code contained herein is licensed under the GNU General Public | |
| 6 | * License. You may obtain a copy of the GNU General Public License | |
| 7 | * Version 2 or later at the following locations: | |
| 8 | * | |
| 9 | * http://www.opensource.org/licenses/gpl-license.html | |
| 10 | * http://www.gnu.org/copyleft/gpl.html | |
| 11 | */ | |
| 12 | ||
| 8888f651 | 13 | #include <dt-bindings/clock/imx6qdl-clock.h> |
| 07134a36 LS |
14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 15 | ||
| 36dffd8f | 16 | #include "skeleton.dtsi" |
| 7d740f87 SG |
17 | |
| 18 | / { | |
| 19 | aliases { | |
| 22970070 | 20 | ethernet0 = &fec; |
| 5f8fbc2c LW |
21 | can0 = &can1; |
| 22 | can1 = &can2; | |
| 5230f8fe SG |
23 | gpio0 = &gpio1; |
| 24 | gpio1 = &gpio2; | |
| 25 | gpio2 = &gpio3; | |
| 26 | gpio3 = &gpio4; | |
| 27 | gpio4 = &gpio5; | |
| 28 | gpio5 = &gpio6; | |
| 29 | gpio6 = &gpio7; | |
| 80fa0584 SH |
30 | i2c0 = &i2c1; |
| 31 | i2c1 = &i2c2; | |
| 32 | i2c2 = &i2c3; | |
| fb06d65c SH |
33 | mmc0 = &usdhc1; |
| 34 | mmc1 = &usdhc2; | |
| 35 | mmc2 = &usdhc3; | |
| 36 | mmc3 = &usdhc4; | |
| 80fa0584 SH |
37 | serial0 = &uart1; |
| 38 | serial1 = &uart2; | |
| 39 | serial2 = &uart3; | |
| 40 | serial3 = &uart4; | |
| 41 | serial4 = &uart5; | |
| 42 | spi0 = &ecspi1; | |
| 43 | spi1 = &ecspi2; | |
| 44 | spi2 = &ecspi3; | |
| 45 | spi3 = &ecspi4; | |
| 8189c51f PC |
46 | usbphy0 = &usbphy1; |
| 47 | usbphy1 = &usbphy2; | |
| 7d740f87 SG |
48 | }; |
| 49 | ||
| 7d740f87 SG |
50 | intc: interrupt-controller@00a01000 { |
| 51 | compatible = "arm,cortex-a9-gic"; | |
| 52 | #interrupt-cells = <3>; | |
| 7d740f87 SG |
53 | interrupt-controller; |
| 54 | reg = <0x00a01000 0x1000>, | |
| 55 | <0x00a00100 0x100>; | |
| 56 | }; | |
| 57 | ||
| 58 | clocks { | |
| 59 | #address-cells = <1>; | |
| 60 | #size-cells = <0>; | |
| 61 | ||
| 62 | ckil { | |
| 63 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
| 4b2b4043 | 64 | #clock-cells = <0>; |
| 7d740f87 SG |
65 | clock-frequency = <32768>; |
| 66 | }; | |
| 67 | ||
| 68 | ckih1 { | |
| 69 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
| 4b2b4043 | 70 | #clock-cells = <0>; |
| 7d740f87 SG |
71 | clock-frequency = <0>; |
| 72 | }; | |
| 73 | ||
| 74 | osc { | |
| 75 | compatible = "fsl,imx-osc", "fixed-clock"; | |
| 4b2b4043 | 76 | #clock-cells = <0>; |
| 7d740f87 SG |
77 | clock-frequency = <24000000>; |
| 78 | }; | |
| 79 | }; | |
| 80 | ||
| 81 | soc { | |
| 82 | #address-cells = <1>; | |
| 83 | #size-cells = <1>; | |
| 84 | compatible = "simple-bus"; | |
| 85 | interrupt-parent = <&intc>; | |
| 86 | ranges; | |
| 87 | ||
| f30fb03d | 88 | dma_apbh: dma-apbh@00110000 { |
| e5d0f9f5 HS |
89 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; |
| 90 | reg = <0x00110000 0x2000>; | |
| 275c08b5 TK |
91 | interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, |
| 92 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
| 93 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
| 94 | <0 13 IRQ_TYPE_LEVEL_HIGH>; | |
| f30fb03d SG |
95 | interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; |
| 96 | #dma-cells = <1>; | |
| 97 | dma-channels = <4>; | |
| 8888f651 | 98 | clocks = <&clks IMX6QDL_CLK_APBH_DMA>; |
| e5d0f9f5 HS |
99 | }; |
| 100 | ||
| be4ccfce | 101 | gpmi: gpmi-nand@00112000 { |
| 0e87e043 SG |
102 | compatible = "fsl,imx6q-gpmi-nand"; |
| 103 | #address-cells = <1>; | |
| 104 | #size-cells = <1>; | |
| 105 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; | |
| 106 | reg-names = "gpmi-nand", "bch"; | |
| 275c08b5 | 107 | interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; |
| c7aa12a6 | 108 | interrupt-names = "bch"; |
| 8888f651 SG |
109 | clocks = <&clks IMX6QDL_CLK_GPMI_IO>, |
| 110 | <&clks IMX6QDL_CLK_GPMI_APB>, | |
| 111 | <&clks IMX6QDL_CLK_GPMI_BCH>, | |
| 112 | <&clks IMX6QDL_CLK_GPMI_BCH_APB>, | |
| 113 | <&clks IMX6QDL_CLK_PER1_BCH>; | |
| 0e87e043 SG |
114 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", |
| 115 | "gpmi_bch_apb", "per1_bch"; | |
| f30fb03d SG |
116 | dmas = <&dma_apbh 0>; |
| 117 | dma-names = "rx-tx"; | |
| 0e87e043 | 118 | status = "disabled"; |
| cf922fa8 HS |
119 | }; |
| 120 | ||
| 7d740f87 | 121 | timer@00a00600 { |
| 58458e03 MZ |
122 | compatible = "arm,cortex-a9-twd-timer"; |
| 123 | reg = <0x00a00600 0x20>; | |
| 124 | interrupts = <1 13 0xf01>; | |
| 8888f651 | 125 | clocks = <&clks IMX6QDL_CLK_TWD>; |
| 7d740f87 SG |
126 | }; |
| 127 | ||
| 128 | L2: l2-cache@00a02000 { | |
| 129 | compatible = "arm,pl310-cache"; | |
| 130 | reg = <0x00a02000 0x1000>; | |
| 275c08b5 | 131 | interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
132 | cache-unified; |
| 133 | cache-level = <2>; | |
| 5a5ca56e DB |
134 | arm,tag-latency = <4 2 3>; |
| 135 | arm,data-latency = <4 2 3>; | |
| 7d740f87 SG |
136 | }; |
| 137 | ||
| 3a57291f SC |
138 | pcie: pcie@0x01000000 { |
| 139 | compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; | |
| fcd17303 LS |
140 | reg = <0x01ffc000 0x04000>, |
| 141 | <0x01f00000 0x80000>; | |
| 142 | reg-names = "dbi", "config"; | |
| 3a57291f SC |
143 | #address-cells = <3>; |
| 144 | #size-cells = <2>; | |
| 145 | device_type = "pci"; | |
| 146 | ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ | |
| 147 | 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ | |
| 148 | 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ | |
| 149 | num-lanes = <1>; | |
| 92a7eb7c LS |
150 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
| 151 | interrupt-names = "msi"; | |
| 07134a36 LS |
152 | #interrupt-cells = <1>; |
| 153 | interrupt-map-mask = <0 0 0 0x7>; | |
| 154 | interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, | |
| 155 | <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, | |
| 156 | <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
| 157 | <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; | |
| 8888f651 SG |
158 | clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, |
| 159 | <&clks IMX6QDL_CLK_LVDS1_GATE>, | |
| 160 | <&clks IMX6QDL_CLK_PCIE_REF_125M>; | |
| 92a7eb7c | 161 | clock-names = "pcie", "pcie_bus", "pcie_phy"; |
| 3a57291f SC |
162 | status = "disabled"; |
| 163 | }; | |
| 164 | ||
| 218abe6f DB |
165 | pmu { |
| 166 | compatible = "arm,cortex-a9-pmu"; | |
| 275c08b5 | 167 | interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; |
| 218abe6f DB |
168 | }; |
| 169 | ||
| 7d740f87 SG |
170 | aips-bus@02000000 { /* AIPS1 */ |
| 171 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 172 | #address-cells = <1>; | |
| 173 | #size-cells = <1>; | |
| 174 | reg = <0x02000000 0x100000>; | |
| 175 | ranges; | |
| 176 | ||
| 177 | spba-bus@02000000 { | |
| 178 | compatible = "fsl,spba-bus", "simple-bus"; | |
| 179 | #address-cells = <1>; | |
| 180 | #size-cells = <1>; | |
| 181 | reg = <0x02000000 0x40000>; | |
| 182 | ranges; | |
| 183 | ||
| 7b7d6727 | 184 | spdif: spdif@02004000 { |
| c9d96df2 | 185 | compatible = "fsl,imx35-spdif"; |
| 7d740f87 | 186 | reg = <0x02004000 0x4000>; |
| 275c08b5 | 187 | interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; |
| c9d96df2 FE |
188 | dmas = <&sdma 14 18 0>, |
| 189 | <&sdma 15 18 0>; | |
| 190 | dma-names = "rx", "tx"; | |
| 8888f651 SG |
191 | clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>, |
| 192 | <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>, | |
| 193 | <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, | |
| 194 | <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, | |
| 195 | <&clks IMX6QDL_CLK_DUMMY>; | |
| c9d96df2 FE |
196 | clock-names = "core", "rxtx0", |
| 197 | "rxtx1", "rxtx2", | |
| 198 | "rxtx3", "rxtx4", | |
| 199 | "rxtx5", "rxtx6", | |
| 200 | "rxtx7"; | |
| 201 | status = "disabled"; | |
| 7d740f87 SG |
202 | }; |
| 203 | ||
| 7b7d6727 | 204 | ecspi1: ecspi@02008000 { |
| 7d740f87 SG |
205 | #address-cells = <1>; |
| 206 | #size-cells = <0>; | |
| 207 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
| 208 | reg = <0x02008000 0x4000>; | |
| 275c08b5 | 209 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
210 | clocks = <&clks IMX6QDL_CLK_ECSPI1>, |
| 211 | <&clks IMX6QDL_CLK_ECSPI1>; | |
| 0e87e043 | 212 | clock-names = "ipg", "per"; |
| b3810c3d FL |
213 | dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; |
| 214 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
215 | status = "disabled"; |
| 216 | }; | |
| 217 | ||
| 7b7d6727 | 218 | ecspi2: ecspi@0200c000 { |
| 7d740f87 SG |
219 | #address-cells = <1>; |
| 220 | #size-cells = <0>; | |
| 221 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
| 222 | reg = <0x0200c000 0x4000>; | |
| 275c08b5 | 223 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
224 | clocks = <&clks IMX6QDL_CLK_ECSPI2>, |
| 225 | <&clks IMX6QDL_CLK_ECSPI2>; | |
| 0e87e043 | 226 | clock-names = "ipg", "per"; |
| b3810c3d FL |
227 | dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; |
| 228 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
229 | status = "disabled"; |
| 230 | }; | |
| 231 | ||
| 7b7d6727 | 232 | ecspi3: ecspi@02010000 { |
| 7d740f87 SG |
233 | #address-cells = <1>; |
| 234 | #size-cells = <0>; | |
| 235 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
| 236 | reg = <0x02010000 0x4000>; | |
| 275c08b5 | 237 | interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
238 | clocks = <&clks IMX6QDL_CLK_ECSPI3>, |
| 239 | <&clks IMX6QDL_CLK_ECSPI3>; | |
| 0e87e043 | 240 | clock-names = "ipg", "per"; |
| b3810c3d FL |
241 | dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; |
| 242 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
243 | status = "disabled"; |
| 244 | }; | |
| 245 | ||
| 7b7d6727 | 246 | ecspi4: ecspi@02014000 { |
| 7d740f87 SG |
247 | #address-cells = <1>; |
| 248 | #size-cells = <0>; | |
| 249 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
| 250 | reg = <0x02014000 0x4000>; | |
| 275c08b5 | 251 | interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
252 | clocks = <&clks IMX6QDL_CLK_ECSPI4>, |
| 253 | <&clks IMX6QDL_CLK_ECSPI4>; | |
| 0e87e043 | 254 | clock-names = "ipg", "per"; |
| b3810c3d FL |
255 | dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; |
| 256 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
257 | status = "disabled"; |
| 258 | }; | |
| 259 | ||
| 0c456cfa | 260 | uart1: serial@02020000 { |
| 7d740f87 SG |
261 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 262 | reg = <0x02020000 0x4000>; | |
| 275c08b5 | 263 | interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
264 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
| 265 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
| 0e87e043 | 266 | clock-names = "ipg", "per"; |
| 72a5cebf HS |
267 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; |
| 268 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
269 | status = "disabled"; |
| 270 | }; | |
| 271 | ||
| 7b7d6727 | 272 | esai: esai@02024000 { |
| 7d740f87 | 273 | reg = <0x02024000 0x4000>; |
| 275c08b5 | 274 | interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
275 | }; |
| 276 | ||
| b1a5da8e | 277 | ssi1: ssi@02028000 { |
| 6ff7f51e | 278 | #sound-dai-cells = <0>; |
| 98ea6ad2 | 279 | compatible = "fsl,imx6q-ssi", |
| 4c03527e | 280 | "fsl,imx51-ssi"; |
| 7d740f87 | 281 | reg = <0x02028000 0x4000>; |
| 275c08b5 | 282 | interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; |
| 935632e9 SW |
283 | clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, |
| 284 | <&clks IMX6QDL_CLK_SSI1>; | |
| 285 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
286 | dmas = <&sdma 37 1 0>, |
| 287 | <&sdma 38 1 0>; | |
| 288 | dma-names = "rx", "tx"; | |
| b1a5da8e | 289 | fsl,fifo-depth = <15>; |
| b1a5da8e | 290 | status = "disabled"; |
| 7d740f87 SG |
291 | }; |
| 292 | ||
| b1a5da8e | 293 | ssi2: ssi@0202c000 { |
| 6ff7f51e | 294 | #sound-dai-cells = <0>; |
| 98ea6ad2 | 295 | compatible = "fsl,imx6q-ssi", |
| 4c03527e | 296 | "fsl,imx51-ssi"; |
| 7d740f87 | 297 | reg = <0x0202c000 0x4000>; |
| 275c08b5 | 298 | interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; |
| 935632e9 SW |
299 | clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, |
| 300 | <&clks IMX6QDL_CLK_SSI2>; | |
| 301 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
302 | dmas = <&sdma 41 1 0>, |
| 303 | <&sdma 42 1 0>; | |
| 304 | dma-names = "rx", "tx"; | |
| b1a5da8e | 305 | fsl,fifo-depth = <15>; |
| b1a5da8e | 306 | status = "disabled"; |
| 7d740f87 SG |
307 | }; |
| 308 | ||
| b1a5da8e | 309 | ssi3: ssi@02030000 { |
| 6ff7f51e | 310 | #sound-dai-cells = <0>; |
| 98ea6ad2 | 311 | compatible = "fsl,imx6q-ssi", |
| 4c03527e | 312 | "fsl,imx51-ssi"; |
| 7d740f87 | 313 | reg = <0x02030000 0x4000>; |
| 275c08b5 | 314 | interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; |
| 935632e9 SW |
315 | clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, |
| 316 | <&clks IMX6QDL_CLK_SSI3>; | |
| 317 | clock-names = "ipg", "baud"; | |
| 5da826ab SG |
318 | dmas = <&sdma 45 1 0>, |
| 319 | <&sdma 46 1 0>; | |
| 320 | dma-names = "rx", "tx"; | |
| b1a5da8e | 321 | fsl,fifo-depth = <15>; |
| b1a5da8e | 322 | status = "disabled"; |
| 7d740f87 SG |
323 | }; |
| 324 | ||
| 7b7d6727 | 325 | asrc: asrc@02034000 { |
| 7d740f87 | 326 | reg = <0x02034000 0x4000>; |
| 275c08b5 | 327 | interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
328 | }; |
| 329 | ||
| 330 | spba@0203c000 { | |
| 331 | reg = <0x0203c000 0x4000>; | |
| 332 | }; | |
| 333 | }; | |
| 334 | ||
| 7b7d6727 | 335 | vpu: vpu@02040000 { |
| a04a0b6f | 336 | compatible = "cnm,coda960"; |
| 7d740f87 | 337 | reg = <0x02040000 0x3c000>; |
| b2faf1a1 PZ |
338 | interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, |
| 339 | <0 3 IRQ_TYPE_LEVEL_HIGH>; | |
| a04a0b6f PZ |
340 | interrupt-names = "bit", "jpeg"; |
| 341 | clocks = <&clks IMX6QDL_CLK_VPU_AXI>, | |
| c9997ba2 FE |
342 | <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; |
| 343 | clock-names = "per", "ahb"; | |
| a04a0b6f PZ |
344 | resets = <&src 1>; |
| 345 | iram = <&ocram>; | |
| 7d740f87 SG |
346 | }; |
| 347 | ||
| 348 | aipstz@0207c000 { /* AIPSTZ1 */ | |
| 349 | reg = <0x0207c000 0x4000>; | |
| 350 | }; | |
| 351 | ||
| 7b7d6727 | 352 | pwm1: pwm@02080000 { |
| 33b38587 SH |
353 | #pwm-cells = <2>; |
| 354 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
| 7d740f87 | 355 | reg = <0x02080000 0x4000>; |
| 275c08b5 | 356 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
357 | clocks = <&clks IMX6QDL_CLK_IPG>, |
| 358 | <&clks IMX6QDL_CLK_PWM1>; | |
| 33b38587 | 359 | clock-names = "ipg", "per"; |
| 7d740f87 SG |
360 | }; |
| 361 | ||
| 7b7d6727 | 362 | pwm2: pwm@02084000 { |
| 33b38587 SH |
363 | #pwm-cells = <2>; |
| 364 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
| 7d740f87 | 365 | reg = <0x02084000 0x4000>; |
| 275c08b5 | 366 | interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
367 | clocks = <&clks IMX6QDL_CLK_IPG>, |
| 368 | <&clks IMX6QDL_CLK_PWM2>; | |
| 33b38587 | 369 | clock-names = "ipg", "per"; |
| 7d740f87 SG |
370 | }; |
| 371 | ||
| 7b7d6727 | 372 | pwm3: pwm@02088000 { |
| 33b38587 SH |
373 | #pwm-cells = <2>; |
| 374 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
| 7d740f87 | 375 | reg = <0x02088000 0x4000>; |
| 275c08b5 | 376 | interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
377 | clocks = <&clks IMX6QDL_CLK_IPG>, |
| 378 | <&clks IMX6QDL_CLK_PWM3>; | |
| 33b38587 | 379 | clock-names = "ipg", "per"; |
| 7d740f87 SG |
380 | }; |
| 381 | ||
| 7b7d6727 | 382 | pwm4: pwm@0208c000 { |
| 33b38587 SH |
383 | #pwm-cells = <2>; |
| 384 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
| 7d740f87 | 385 | reg = <0x0208c000 0x4000>; |
| 275c08b5 | 386 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
387 | clocks = <&clks IMX6QDL_CLK_IPG>, |
| 388 | <&clks IMX6QDL_CLK_PWM4>; | |
| 33b38587 | 389 | clock-names = "ipg", "per"; |
| 7d740f87 SG |
390 | }; |
| 391 | ||
| 7b7d6727 | 392 | can1: flexcan@02090000 { |
| 0f225212 | 393 | compatible = "fsl,imx6q-flexcan"; |
| 7d740f87 | 394 | reg = <0x02090000 0x4000>; |
| 275c08b5 | 395 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
396 | clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, |
| 397 | <&clks IMX6QDL_CLK_CAN1_SERIAL>; | |
| 0f225212 | 398 | clock-names = "ipg", "per"; |
| a1135337 | 399 | status = "disabled"; |
| 7d740f87 SG |
400 | }; |
| 401 | ||
| 7b7d6727 | 402 | can2: flexcan@02094000 { |
| 0f225212 | 403 | compatible = "fsl,imx6q-flexcan"; |
| 7d740f87 | 404 | reg = <0x02094000 0x4000>; |
| 275c08b5 | 405 | interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
406 | clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, |
| 407 | <&clks IMX6QDL_CLK_CAN2_SERIAL>; | |
| 0f225212 | 408 | clock-names = "ipg", "per"; |
| a1135337 | 409 | status = "disabled"; |
| 7d740f87 SG |
410 | }; |
| 411 | ||
| 7b7d6727 | 412 | gpt: gpt@02098000 { |
| 97b108f9 | 413 | compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; |
| 7d740f87 | 414 | reg = <0x02098000 0x4000>; |
| 275c08b5 | 415 | interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 416 | clocks = <&clks IMX6QDL_CLK_GPT_IPG>, |
| 2b2244a3 AH |
417 | <&clks IMX6QDL_CLK_GPT_IPG_PER>, |
| 418 | <&clks IMX6QDL_CLK_GPT_3M>; | |
| 419 | clock-names = "ipg", "per", "osc_per"; | |
| 7d740f87 SG |
420 | }; |
| 421 | ||
| 4d191868 | 422 | gpio1: gpio@0209c000 { |
| aeb27748 | 423 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 424 | reg = <0x0209c000 0x4000>; |
| 275c08b5 TK |
425 | interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, |
| 426 | <0 67 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
427 | gpio-controller; |
| 428 | #gpio-cells = <2>; | |
| 429 | interrupt-controller; | |
| 88cde8b7 | 430 | #interrupt-cells = <2>; |
| 7d740f87 SG |
431 | }; |
| 432 | ||
| 4d191868 | 433 | gpio2: gpio@020a0000 { |
| aeb27748 | 434 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 435 | reg = <0x020a0000 0x4000>; |
| 275c08b5 TK |
436 | interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, |
| 437 | <0 69 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
438 | gpio-controller; |
| 439 | #gpio-cells = <2>; | |
| 440 | interrupt-controller; | |
| 88cde8b7 | 441 | #interrupt-cells = <2>; |
| 7d740f87 SG |
442 | }; |
| 443 | ||
| 4d191868 | 444 | gpio3: gpio@020a4000 { |
| aeb27748 | 445 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 446 | reg = <0x020a4000 0x4000>; |
| 275c08b5 TK |
447 | interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, |
| 448 | <0 71 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
449 | gpio-controller; |
| 450 | #gpio-cells = <2>; | |
| 451 | interrupt-controller; | |
| 88cde8b7 | 452 | #interrupt-cells = <2>; |
| 7d740f87 SG |
453 | }; |
| 454 | ||
| 4d191868 | 455 | gpio4: gpio@020a8000 { |
| aeb27748 | 456 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 457 | reg = <0x020a8000 0x4000>; |
| 275c08b5 TK |
458 | interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, |
| 459 | <0 73 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
460 | gpio-controller; |
| 461 | #gpio-cells = <2>; | |
| 462 | interrupt-controller; | |
| 88cde8b7 | 463 | #interrupt-cells = <2>; |
| 7d740f87 SG |
464 | }; |
| 465 | ||
| 4d191868 | 466 | gpio5: gpio@020ac000 { |
| aeb27748 | 467 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 468 | reg = <0x020ac000 0x4000>; |
| 275c08b5 TK |
469 | interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, |
| 470 | <0 75 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
471 | gpio-controller; |
| 472 | #gpio-cells = <2>; | |
| 473 | interrupt-controller; | |
| 88cde8b7 | 474 | #interrupt-cells = <2>; |
| 7d740f87 SG |
475 | }; |
| 476 | ||
| 4d191868 | 477 | gpio6: gpio@020b0000 { |
| aeb27748 | 478 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 479 | reg = <0x020b0000 0x4000>; |
| 275c08b5 TK |
480 | interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, |
| 481 | <0 77 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
482 | gpio-controller; |
| 483 | #gpio-cells = <2>; | |
| 484 | interrupt-controller; | |
| 88cde8b7 | 485 | #interrupt-cells = <2>; |
| 7d740f87 SG |
486 | }; |
| 487 | ||
| 4d191868 | 488 | gpio7: gpio@020b4000 { |
| aeb27748 | 489 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
| 7d740f87 | 490 | reg = <0x020b4000 0x4000>; |
| 275c08b5 TK |
491 | interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, |
| 492 | <0 79 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
493 | gpio-controller; |
| 494 | #gpio-cells = <2>; | |
| 495 | interrupt-controller; | |
| 88cde8b7 | 496 | #interrupt-cells = <2>; |
| 7d740f87 SG |
497 | }; |
| 498 | ||
| 7b7d6727 | 499 | kpp: kpp@020b8000 { |
| 36d3a8f0 | 500 | compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; |
| 7d740f87 | 501 | reg = <0x020b8000 0x4000>; |
| 275c08b5 | 502 | interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 503 | clocks = <&clks IMX6QDL_CLK_IPG>; |
| 1b6f2368 | 504 | status = "disabled"; |
| 7d740f87 SG |
505 | }; |
| 506 | ||
| 7b7d6727 | 507 | wdog1: wdog@020bc000 { |
| 7d740f87 SG |
508 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| 509 | reg = <0x020bc000 0x4000>; | |
| 275c08b5 | 510 | interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 511 | clocks = <&clks IMX6QDL_CLK_DUMMY>; |
| 7d740f87 SG |
512 | }; |
| 513 | ||
| 7b7d6727 | 514 | wdog2: wdog@020c0000 { |
| 7d740f87 SG |
515 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
| 516 | reg = <0x020c0000 0x4000>; | |
| 275c08b5 | 517 | interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 518 | clocks = <&clks IMX6QDL_CLK_DUMMY>; |
| 7d740f87 SG |
519 | status = "disabled"; |
| 520 | }; | |
| 521 | ||
| 0e87e043 | 522 | clks: ccm@020c4000 { |
| 7d740f87 SG |
523 | compatible = "fsl,imx6q-ccm"; |
| 524 | reg = <0x020c4000 0x4000>; | |
| 275c08b5 TK |
525 | interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, |
| 526 | <0 88 IRQ_TYPE_LEVEL_HIGH>; | |
| 0e87e043 | 527 | #clock-cells = <1>; |
| 7d740f87 SG |
528 | }; |
| 529 | ||
| baa64151 DA |
530 | anatop: anatop@020c8000 { |
| 531 | compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; | |
| 7d740f87 | 532 | reg = <0x020c8000 0x1000>; |
| 275c08b5 TK |
533 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, |
| 534 | <0 54 IRQ_TYPE_LEVEL_HIGH>, | |
| 535 | <0 127 IRQ_TYPE_LEVEL_HIGH>; | |
| a1e327e6 YCLP |
536 | |
| 537 | regulator-1p1@110 { | |
| 538 | compatible = "fsl,anatop-regulator"; | |
| 539 | regulator-name = "vdd1p1"; | |
| 540 | regulator-min-microvolt = <800000>; | |
| 541 | regulator-max-microvolt = <1375000>; | |
| 542 | regulator-always-on; | |
| 543 | anatop-reg-offset = <0x110>; | |
| 544 | anatop-vol-bit-shift = <8>; | |
| 545 | anatop-vol-bit-width = <5>; | |
| 546 | anatop-min-bit-val = <4>; | |
| 547 | anatop-min-voltage = <800000>; | |
| 548 | anatop-max-voltage = <1375000>; | |
| 549 | }; | |
| 550 | ||
| 551 | regulator-3p0@120 { | |
| 552 | compatible = "fsl,anatop-regulator"; | |
| 553 | regulator-name = "vdd3p0"; | |
| 554 | regulator-min-microvolt = <2800000>; | |
| 555 | regulator-max-microvolt = <3150000>; | |
| 556 | regulator-always-on; | |
| 557 | anatop-reg-offset = <0x120>; | |
| 558 | anatop-vol-bit-shift = <8>; | |
| 559 | anatop-vol-bit-width = <5>; | |
| 560 | anatop-min-bit-val = <0>; | |
| 561 | anatop-min-voltage = <2625000>; | |
| 562 | anatop-max-voltage = <3400000>; | |
| 563 | }; | |
| 564 | ||
| 565 | regulator-2p5@130 { | |
| 566 | compatible = "fsl,anatop-regulator"; | |
| 567 | regulator-name = "vdd2p5"; | |
| 568 | regulator-min-microvolt = <2000000>; | |
| 569 | regulator-max-microvolt = <2750000>; | |
| 570 | regulator-always-on; | |
| 571 | anatop-reg-offset = <0x130>; | |
| 572 | anatop-vol-bit-shift = <8>; | |
| 573 | anatop-vol-bit-width = <5>; | |
| 574 | anatop-min-bit-val = <0>; | |
| 575 | anatop-min-voltage = <2000000>; | |
| 576 | anatop-max-voltage = <2750000>; | |
| 577 | }; | |
| 578 | ||
| 96574a6d | 579 | reg_arm: regulator-vddcore@140 { |
| a1e327e6 | 580 | compatible = "fsl,anatop-regulator"; |
| 118c98a6 | 581 | regulator-name = "vddarm"; |
| a1e327e6 YCLP |
582 | regulator-min-microvolt = <725000>; |
| 583 | regulator-max-microvolt = <1450000>; | |
| 584 | regulator-always-on; | |
| 585 | anatop-reg-offset = <0x140>; | |
| 586 | anatop-vol-bit-shift = <0>; | |
| 587 | anatop-vol-bit-width = <5>; | |
| 46743dd6 AH |
588 | anatop-delay-reg-offset = <0x170>; |
| 589 | anatop-delay-bit-shift = <24>; | |
| 590 | anatop-delay-bit-width = <2>; | |
| a1e327e6 YCLP |
591 | anatop-min-bit-val = <1>; |
| 592 | anatop-min-voltage = <725000>; | |
| 593 | anatop-max-voltage = <1450000>; | |
| 594 | }; | |
| 595 | ||
| 96574a6d | 596 | reg_pu: regulator-vddpu@140 { |
| a1e327e6 YCLP |
597 | compatible = "fsl,anatop-regulator"; |
| 598 | regulator-name = "vddpu"; | |
| 599 | regulator-min-microvolt = <725000>; | |
| 600 | regulator-max-microvolt = <1450000>; | |
| 601 | regulator-always-on; | |
| 602 | anatop-reg-offset = <0x140>; | |
| 603 | anatop-vol-bit-shift = <9>; | |
| 604 | anatop-vol-bit-width = <5>; | |
| 46743dd6 AH |
605 | anatop-delay-reg-offset = <0x170>; |
| 606 | anatop-delay-bit-shift = <26>; | |
| 607 | anatop-delay-bit-width = <2>; | |
| a1e327e6 YCLP |
608 | anatop-min-bit-val = <1>; |
| 609 | anatop-min-voltage = <725000>; | |
| 610 | anatop-max-voltage = <1450000>; | |
| 611 | }; | |
| 612 | ||
| 96574a6d | 613 | reg_soc: regulator-vddsoc@140 { |
| a1e327e6 YCLP |
614 | compatible = "fsl,anatop-regulator"; |
| 615 | regulator-name = "vddsoc"; | |
| 616 | regulator-min-microvolt = <725000>; | |
| 617 | regulator-max-microvolt = <1450000>; | |
| 618 | regulator-always-on; | |
| 619 | anatop-reg-offset = <0x140>; | |
| 620 | anatop-vol-bit-shift = <18>; | |
| 621 | anatop-vol-bit-width = <5>; | |
| 46743dd6 AH |
622 | anatop-delay-reg-offset = <0x170>; |
| 623 | anatop-delay-bit-shift = <28>; | |
| 624 | anatop-delay-bit-width = <2>; | |
| a1e327e6 YCLP |
625 | anatop-min-bit-val = <1>; |
| 626 | anatop-min-voltage = <725000>; | |
| 627 | anatop-max-voltage = <1450000>; | |
| 628 | }; | |
| 7d740f87 SG |
629 | }; |
| 630 | ||
| 3fe6373b SG |
631 | tempmon: tempmon { |
| 632 | compatible = "fsl,imx6q-tempmon"; | |
| 275c08b5 | 633 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; |
| 3fe6373b SG |
634 | fsl,tempmon = <&anatop>; |
| 635 | fsl,tempmon-data = <&ocotp>; | |
| 8888f651 | 636 | clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; |
| 3fe6373b SG |
637 | }; |
| 638 | ||
| 74bd88f7 RZ |
639 | usbphy1: usbphy@020c9000 { |
| 640 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
| 7d740f87 | 641 | reg = <0x020c9000 0x1000>; |
| 275c08b5 | 642 | interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 643 | clocks = <&clks IMX6QDL_CLK_USBPHY1>; |
| 76a38855 | 644 | fsl,anatop = <&anatop>; |
| 7d740f87 SG |
645 | }; |
| 646 | ||
| 74bd88f7 RZ |
647 | usbphy2: usbphy@020ca000 { |
| 648 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
| 7d740f87 | 649 | reg = <0x020ca000 0x1000>; |
| 275c08b5 | 650 | interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 651 | clocks = <&clks IMX6QDL_CLK_USBPHY2>; |
| 76a38855 | 652 | fsl,anatop = <&anatop>; |
| 7d740f87 SG |
653 | }; |
| 654 | ||
| 655 | snvs@020cc000 { | |
| c9250388 SG |
656 | compatible = "fsl,sec-v4.0-mon", "simple-bus"; |
| 657 | #address-cells = <1>; | |
| 658 | #size-cells = <1>; | |
| 659 | ranges = <0 0x020cc000 0x4000>; | |
| 660 | ||
| 661 | snvs-rtc-lp@34 { | |
| 662 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; | |
| 663 | reg = <0x34 0x58>; | |
| 275c08b5 TK |
664 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, |
| 665 | <0 20 IRQ_TYPE_LEVEL_HIGH>; | |
| c9250388 | 666 | }; |
| 422b0676 RG |
667 | |
| 668 | snvs_poweroff: snvs-poweroff@38 { | |
| 669 | compatible = "fsl,sec-v4.0-poweroff"; | |
| 670 | reg = <0x38 0x4>; | |
| 671 | status = "disabled"; | |
| 672 | }; | |
| 7d740f87 SG |
673 | }; |
| 674 | ||
| 7b7d6727 | 675 | epit1: epit@020d0000 { /* EPIT1 */ |
| 7d740f87 | 676 | reg = <0x020d0000 0x4000>; |
| 275c08b5 | 677 | interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
678 | }; |
| 679 | ||
| 7b7d6727 | 680 | epit2: epit@020d4000 { /* EPIT2 */ |
| 7d740f87 | 681 | reg = <0x020d4000 0x4000>; |
| 275c08b5 | 682 | interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
683 | }; |
| 684 | ||
| 7b7d6727 | 685 | src: src@020d8000 { |
| bd3d924d | 686 | compatible = "fsl,imx6q-src", "fsl,imx51-src"; |
| 7d740f87 | 687 | reg = <0x020d8000 0x4000>; |
| 275c08b5 TK |
688 | interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, |
| 689 | <0 96 IRQ_TYPE_LEVEL_HIGH>; | |
| 09ebf366 | 690 | #reset-cells = <1>; |
| 7d740f87 SG |
691 | }; |
| 692 | ||
| 7b7d6727 | 693 | gpc: gpc@020dc000 { |
| 7d740f87 SG |
694 | compatible = "fsl,imx6q-gpc"; |
| 695 | reg = <0x020dc000 0x4000>; | |
| 275c08b5 TK |
696 | interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, |
| 697 | <0 90 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
698 | }; |
| 699 | ||
| df37e0c0 DA |
700 | gpr: iomuxc-gpr@020e0000 { |
| 701 | compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; | |
| 702 | reg = <0x020e0000 0x38>; | |
| 703 | }; | |
| 704 | ||
| c56009b2 SG |
705 | iomuxc: iomuxc@020e0000 { |
| 706 | compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; | |
| 707 | reg = <0x020e0000 0x4000>; | |
| c56009b2 SG |
708 | }; |
| 709 | ||
| 41c04342 ST |
710 | ldb: ldb@020e0008 { |
| 711 | #address-cells = <1>; | |
| 712 | #size-cells = <0>; | |
| 713 | compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; | |
| 714 | gpr = <&gpr>; | |
| 715 | status = "disabled"; | |
| 716 | ||
| 717 | lvds-channel@0 { | |
| 4520e692 PZ |
718 | #address-cells = <1>; |
| 719 | #size-cells = <0>; | |
| 41c04342 | 720 | reg = <0>; |
| 41c04342 | 721 | status = "disabled"; |
| 4520e692 PZ |
722 | |
| 723 | port@0 { | |
| 724 | reg = <0>; | |
| 725 | ||
| 726 | lvds0_mux_0: endpoint { | |
| 727 | remote-endpoint = <&ipu1_di0_lvds0>; | |
| 728 | }; | |
| 729 | }; | |
| 730 | ||
| 731 | port@1 { | |
| 732 | reg = <1>; | |
| 733 | ||
| 734 | lvds0_mux_1: endpoint { | |
| 735 | remote-endpoint = <&ipu1_di1_lvds0>; | |
| 736 | }; | |
| 737 | }; | |
| 41c04342 ST |
738 | }; |
| 739 | ||
| 740 | lvds-channel@1 { | |
| 4520e692 PZ |
741 | #address-cells = <1>; |
| 742 | #size-cells = <0>; | |
| 41c04342 | 743 | reg = <1>; |
| 41c04342 | 744 | status = "disabled"; |
| 4520e692 PZ |
745 | |
| 746 | port@0 { | |
| 747 | reg = <0>; | |
| 748 | ||
| 749 | lvds1_mux_0: endpoint { | |
| 750 | remote-endpoint = <&ipu1_di0_lvds1>; | |
| 751 | }; | |
| 752 | }; | |
| 753 | ||
| 754 | port@1 { | |
| 755 | reg = <1>; | |
| 756 | ||
| 757 | lvds1_mux_1: endpoint { | |
| 758 | remote-endpoint = <&ipu1_di1_lvds1>; | |
| 759 | }; | |
| 760 | }; | |
| 41c04342 ST |
761 | }; |
| 762 | }; | |
| 763 | ||
| 04cec1a2 | 764 | hdmi: hdmi@0120000 { |
| 4520e692 PZ |
765 | #address-cells = <1>; |
| 766 | #size-cells = <0>; | |
| 04cec1a2 RK |
767 | reg = <0x00120000 0x9000>; |
| 768 | interrupts = <0 115 0x04>; | |
| 769 | gpr = <&gpr>; | |
| 8888f651 SG |
770 | clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, |
| 771 | <&clks IMX6QDL_CLK_HDMI_ISFR>; | |
| 04cec1a2 RK |
772 | clock-names = "iahb", "isfr"; |
| 773 | status = "disabled"; | |
| 4520e692 PZ |
774 | |
| 775 | port@0 { | |
| 776 | reg = <0>; | |
| 777 | ||
| 778 | hdmi_mux_0: endpoint { | |
| 779 | remote-endpoint = <&ipu1_di0_hdmi>; | |
| 780 | }; | |
| 781 | }; | |
| 782 | ||
| 783 | port@1 { | |
| 784 | reg = <1>; | |
| 785 | ||
| 786 | hdmi_mux_1: endpoint { | |
| 787 | remote-endpoint = <&ipu1_di1_hdmi>; | |
| 788 | }; | |
| 789 | }; | |
| 04cec1a2 RK |
790 | }; |
| 791 | ||
| 7b7d6727 | 792 | dcic1: dcic@020e4000 { |
| 7d740f87 | 793 | reg = <0x020e4000 0x4000>; |
| 275c08b5 | 794 | interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
795 | }; |
| 796 | ||
| 7b7d6727 | 797 | dcic2: dcic@020e8000 { |
| 7d740f87 | 798 | reg = <0x020e8000 0x4000>; |
| 275c08b5 | 799 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
800 | }; |
| 801 | ||
| 7b7d6727 | 802 | sdma: sdma@020ec000 { |
| 7d740f87 SG |
803 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
| 804 | reg = <0x020ec000 0x4000>; | |
| 275c08b5 | 805 | interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
806 | clocks = <&clks IMX6QDL_CLK_SDMA>, |
| 807 | <&clks IMX6QDL_CLK_SDMA>; | |
| 0e87e043 | 808 | clock-names = "ipg", "ahb"; |
| fb72bb21 | 809 | #dma-cells = <3>; |
| d6b9c591 | 810 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
| 7d740f87 SG |
811 | }; |
| 812 | }; | |
| 813 | ||
| 814 | aips-bus@02100000 { /* AIPS2 */ | |
| 815 | compatible = "fsl,aips-bus", "simple-bus"; | |
| 816 | #address-cells = <1>; | |
| 817 | #size-cells = <1>; | |
| 818 | reg = <0x02100000 0x100000>; | |
| 819 | ranges; | |
| 820 | ||
| 821 | caam@02100000 { | |
| 822 | reg = <0x02100000 0x40000>; | |
| 275c08b5 TK |
823 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>, |
| 824 | <0 106 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
825 | }; |
| 826 | ||
| 827 | aipstz@0217c000 { /* AIPSTZ2 */ | |
| 828 | reg = <0x0217c000 0x4000>; | |
| 829 | }; | |
| 830 | ||
| 7b7d6727 | 831 | usbotg: usb@02184000 { |
| 74bd88f7 RZ |
832 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 833 | reg = <0x02184000 0x200>; | |
| 275c08b5 | 834 | interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 835 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
| 74bd88f7 | 836 | fsl,usbphy = <&usbphy1>; |
| 28342c61 | 837 | fsl,usbmisc = <&usbmisc 0>; |
| 74bd88f7 RZ |
838 | status = "disabled"; |
| 839 | }; | |
| 840 | ||
| 7b7d6727 | 841 | usbh1: usb@02184200 { |
| 74bd88f7 RZ |
842 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 843 | reg = <0x02184200 0x200>; | |
| 275c08b5 | 844 | interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 845 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
| 74bd88f7 | 846 | fsl,usbphy = <&usbphy2>; |
| 28342c61 | 847 | fsl,usbmisc = <&usbmisc 1>; |
| 74bd88f7 RZ |
848 | status = "disabled"; |
| 849 | }; | |
| 850 | ||
| 7b7d6727 | 851 | usbh2: usb@02184400 { |
| 74bd88f7 RZ |
852 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 853 | reg = <0x02184400 0x200>; | |
| 275c08b5 | 854 | interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 855 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
| 28342c61 | 856 | fsl,usbmisc = <&usbmisc 2>; |
| 74bd88f7 RZ |
857 | status = "disabled"; |
| 858 | }; | |
| 859 | ||
| 7b7d6727 | 860 | usbh3: usb@02184600 { |
| 74bd88f7 RZ |
861 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
| 862 | reg = <0x02184600 0x200>; | |
| 275c08b5 | 863 | interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 864 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
| 28342c61 | 865 | fsl,usbmisc = <&usbmisc 3>; |
| 74bd88f7 RZ |
866 | status = "disabled"; |
| 867 | }; | |
| 868 | ||
| 60984bdf | 869 | usbmisc: usbmisc@02184800 { |
| 28342c61 RZ |
870 | #index-cells = <1>; |
| 871 | compatible = "fsl,imx6q-usbmisc"; | |
| 872 | reg = <0x02184800 0x200>; | |
| 8888f651 | 873 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
| 28342c61 RZ |
874 | }; |
| 875 | ||
| 7b7d6727 | 876 | fec: ethernet@02188000 { |
| 7d740f87 SG |
877 | compatible = "fsl,imx6q-fec"; |
| 878 | reg = <0x02188000 0x4000>; | |
| 454cf8f5 TK |
879 | interrupts-extended = |
| 880 | <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, | |
| 881 | <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; | |
| 8888f651 SG |
882 | clocks = <&clks IMX6QDL_CLK_ENET>, |
| 883 | <&clks IMX6QDL_CLK_ENET>, | |
| 884 | <&clks IMX6QDL_CLK_ENET_REF>; | |
| 7629838c | 885 | clock-names = "ipg", "ahb", "ptp"; |
| 7d740f87 SG |
886 | status = "disabled"; |
| 887 | }; | |
| 888 | ||
| 889 | mlb@0218c000 { | |
| 890 | reg = <0x0218c000 0x4000>; | |
| 275c08b5 TK |
891 | interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, |
| 892 | <0 117 IRQ_TYPE_LEVEL_HIGH>, | |
| 893 | <0 126 IRQ_TYPE_LEVEL_HIGH>; | |
| 7d740f87 SG |
894 | }; |
| 895 | ||
| 7b7d6727 | 896 | usdhc1: usdhc@02190000 { |
| 7d740f87 SG |
897 | compatible = "fsl,imx6q-usdhc"; |
| 898 | reg = <0x02190000 0x4000>; | |
| 275c08b5 | 899 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
900 | clocks = <&clks IMX6QDL_CLK_USDHC1>, |
| 901 | <&clks IMX6QDL_CLK_USDHC1>, | |
| 902 | <&clks IMX6QDL_CLK_USDHC1>; | |
| 0e87e043 | 903 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 904 | bus-width = <4>; |
| 7d740f87 SG |
905 | status = "disabled"; |
| 906 | }; | |
| 907 | ||
| 7b7d6727 | 908 | usdhc2: usdhc@02194000 { |
| 7d740f87 SG |
909 | compatible = "fsl,imx6q-usdhc"; |
| 910 | reg = <0x02194000 0x4000>; | |
| 275c08b5 | 911 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
912 | clocks = <&clks IMX6QDL_CLK_USDHC2>, |
| 913 | <&clks IMX6QDL_CLK_USDHC2>, | |
| 914 | <&clks IMX6QDL_CLK_USDHC2>; | |
| 0e87e043 | 915 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 916 | bus-width = <4>; |
| 7d740f87 SG |
917 | status = "disabled"; |
| 918 | }; | |
| 919 | ||
| 7b7d6727 | 920 | usdhc3: usdhc@02198000 { |
| 7d740f87 SG |
921 | compatible = "fsl,imx6q-usdhc"; |
| 922 | reg = <0x02198000 0x4000>; | |
| 275c08b5 | 923 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
924 | clocks = <&clks IMX6QDL_CLK_USDHC3>, |
| 925 | <&clks IMX6QDL_CLK_USDHC3>, | |
| 926 | <&clks IMX6QDL_CLK_USDHC3>; | |
| 0e87e043 | 927 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 928 | bus-width = <4>; |
| 7d740f87 SG |
929 | status = "disabled"; |
| 930 | }; | |
| 931 | ||
| 7b7d6727 | 932 | usdhc4: usdhc@0219c000 { |
| 7d740f87 SG |
933 | compatible = "fsl,imx6q-usdhc"; |
| 934 | reg = <0x0219c000 0x4000>; | |
| 275c08b5 | 935 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
936 | clocks = <&clks IMX6QDL_CLK_USDHC4>, |
| 937 | <&clks IMX6QDL_CLK_USDHC4>, | |
| 938 | <&clks IMX6QDL_CLK_USDHC4>; | |
| 0e87e043 | 939 | clock-names = "ipg", "ahb", "per"; |
| c104b6a2 | 940 | bus-width = <4>; |
| 7d740f87 SG |
941 | status = "disabled"; |
| 942 | }; | |
| 943 | ||
| 7b7d6727 | 944 | i2c1: i2c@021a0000 { |
| 7d740f87 SG |
945 | #address-cells = <1>; |
| 946 | #size-cells = <0>; | |
| 5bdfba29 | 947 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| 7d740f87 | 948 | reg = <0x021a0000 0x4000>; |
| 275c08b5 | 949 | interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 950 | clocks = <&clks IMX6QDL_CLK_I2C1>; |
| 7d740f87 SG |
951 | status = "disabled"; |
| 952 | }; | |
| 953 | ||
| 7b7d6727 | 954 | i2c2: i2c@021a4000 { |
| 7d740f87 SG |
955 | #address-cells = <1>; |
| 956 | #size-cells = <0>; | |
| 5bdfba29 | 957 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| 7d740f87 | 958 | reg = <0x021a4000 0x4000>; |
| 275c08b5 | 959 | interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 960 | clocks = <&clks IMX6QDL_CLK_I2C2>; |
| 7d740f87 SG |
961 | status = "disabled"; |
| 962 | }; | |
| 963 | ||
| 7b7d6727 | 964 | i2c3: i2c@021a8000 { |
| 7d740f87 SG |
965 | #address-cells = <1>; |
| 966 | #size-cells = <0>; | |
| 5bdfba29 | 967 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| 7d740f87 | 968 | reg = <0x021a8000 0x4000>; |
| 275c08b5 | 969 | interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 970 | clocks = <&clks IMX6QDL_CLK_I2C3>; |
| 7d740f87 SG |
971 | status = "disabled"; |
| 972 | }; | |
| 973 | ||
| 974 | romcp@021ac000 { | |
| 975 | reg = <0x021ac000 0x4000>; | |
| 976 | }; | |
| 977 | ||
| 7b7d6727 | 978 | mmdc0: mmdc@021b0000 { /* MMDC0 */ |
| 7d740f87 SG |
979 | compatible = "fsl,imx6q-mmdc"; |
| 980 | reg = <0x021b0000 0x4000>; | |
| 981 | }; | |
| 982 | ||
| 7b7d6727 | 983 | mmdc1: mmdc@021b4000 { /* MMDC1 */ |
| 7d740f87 SG |
984 | reg = <0x021b4000 0x4000>; |
| 985 | }; | |
| 986 | ||
| 05e3f8e7 HS |
987 | weim: weim@021b8000 { |
| 988 | compatible = "fsl,imx6q-weim"; | |
| 7d740f87 | 989 | reg = <0x021b8000 0x4000>; |
| 275c08b5 | 990 | interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 | 991 | clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; |
| 7d740f87 SG |
992 | }; |
| 993 | ||
| 3fe6373b SG |
994 | ocotp: ocotp@021bc000 { |
| 995 | compatible = "fsl,imx6q-ocotp", "syscon"; | |
| 7d740f87 SG |
996 | reg = <0x021bc000 0x4000>; |
| 997 | }; | |
| 998 | ||
| 7d740f87 SG |
999 | tzasc@021d0000 { /* TZASC1 */ |
| 1000 | reg = <0x021d0000 0x4000>; | |
| 275c08b5 | 1001 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
1002 | }; |
| 1003 | ||
| 1004 | tzasc@021d4000 { /* TZASC2 */ | |
| 1005 | reg = <0x021d4000 0x4000>; | |
| 275c08b5 | 1006 | interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
1007 | }; |
| 1008 | ||
| 7b7d6727 | 1009 | audmux: audmux@021d8000 { |
| f965cd55 | 1010 | compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; |
| 7d740f87 | 1011 | reg = <0x021d8000 0x4000>; |
| f965cd55 | 1012 | status = "disabled"; |
| 7d740f87 SG |
1013 | }; |
| 1014 | ||
| 5e0c7cd4 | 1015 | mipi_csi: mipi@021dc000 { |
| 7d740f87 SG |
1016 | reg = <0x021dc000 0x4000>; |
| 1017 | }; | |
| 1018 | ||
| 4520e692 PZ |
1019 | mipi_dsi: mipi@021e0000 { |
| 1020 | #address-cells = <1>; | |
| 1021 | #size-cells = <0>; | |
| 7d740f87 | 1022 | reg = <0x021e0000 0x4000>; |
| 4520e692 PZ |
1023 | status = "disabled"; |
| 1024 | ||
| 1025 | port@0 { | |
| 1026 | reg = <0>; | |
| 1027 | ||
| 1028 | mipi_mux_0: endpoint { | |
| 1029 | remote-endpoint = <&ipu1_di0_mipi>; | |
| 1030 | }; | |
| 1031 | }; | |
| 1032 | ||
| 1033 | port@1 { | |
| 1034 | reg = <1>; | |
| 1035 | ||
| 1036 | mipi_mux_1: endpoint { | |
| 1037 | remote-endpoint = <&ipu1_di1_mipi>; | |
| 1038 | }; | |
| 1039 | }; | |
| 7d740f87 SG |
1040 | }; |
| 1041 | ||
| 1042 | vdoa@021e4000 { | |
| 1043 | reg = <0x021e4000 0x4000>; | |
| 275c08b5 | 1044 | interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; |
| 7d740f87 SG |
1045 | }; |
| 1046 | ||
| 0c456cfa | 1047 | uart2: serial@021e8000 { |
| 7d740f87 SG |
1048 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1049 | reg = <0x021e8000 0x4000>; | |
| 275c08b5 | 1050 | interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
1051 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
| 1052 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
| 0e87e043 | 1053 | clock-names = "ipg", "per"; |
| 72a5cebf HS |
1054 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; |
| 1055 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
1056 | status = "disabled"; |
| 1057 | }; | |
| 1058 | ||
| 0c456cfa | 1059 | uart3: serial@021ec000 { |
| 7d740f87 SG |
1060 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1061 | reg = <0x021ec000 0x4000>; | |
| 275c08b5 | 1062 | interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
1063 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
| 1064 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
| 0e87e043 | 1065 | clock-names = "ipg", "per"; |
| 72a5cebf HS |
1066 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; |
| 1067 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
1068 | status = "disabled"; |
| 1069 | }; | |
| 1070 | ||
| 0c456cfa | 1071 | uart4: serial@021f0000 { |
| 7d740f87 SG |
1072 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1073 | reg = <0x021f0000 0x4000>; | |
| 275c08b5 | 1074 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
1075 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
| 1076 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
| 0e87e043 | 1077 | clock-names = "ipg", "per"; |
| 72a5cebf HS |
1078 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; |
| 1079 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
1080 | status = "disabled"; |
| 1081 | }; | |
| 1082 | ||
| 0c456cfa | 1083 | uart5: serial@021f4000 { |
| 7d740f87 SG |
1084 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
| 1085 | reg = <0x021f4000 0x4000>; | |
| 275c08b5 | 1086 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; |
| 8888f651 SG |
1087 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
| 1088 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
| 0e87e043 | 1089 | clock-names = "ipg", "per"; |
| 72a5cebf HS |
1090 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; |
| 1091 | dma-names = "rx", "tx"; | |
| 7d740f87 SG |
1092 | status = "disabled"; |
| 1093 | }; | |
| 1094 | }; | |
| 91660d74 SH |
1095 | |
| 1096 | ipu1: ipu@02400000 { | |
| 4520e692 PZ |
1097 | #address-cells = <1>; |
| 1098 | #size-cells = <0>; | |
| 91660d74 SH |
1099 | compatible = "fsl,imx6q-ipu"; |
| 1100 | reg = <0x02400000 0x400000>; | |
| 275c08b5 TK |
1101 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, |
| 1102 | <0 5 IRQ_TYPE_LEVEL_HIGH>; | |
| 8888f651 SG |
1103 | clocks = <&clks IMX6QDL_CLK_IPU1>, |
| 1104 | <&clks IMX6QDL_CLK_IPU1_DI0>, | |
| 1105 | <&clks IMX6QDL_CLK_IPU1_DI1>; | |
| 91660d74 | 1106 | clock-names = "bus", "di0", "di1"; |
| 09ebf366 | 1107 | resets = <&src 2>; |
| 4520e692 | 1108 | |
| c0470c38 PZ |
1109 | ipu1_csi0: port@0 { |
| 1110 | reg = <0>; | |
| 1111 | }; | |
| 1112 | ||
| 1113 | ipu1_csi1: port@1 { | |
| 1114 | reg = <1>; | |
| 1115 | }; | |
| 1116 | ||
| 4520e692 PZ |
1117 | ipu1_di0: port@2 { |
| 1118 | #address-cells = <1>; | |
| 1119 | #size-cells = <0>; | |
| 1120 | reg = <2>; | |
| 1121 | ||
| 1122 | ipu1_di0_disp0: endpoint@0 { | |
| 1123 | }; | |
| 1124 | ||
| 1125 | ipu1_di0_hdmi: endpoint@1 { | |
| 1126 | remote-endpoint = <&hdmi_mux_0>; | |
| 1127 | }; | |
| 1128 | ||
| 1129 | ipu1_di0_mipi: endpoint@2 { | |
| 1130 | remote-endpoint = <&mipi_mux_0>; | |
| 1131 | }; | |
| 1132 | ||
| 1133 | ipu1_di0_lvds0: endpoint@3 { | |
| 1134 | remote-endpoint = <&lvds0_mux_0>; | |
| 1135 | }; | |
| 1136 | ||
| 1137 | ipu1_di0_lvds1: endpoint@4 { | |
| 1138 | remote-endpoint = <&lvds1_mux_0>; | |
| 1139 | }; | |
| 1140 | }; | |
| 1141 | ||
| 1142 | ipu1_di1: port@3 { | |
| 1143 | #address-cells = <1>; | |
| 1144 | #size-cells = <0>; | |
| 1145 | reg = <3>; | |
| 1146 | ||
| 1147 | ipu1_di0_disp1: endpoint@0 { | |
| 1148 | }; | |
| 1149 | ||
| 1150 | ipu1_di1_hdmi: endpoint@1 { | |
| 1151 | remote-endpoint = <&hdmi_mux_1>; | |
| 1152 | }; | |
| 1153 | ||
| 1154 | ipu1_di1_mipi: endpoint@2 { | |
| 1155 | remote-endpoint = <&mipi_mux_1>; | |
| 1156 | }; | |
| 1157 | ||
| 1158 | ipu1_di1_lvds0: endpoint@3 { | |
| 1159 | remote-endpoint = <&lvds0_mux_1>; | |
| 1160 | }; | |
| 1161 | ||
| 1162 | ipu1_di1_lvds1: endpoint@4 { | |
| 1163 | remote-endpoint = <&lvds1_mux_1>; | |
| 1164 | }; | |
| 1165 | }; | |
| 91660d74 | 1166 | }; |
| 7d740f87 SG |
1167 | }; |
| 1168 | }; |