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Commit | Line | Data |
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7d740f87 SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
8888f651 | 13 | #include <dt-bindings/clock/imx6qdl-clock.h> |
07134a36 LS |
14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
15 | ||
7d740f87 | 16 | / { |
7f107887 FE |
17 | #address-cells = <1>; |
18 | #size-cells = <1>; | |
a971c554 FE |
19 | /* |
20 | * The decompressor and also some bootloaders rely on a | |
21 | * pre-existing /chosen node to be available to insert the | |
22 | * command line and merge other ATAGS info. | |
23 | * Also for U-Boot there must be a pre-existing /memory node. | |
24 | */ | |
25 | chosen {}; | |
26 | memory { device_type = "memory"; reg = <0 0>; }; | |
7f107887 | 27 | |
7d740f87 | 28 | aliases { |
22970070 | 29 | ethernet0 = &fec; |
5f8fbc2c LW |
30 | can0 = &can1; |
31 | can1 = &can2; | |
5230f8fe SG |
32 | gpio0 = &gpio1; |
33 | gpio1 = &gpio2; | |
34 | gpio2 = &gpio3; | |
35 | gpio3 = &gpio4; | |
36 | gpio4 = &gpio5; | |
37 | gpio5 = &gpio6; | |
38 | gpio6 = &gpio7; | |
80fa0584 SH |
39 | i2c0 = &i2c1; |
40 | i2c1 = &i2c2; | |
41 | i2c2 = &i2c3; | |
41beef39 | 42 | ipu0 = &ipu1; |
fb06d65c SH |
43 | mmc0 = &usdhc1; |
44 | mmc1 = &usdhc2; | |
45 | mmc2 = &usdhc3; | |
46 | mmc3 = &usdhc4; | |
80fa0584 SH |
47 | serial0 = &uart1; |
48 | serial1 = &uart2; | |
49 | serial2 = &uart3; | |
50 | serial3 = &uart4; | |
51 | serial4 = &uart5; | |
52 | spi0 = &ecspi1; | |
53 | spi1 = &ecspi2; | |
54 | spi2 = &ecspi3; | |
55 | spi3 = &ecspi4; | |
8189c51f PC |
56 | usbphy0 = &usbphy1; |
57 | usbphy1 = &usbphy2; | |
7d740f87 SG |
58 | }; |
59 | ||
7d740f87 SG |
60 | clocks { |
61 | #address-cells = <1>; | |
62 | #size-cells = <0>; | |
63 | ||
64 | ckil { | |
65 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
4b2b4043 | 66 | #clock-cells = <0>; |
7d740f87 SG |
67 | clock-frequency = <32768>; |
68 | }; | |
69 | ||
70 | ckih1 { | |
71 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
4b2b4043 | 72 | #clock-cells = <0>; |
7d740f87 SG |
73 | clock-frequency = <0>; |
74 | }; | |
75 | ||
76 | osc { | |
77 | compatible = "fsl,imx-osc", "fixed-clock"; | |
4b2b4043 | 78 | #clock-cells = <0>; |
7d740f87 SG |
79 | clock-frequency = <24000000>; |
80 | }; | |
81 | }; | |
82 | ||
83 | soc { | |
84 | #address-cells = <1>; | |
85 | #size-cells = <1>; | |
86 | compatible = "simple-bus"; | |
b923ff6a | 87 | interrupt-parent = <&gpc>; |
7d740f87 SG |
88 | ranges; |
89 | ||
f30fb03d | 90 | dma_apbh: dma-apbh@00110000 { |
e5d0f9f5 HS |
91 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; |
92 | reg = <0x00110000 0x2000>; | |
275c08b5 TK |
93 | interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, |
94 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
95 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
96 | <0 13 IRQ_TYPE_LEVEL_HIGH>; | |
f30fb03d SG |
97 | interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; |
98 | #dma-cells = <1>; | |
99 | dma-channels = <4>; | |
8888f651 | 100 | clocks = <&clks IMX6QDL_CLK_APBH_DMA>; |
e5d0f9f5 HS |
101 | }; |
102 | ||
be4ccfce | 103 | gpmi: gpmi-nand@00112000 { |
0e87e043 SG |
104 | compatible = "fsl,imx6q-gpmi-nand"; |
105 | #address-cells = <1>; | |
106 | #size-cells = <1>; | |
107 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; | |
108 | reg-names = "gpmi-nand", "bch"; | |
275c08b5 | 109 | interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; |
c7aa12a6 | 110 | interrupt-names = "bch"; |
8888f651 SG |
111 | clocks = <&clks IMX6QDL_CLK_GPMI_IO>, |
112 | <&clks IMX6QDL_CLK_GPMI_APB>, | |
113 | <&clks IMX6QDL_CLK_GPMI_BCH>, | |
114 | <&clks IMX6QDL_CLK_GPMI_BCH_APB>, | |
115 | <&clks IMX6QDL_CLK_PER1_BCH>; | |
0e87e043 SG |
116 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", |
117 | "gpmi_bch_apb", "per1_bch"; | |
f30fb03d SG |
118 | dmas = <&dma_apbh 0>; |
119 | dma-names = "rx-tx"; | |
0e87e043 | 120 | status = "disabled"; |
cf922fa8 HS |
121 | }; |
122 | ||
ac4af82b LS |
123 | hdmi: hdmi@0120000 { |
124 | #address-cells = <1>; | |
125 | #size-cells = <0>; | |
126 | reg = <0x00120000 0x9000>; | |
127 | interrupts = <0 115 0x04>; | |
128 | gpr = <&gpr>; | |
129 | clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, | |
130 | <&clks IMX6QDL_CLK_HDMI_ISFR>; | |
131 | clock-names = "iahb", "isfr"; | |
132 | status = "disabled"; | |
133 | ||
134 | port@0 { | |
135 | reg = <0>; | |
136 | ||
137 | hdmi_mux_0: endpoint { | |
138 | remote-endpoint = <&ipu1_di0_hdmi>; | |
139 | }; | |
140 | }; | |
141 | ||
142 | port@1 { | |
143 | reg = <1>; | |
144 | ||
145 | hdmi_mux_1: endpoint { | |
146 | remote-endpoint = <&ipu1_di1_hdmi>; | |
147 | }; | |
148 | }; | |
149 | }; | |
150 | ||
419e202b LS |
151 | gpu_3d: gpu@00130000 { |
152 | compatible = "vivante,gc"; | |
153 | reg = <0x00130000 0x4000>; | |
154 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; | |
155 | clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, | |
156 | <&clks IMX6QDL_CLK_GPU3D_CORE>, | |
157 | <&clks IMX6QDL_CLK_GPU3D_SHADER>; | |
158 | clock-names = "bus", "core", "shader"; | |
159 | power-domains = <&gpc 1>; | |
160 | }; | |
161 | ||
162 | gpu_2d: gpu@00134000 { | |
163 | compatible = "vivante,gc"; | |
164 | reg = <0x00134000 0x4000>; | |
165 | interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; | |
166 | clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, | |
167 | <&clks IMX6QDL_CLK_GPU2D_CORE>; | |
168 | clock-names = "bus", "core"; | |
169 | power-domains = <&gpc 1>; | |
170 | }; | |
171 | ||
7d740f87 | 172 | timer@00a00600 { |
58458e03 MZ |
173 | compatible = "arm,cortex-a9-twd-timer"; |
174 | reg = <0x00a00600 0x20>; | |
175 | interrupts = <1 13 0xf01>; | |
b923ff6a | 176 | interrupt-parent = <&intc>; |
8888f651 | 177 | clocks = <&clks IMX6QDL_CLK_TWD>; |
7d740f87 SG |
178 | }; |
179 | ||
67157882 LS |
180 | intc: interrupt-controller@00a01000 { |
181 | compatible = "arm,cortex-a9-gic"; | |
182 | #interrupt-cells = <3>; | |
183 | interrupt-controller; | |
184 | reg = <0x00a01000 0x1000>, | |
185 | <0x00a00100 0x100>; | |
186 | interrupt-parent = <&intc>; | |
187 | }; | |
188 | ||
7d740f87 SG |
189 | L2: l2-cache@00a02000 { |
190 | compatible = "arm,pl310-cache"; | |
191 | reg = <0x00a02000 0x1000>; | |
275c08b5 | 192 | interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
193 | cache-unified; |
194 | cache-level = <2>; | |
5a5ca56e DB |
195 | arm,tag-latency = <4 2 3>; |
196 | arm,data-latency = <4 2 3>; | |
74332d75 | 197 | arm,shared-override; |
7d740f87 SG |
198 | }; |
199 | ||
3e1b8577 | 200 | pcie: pcie@1ffc000 { |
3a57291f | 201 | compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; |
fcd17303 LS |
202 | reg = <0x01ffc000 0x04000>, |
203 | <0x01f00000 0x80000>; | |
204 | reg-names = "dbi", "config"; | |
3a57291f SC |
205 | #address-cells = <3>; |
206 | #size-cells = <2>; | |
207 | device_type = "pci"; | |
3e1b8577 | 208 | bus-range = <0x00 0xff>; |
d9cf0a12 | 209 | ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ |
3a57291f SC |
210 | 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ |
211 | num-lanes = <1>; | |
92a7eb7c LS |
212 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
213 | interrupt-names = "msi"; | |
07134a36 LS |
214 | #interrupt-cells = <1>; |
215 | interrupt-map-mask = <0 0 0 0x7>; | |
1a9fa190 | 216 | interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
bf5393c5 JT |
217 | <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, |
218 | <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
219 | <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; | |
8888f651 SG |
220 | clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, |
221 | <&clks IMX6QDL_CLK_LVDS1_GATE>, | |
222 | <&clks IMX6QDL_CLK_PCIE_REF_125M>; | |
92a7eb7c | 223 | clock-names = "pcie", "pcie_bus", "pcie_phy"; |
3a57291f SC |
224 | status = "disabled"; |
225 | }; | |
226 | ||
218abe6f DB |
227 | pmu { |
228 | compatible = "arm,cortex-a9-pmu"; | |
275c08b5 | 229 | interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; |
218abe6f DB |
230 | }; |
231 | ||
7d740f87 SG |
232 | aips-bus@02000000 { /* AIPS1 */ |
233 | compatible = "fsl,aips-bus", "simple-bus"; | |
234 | #address-cells = <1>; | |
235 | #size-cells = <1>; | |
236 | reg = <0x02000000 0x100000>; | |
237 | ranges; | |
238 | ||
239 | spba-bus@02000000 { | |
240 | compatible = "fsl,spba-bus", "simple-bus"; | |
241 | #address-cells = <1>; | |
242 | #size-cells = <1>; | |
243 | reg = <0x02000000 0x40000>; | |
244 | ranges; | |
245 | ||
7b7d6727 | 246 | spdif: spdif@02004000 { |
c9d96df2 | 247 | compatible = "fsl,imx35-spdif"; |
7d740f87 | 248 | reg = <0x02004000 0x4000>; |
275c08b5 | 249 | interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; |
c9d96df2 FE |
250 | dmas = <&sdma 14 18 0>, |
251 | <&sdma 15 18 0>; | |
252 | dma-names = "rx", "tx"; | |
833f2cbf SW |
253 | clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, |
254 | <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, | |
255 | <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, | |
f065e9e4 | 256 | <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, |
833f2cbf | 257 | <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; |
c9d96df2 FE |
258 | clock-names = "core", "rxtx0", |
259 | "rxtx1", "rxtx2", | |
260 | "rxtx3", "rxtx4", | |
261 | "rxtx5", "rxtx6", | |
09d3059a | 262 | "rxtx7", "spba"; |
c9d96df2 | 263 | status = "disabled"; |
7d740f87 SG |
264 | }; |
265 | ||
7b7d6727 | 266 | ecspi1: ecspi@02008000 { |
7d740f87 SG |
267 | #address-cells = <1>; |
268 | #size-cells = <0>; | |
269 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
270 | reg = <0x02008000 0x4000>; | |
275c08b5 | 271 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
272 | clocks = <&clks IMX6QDL_CLK_ECSPI1>, |
273 | <&clks IMX6QDL_CLK_ECSPI1>; | |
0e87e043 | 274 | clock-names = "ipg", "per"; |
dd4b487b | 275 | dmas = <&sdma 3 8 1>, <&sdma 4 8 2>; |
b3810c3d | 276 | dma-names = "rx", "tx"; |
7d740f87 SG |
277 | status = "disabled"; |
278 | }; | |
279 | ||
7b7d6727 | 280 | ecspi2: ecspi@0200c000 { |
7d740f87 SG |
281 | #address-cells = <1>; |
282 | #size-cells = <0>; | |
283 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
284 | reg = <0x0200c000 0x4000>; | |
275c08b5 | 285 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
286 | clocks = <&clks IMX6QDL_CLK_ECSPI2>, |
287 | <&clks IMX6QDL_CLK_ECSPI2>; | |
0e87e043 | 288 | clock-names = "ipg", "per"; |
dd4b487b | 289 | dmas = <&sdma 5 8 1>, <&sdma 6 8 2>; |
b3810c3d | 290 | dma-names = "rx", "tx"; |
7d740f87 SG |
291 | status = "disabled"; |
292 | }; | |
293 | ||
7b7d6727 | 294 | ecspi3: ecspi@02010000 { |
7d740f87 SG |
295 | #address-cells = <1>; |
296 | #size-cells = <0>; | |
297 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
298 | reg = <0x02010000 0x4000>; | |
275c08b5 | 299 | interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
300 | clocks = <&clks IMX6QDL_CLK_ECSPI3>, |
301 | <&clks IMX6QDL_CLK_ECSPI3>; | |
0e87e043 | 302 | clock-names = "ipg", "per"; |
dd4b487b | 303 | dmas = <&sdma 7 8 1>, <&sdma 8 8 2>; |
b3810c3d | 304 | dma-names = "rx", "tx"; |
7d740f87 SG |
305 | status = "disabled"; |
306 | }; | |
307 | ||
7b7d6727 | 308 | ecspi4: ecspi@02014000 { |
7d740f87 SG |
309 | #address-cells = <1>; |
310 | #size-cells = <0>; | |
311 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
312 | reg = <0x02014000 0x4000>; | |
275c08b5 | 313 | interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
314 | clocks = <&clks IMX6QDL_CLK_ECSPI4>, |
315 | <&clks IMX6QDL_CLK_ECSPI4>; | |
0e87e043 | 316 | clock-names = "ipg", "per"; |
dd4b487b | 317 | dmas = <&sdma 9 8 1>, <&sdma 10 8 2>; |
b3810c3d | 318 | dma-names = "rx", "tx"; |
7d740f87 SG |
319 | status = "disabled"; |
320 | }; | |
321 | ||
0c456cfa | 322 | uart1: serial@02020000 { |
7d740f87 SG |
323 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
324 | reg = <0x02020000 0x4000>; | |
275c08b5 | 325 | interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
326 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
327 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 328 | clock-names = "ipg", "per"; |
72a5cebf HS |
329 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; |
330 | dma-names = "rx", "tx"; | |
7d740f87 SG |
331 | status = "disabled"; |
332 | }; | |
333 | ||
7b7d6727 | 334 | esai: esai@02024000 { |
97dae859 SW |
335 | #sound-dai-cells = <0>; |
336 | compatible = "fsl,imx35-esai"; | |
7d740f87 | 337 | reg = <0x02024000 0x4000>; |
275c08b5 | 338 | interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; |
97dae859 SW |
339 | clocks = <&clks IMX6QDL_CLK_ESAI_IPG>, |
340 | <&clks IMX6QDL_CLK_ESAI_MEM>, | |
341 | <&clks IMX6QDL_CLK_ESAI_EXTAL>, | |
342 | <&clks IMX6QDL_CLK_ESAI_IPG>, | |
343 | <&clks IMX6QDL_CLK_SPBA>; | |
09d3059a | 344 | clock-names = "core", "mem", "extal", "fsys", "spba"; |
97dae859 SW |
345 | dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; |
346 | dma-names = "rx", "tx"; | |
347 | status = "disabled"; | |
7d740f87 SG |
348 | }; |
349 | ||
b1a5da8e | 350 | ssi1: ssi@02028000 { |
6ff7f51e | 351 | #sound-dai-cells = <0>; |
98ea6ad2 | 352 | compatible = "fsl,imx6q-ssi", |
4c03527e | 353 | "fsl,imx51-ssi"; |
7d740f87 | 354 | reg = <0x02028000 0x4000>; |
275c08b5 | 355 | interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; |
935632e9 SW |
356 | clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, |
357 | <&clks IMX6QDL_CLK_SSI1>; | |
358 | clock-names = "ipg", "baud"; | |
5da826ab SG |
359 | dmas = <&sdma 37 1 0>, |
360 | <&sdma 38 1 0>; | |
361 | dma-names = "rx", "tx"; | |
b1a5da8e | 362 | fsl,fifo-depth = <15>; |
b1a5da8e | 363 | status = "disabled"; |
7d740f87 SG |
364 | }; |
365 | ||
b1a5da8e | 366 | ssi2: ssi@0202c000 { |
6ff7f51e | 367 | #sound-dai-cells = <0>; |
98ea6ad2 | 368 | compatible = "fsl,imx6q-ssi", |
4c03527e | 369 | "fsl,imx51-ssi"; |
7d740f87 | 370 | reg = <0x0202c000 0x4000>; |
275c08b5 | 371 | interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; |
935632e9 SW |
372 | clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, |
373 | <&clks IMX6QDL_CLK_SSI2>; | |
374 | clock-names = "ipg", "baud"; | |
5da826ab SG |
375 | dmas = <&sdma 41 1 0>, |
376 | <&sdma 42 1 0>; | |
377 | dma-names = "rx", "tx"; | |
b1a5da8e | 378 | fsl,fifo-depth = <15>; |
b1a5da8e | 379 | status = "disabled"; |
7d740f87 SG |
380 | }; |
381 | ||
b1a5da8e | 382 | ssi3: ssi@02030000 { |
6ff7f51e | 383 | #sound-dai-cells = <0>; |
98ea6ad2 | 384 | compatible = "fsl,imx6q-ssi", |
4c03527e | 385 | "fsl,imx51-ssi"; |
7d740f87 | 386 | reg = <0x02030000 0x4000>; |
275c08b5 | 387 | interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; |
935632e9 SW |
388 | clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, |
389 | <&clks IMX6QDL_CLK_SSI3>; | |
390 | clock-names = "ipg", "baud"; | |
5da826ab SG |
391 | dmas = <&sdma 45 1 0>, |
392 | <&sdma 46 1 0>; | |
393 | dma-names = "rx", "tx"; | |
b1a5da8e | 394 | fsl,fifo-depth = <15>; |
b1a5da8e | 395 | status = "disabled"; |
7d740f87 SG |
396 | }; |
397 | ||
7b7d6727 | 398 | asrc: asrc@02034000 { |
97dae859 | 399 | compatible = "fsl,imx53-asrc"; |
7d740f87 | 400 | reg = <0x02034000 0x4000>; |
275c08b5 | 401 | interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; |
97dae859 SW |
402 | clocks = <&clks IMX6QDL_CLK_ASRC_IPG>, |
403 | <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>, | |
404 | <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, | |
405 | <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, | |
406 | <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, | |
407 | <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>, | |
408 | <&clks IMX6QDL_CLK_SPBA>; | |
409 | clock-names = "mem", "ipg", "asrck_0", | |
410 | "asrck_1", "asrck_2", "asrck_3", "asrck_4", | |
411 | "asrck_5", "asrck_6", "asrck_7", "asrck_8", | |
412 | "asrck_9", "asrck_a", "asrck_b", "asrck_c", | |
09d3059a | 413 | "asrck_d", "asrck_e", "asrck_f", "spba"; |
97dae859 SW |
414 | dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, |
415 | <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; | |
416 | dma-names = "rxa", "rxb", "rxc", | |
417 | "txa", "txb", "txc"; | |
418 | fsl,asrc-rate = <48000>; | |
419 | fsl,asrc-width = <16>; | |
420 | status = "okay"; | |
7d740f87 SG |
421 | }; |
422 | ||
423 | spba@0203c000 { | |
424 | reg = <0x0203c000 0x4000>; | |
425 | }; | |
426 | }; | |
427 | ||
7b7d6727 | 428 | vpu: vpu@02040000 { |
a04a0b6f | 429 | compatible = "cnm,coda960"; |
7d740f87 | 430 | reg = <0x02040000 0x3c000>; |
b2faf1a1 PZ |
431 | interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, |
432 | <0 3 IRQ_TYPE_LEVEL_HIGH>; | |
a04a0b6f PZ |
433 | interrupt-names = "bit", "jpeg"; |
434 | clocks = <&clks IMX6QDL_CLK_VPU_AXI>, | |
c9997ba2 FE |
435 | <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; |
436 | clock-names = "per", "ahb"; | |
29eea64c | 437 | power-domains = <&gpc 1>; |
a04a0b6f PZ |
438 | resets = <&src 1>; |
439 | iram = <&ocram>; | |
7d740f87 SG |
440 | }; |
441 | ||
442 | aipstz@0207c000 { /* AIPSTZ1 */ | |
443 | reg = <0x0207c000 0x4000>; | |
444 | }; | |
445 | ||
7b7d6727 | 446 | pwm1: pwm@02080000 { |
33b38587 SH |
447 | #pwm-cells = <2>; |
448 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 | 449 | reg = <0x02080000 0x4000>; |
275c08b5 | 450 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
451 | clocks = <&clks IMX6QDL_CLK_IPG>, |
452 | <&clks IMX6QDL_CLK_PWM1>; | |
33b38587 | 453 | clock-names = "ipg", "per"; |
e2675266 | 454 | status = "disabled"; |
7d740f87 SG |
455 | }; |
456 | ||
7b7d6727 | 457 | pwm2: pwm@02084000 { |
33b38587 SH |
458 | #pwm-cells = <2>; |
459 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 | 460 | reg = <0x02084000 0x4000>; |
275c08b5 | 461 | interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
462 | clocks = <&clks IMX6QDL_CLK_IPG>, |
463 | <&clks IMX6QDL_CLK_PWM2>; | |
33b38587 | 464 | clock-names = "ipg", "per"; |
e2675266 | 465 | status = "disabled"; |
7d740f87 SG |
466 | }; |
467 | ||
7b7d6727 | 468 | pwm3: pwm@02088000 { |
33b38587 SH |
469 | #pwm-cells = <2>; |
470 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 | 471 | reg = <0x02088000 0x4000>; |
275c08b5 | 472 | interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
473 | clocks = <&clks IMX6QDL_CLK_IPG>, |
474 | <&clks IMX6QDL_CLK_PWM3>; | |
33b38587 | 475 | clock-names = "ipg", "per"; |
e2675266 | 476 | status = "disabled"; |
7d740f87 SG |
477 | }; |
478 | ||
7b7d6727 | 479 | pwm4: pwm@0208c000 { |
33b38587 SH |
480 | #pwm-cells = <2>; |
481 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 | 482 | reg = <0x0208c000 0x4000>; |
275c08b5 | 483 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
484 | clocks = <&clks IMX6QDL_CLK_IPG>, |
485 | <&clks IMX6QDL_CLK_PWM4>; | |
33b38587 | 486 | clock-names = "ipg", "per"; |
e2675266 | 487 | status = "disabled"; |
7d740f87 SG |
488 | }; |
489 | ||
7b7d6727 | 490 | can1: flexcan@02090000 { |
0f225212 | 491 | compatible = "fsl,imx6q-flexcan"; |
7d740f87 | 492 | reg = <0x02090000 0x4000>; |
275c08b5 | 493 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
494 | clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, |
495 | <&clks IMX6QDL_CLK_CAN1_SERIAL>; | |
0f225212 | 496 | clock-names = "ipg", "per"; |
a1135337 | 497 | status = "disabled"; |
7d740f87 SG |
498 | }; |
499 | ||
7b7d6727 | 500 | can2: flexcan@02094000 { |
0f225212 | 501 | compatible = "fsl,imx6q-flexcan"; |
7d740f87 | 502 | reg = <0x02094000 0x4000>; |
275c08b5 | 503 | interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
504 | clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, |
505 | <&clks IMX6QDL_CLK_CAN2_SERIAL>; | |
0f225212 | 506 | clock-names = "ipg", "per"; |
a1135337 | 507 | status = "disabled"; |
7d740f87 SG |
508 | }; |
509 | ||
7b7d6727 | 510 | gpt: gpt@02098000 { |
97b108f9 | 511 | compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; |
7d740f87 | 512 | reg = <0x02098000 0x4000>; |
275c08b5 | 513 | interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 514 | clocks = <&clks IMX6QDL_CLK_GPT_IPG>, |
2b2244a3 AH |
515 | <&clks IMX6QDL_CLK_GPT_IPG_PER>, |
516 | <&clks IMX6QDL_CLK_GPT_3M>; | |
517 | clock-names = "ipg", "per", "osc_per"; | |
7d740f87 SG |
518 | }; |
519 | ||
4d191868 | 520 | gpio1: gpio@0209c000 { |
aeb27748 | 521 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 522 | reg = <0x0209c000 0x4000>; |
275c08b5 TK |
523 | interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, |
524 | <0 67 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
525 | gpio-controller; |
526 | #gpio-cells = <2>; | |
527 | interrupt-controller; | |
88cde8b7 | 528 | #interrupt-cells = <2>; |
7d740f87 SG |
529 | }; |
530 | ||
4d191868 | 531 | gpio2: gpio@020a0000 { |
aeb27748 | 532 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 533 | reg = <0x020a0000 0x4000>; |
275c08b5 TK |
534 | interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, |
535 | <0 69 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
536 | gpio-controller; |
537 | #gpio-cells = <2>; | |
538 | interrupt-controller; | |
88cde8b7 | 539 | #interrupt-cells = <2>; |
7d740f87 SG |
540 | }; |
541 | ||
4d191868 | 542 | gpio3: gpio@020a4000 { |
aeb27748 | 543 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 544 | reg = <0x020a4000 0x4000>; |
275c08b5 TK |
545 | interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, |
546 | <0 71 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
547 | gpio-controller; |
548 | #gpio-cells = <2>; | |
549 | interrupt-controller; | |
88cde8b7 | 550 | #interrupt-cells = <2>; |
7d740f87 SG |
551 | }; |
552 | ||
4d191868 | 553 | gpio4: gpio@020a8000 { |
aeb27748 | 554 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 555 | reg = <0x020a8000 0x4000>; |
275c08b5 TK |
556 | interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, |
557 | <0 73 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
558 | gpio-controller; |
559 | #gpio-cells = <2>; | |
560 | interrupt-controller; | |
88cde8b7 | 561 | #interrupt-cells = <2>; |
7d740f87 SG |
562 | }; |
563 | ||
4d191868 | 564 | gpio5: gpio@020ac000 { |
aeb27748 | 565 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 566 | reg = <0x020ac000 0x4000>; |
275c08b5 TK |
567 | interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, |
568 | <0 75 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
569 | gpio-controller; |
570 | #gpio-cells = <2>; | |
571 | interrupt-controller; | |
88cde8b7 | 572 | #interrupt-cells = <2>; |
7d740f87 SG |
573 | }; |
574 | ||
4d191868 | 575 | gpio6: gpio@020b0000 { |
aeb27748 | 576 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 577 | reg = <0x020b0000 0x4000>; |
275c08b5 TK |
578 | interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, |
579 | <0 77 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
580 | gpio-controller; |
581 | #gpio-cells = <2>; | |
582 | interrupt-controller; | |
88cde8b7 | 583 | #interrupt-cells = <2>; |
7d740f87 SG |
584 | }; |
585 | ||
4d191868 | 586 | gpio7: gpio@020b4000 { |
aeb27748 | 587 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 588 | reg = <0x020b4000 0x4000>; |
275c08b5 TK |
589 | interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, |
590 | <0 79 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
591 | gpio-controller; |
592 | #gpio-cells = <2>; | |
593 | interrupt-controller; | |
88cde8b7 | 594 | #interrupt-cells = <2>; |
7d740f87 SG |
595 | }; |
596 | ||
7b7d6727 | 597 | kpp: kpp@020b8000 { |
36d3a8f0 | 598 | compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; |
7d740f87 | 599 | reg = <0x020b8000 0x4000>; |
275c08b5 | 600 | interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 601 | clocks = <&clks IMX6QDL_CLK_IPG>; |
1b6f2368 | 602 | status = "disabled"; |
7d740f87 SG |
603 | }; |
604 | ||
7b7d6727 | 605 | wdog1: wdog@020bc000 { |
7d740f87 SG |
606 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
607 | reg = <0x020bc000 0x4000>; | |
275c08b5 | 608 | interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 609 | clocks = <&clks IMX6QDL_CLK_DUMMY>; |
7d740f87 SG |
610 | }; |
611 | ||
7b7d6727 | 612 | wdog2: wdog@020c0000 { |
7d740f87 SG |
613 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
614 | reg = <0x020c0000 0x4000>; | |
275c08b5 | 615 | interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 616 | clocks = <&clks IMX6QDL_CLK_DUMMY>; |
7d740f87 SG |
617 | status = "disabled"; |
618 | }; | |
619 | ||
0e87e043 | 620 | clks: ccm@020c4000 { |
7d740f87 SG |
621 | compatible = "fsl,imx6q-ccm"; |
622 | reg = <0x020c4000 0x4000>; | |
275c08b5 TK |
623 | interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, |
624 | <0 88 IRQ_TYPE_LEVEL_HIGH>; | |
0e87e043 | 625 | #clock-cells = <1>; |
7d740f87 SG |
626 | }; |
627 | ||
baa64151 DA |
628 | anatop: anatop@020c8000 { |
629 | compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; | |
7d740f87 | 630 | reg = <0x020c8000 0x1000>; |
275c08b5 TK |
631 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, |
632 | <0 54 IRQ_TYPE_LEVEL_HIGH>, | |
633 | <0 127 IRQ_TYPE_LEVEL_HIGH>; | |
a1e327e6 | 634 | |
c77ebb45 | 635 | regulator-1p1 { |
a1e327e6 YCLP |
636 | compatible = "fsl,anatop-regulator"; |
637 | regulator-name = "vdd1p1"; | |
ecbf5e70 LS |
638 | regulator-min-microvolt = <1000000>; |
639 | regulator-max-microvolt = <1200000>; | |
a1e327e6 YCLP |
640 | regulator-always-on; |
641 | anatop-reg-offset = <0x110>; | |
642 | anatop-vol-bit-shift = <8>; | |
643 | anatop-vol-bit-width = <5>; | |
644 | anatop-min-bit-val = <4>; | |
645 | anatop-min-voltage = <800000>; | |
646 | anatop-max-voltage = <1375000>; | |
647 | }; | |
648 | ||
c77ebb45 | 649 | regulator-3p0 { |
a1e327e6 YCLP |
650 | compatible = "fsl,anatop-regulator"; |
651 | regulator-name = "vdd3p0"; | |
652 | regulator-min-microvolt = <2800000>; | |
653 | regulator-max-microvolt = <3150000>; | |
654 | regulator-always-on; | |
655 | anatop-reg-offset = <0x120>; | |
656 | anatop-vol-bit-shift = <8>; | |
657 | anatop-vol-bit-width = <5>; | |
658 | anatop-min-bit-val = <0>; | |
659 | anatop-min-voltage = <2625000>; | |
660 | anatop-max-voltage = <3400000>; | |
661 | }; | |
662 | ||
c77ebb45 | 663 | regulator-2p5 { |
a1e327e6 YCLP |
664 | compatible = "fsl,anatop-regulator"; |
665 | regulator-name = "vdd2p5"; | |
ecbf5e70 | 666 | regulator-min-microvolt = <2250000>; |
a1e327e6 YCLP |
667 | regulator-max-microvolt = <2750000>; |
668 | regulator-always-on; | |
669 | anatop-reg-offset = <0x130>; | |
670 | anatop-vol-bit-shift = <8>; | |
671 | anatop-vol-bit-width = <5>; | |
672 | anatop-min-bit-val = <0>; | |
993051b2 LS |
673 | anatop-min-voltage = <2100000>; |
674 | anatop-max-voltage = <2875000>; | |
a1e327e6 YCLP |
675 | }; |
676 | ||
c77ebb45 | 677 | reg_arm: regulator-vddcore { |
a1e327e6 | 678 | compatible = "fsl,anatop-regulator"; |
118c98a6 | 679 | regulator-name = "vddarm"; |
a1e327e6 YCLP |
680 | regulator-min-microvolt = <725000>; |
681 | regulator-max-microvolt = <1450000>; | |
682 | regulator-always-on; | |
683 | anatop-reg-offset = <0x140>; | |
684 | anatop-vol-bit-shift = <0>; | |
685 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
686 | anatop-delay-reg-offset = <0x170>; |
687 | anatop-delay-bit-shift = <24>; | |
688 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
689 | anatop-min-bit-val = <1>; |
690 | anatop-min-voltage = <725000>; | |
691 | anatop-max-voltage = <1450000>; | |
692 | }; | |
693 | ||
c77ebb45 | 694 | reg_pu: regulator-vddpu { |
a1e327e6 YCLP |
695 | compatible = "fsl,anatop-regulator"; |
696 | regulator-name = "vddpu"; | |
697 | regulator-min-microvolt = <725000>; | |
698 | regulator-max-microvolt = <1450000>; | |
40130d32 | 699 | regulator-enable-ramp-delay = <150>; |
a1e327e6 YCLP |
700 | anatop-reg-offset = <0x140>; |
701 | anatop-vol-bit-shift = <9>; | |
702 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
703 | anatop-delay-reg-offset = <0x170>; |
704 | anatop-delay-bit-shift = <26>; | |
705 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
706 | anatop-min-bit-val = <1>; |
707 | anatop-min-voltage = <725000>; | |
708 | anatop-max-voltage = <1450000>; | |
709 | }; | |
710 | ||
c77ebb45 | 711 | reg_soc: regulator-vddsoc { |
a1e327e6 YCLP |
712 | compatible = "fsl,anatop-regulator"; |
713 | regulator-name = "vddsoc"; | |
714 | regulator-min-microvolt = <725000>; | |
715 | regulator-max-microvolt = <1450000>; | |
716 | regulator-always-on; | |
717 | anatop-reg-offset = <0x140>; | |
718 | anatop-vol-bit-shift = <18>; | |
719 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
720 | anatop-delay-reg-offset = <0x170>; |
721 | anatop-delay-bit-shift = <28>; | |
722 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
723 | anatop-min-bit-val = <1>; |
724 | anatop-min-voltage = <725000>; | |
725 | anatop-max-voltage = <1450000>; | |
726 | }; | |
7d740f87 SG |
727 | }; |
728 | ||
3fe6373b SG |
729 | tempmon: tempmon { |
730 | compatible = "fsl,imx6q-tempmon"; | |
275c08b5 | 731 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; |
3fe6373b SG |
732 | fsl,tempmon = <&anatop>; |
733 | fsl,tempmon-data = <&ocotp>; | |
8888f651 | 734 | clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; |
3fe6373b SG |
735 | }; |
736 | ||
74bd88f7 RZ |
737 | usbphy1: usbphy@020c9000 { |
738 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
7d740f87 | 739 | reg = <0x020c9000 0x1000>; |
275c08b5 | 740 | interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 741 | clocks = <&clks IMX6QDL_CLK_USBPHY1>; |
76a38855 | 742 | fsl,anatop = <&anatop>; |
7d740f87 SG |
743 | }; |
744 | ||
74bd88f7 RZ |
745 | usbphy2: usbphy@020ca000 { |
746 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
7d740f87 | 747 | reg = <0x020ca000 0x1000>; |
275c08b5 | 748 | interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 749 | clocks = <&clks IMX6QDL_CLK_USBPHY2>; |
76a38855 | 750 | fsl,anatop = <&anatop>; |
7d740f87 SG |
751 | }; |
752 | ||
95d739b5 FL |
753 | snvs: snvs@020cc000 { |
754 | compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; | |
755 | reg = <0x020cc000 0x4000>; | |
c9250388 | 756 | |
95d739b5 | 757 | snvs_rtc: snvs-rtc-lp { |
c9250388 | 758 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
95d739b5 FL |
759 | regmap = <&snvs>; |
760 | offset = <0x34>; | |
275c08b5 TK |
761 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, |
762 | <0 20 IRQ_TYPE_LEVEL_HIGH>; | |
c9250388 | 763 | }; |
422b0676 | 764 | |
95d739b5 FL |
765 | snvs_poweroff: snvs-poweroff { |
766 | compatible = "syscon-poweroff"; | |
767 | regmap = <&snvs>; | |
768 | offset = <0x38>; | |
769 | mask = <0x60>; | |
422b0676 RG |
770 | status = "disabled"; |
771 | }; | |
7d740f87 SG |
772 | }; |
773 | ||
7b7d6727 | 774 | epit1: epit@020d0000 { /* EPIT1 */ |
7d740f87 | 775 | reg = <0x020d0000 0x4000>; |
275c08b5 | 776 | interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
777 | }; |
778 | ||
7b7d6727 | 779 | epit2: epit@020d4000 { /* EPIT2 */ |
7d740f87 | 780 | reg = <0x020d4000 0x4000>; |
275c08b5 | 781 | interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
782 | }; |
783 | ||
7b7d6727 | 784 | src: src@020d8000 { |
bd3d924d | 785 | compatible = "fsl,imx6q-src", "fsl,imx51-src"; |
7d740f87 | 786 | reg = <0x020d8000 0x4000>; |
275c08b5 TK |
787 | interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, |
788 | <0 96 IRQ_TYPE_LEVEL_HIGH>; | |
09ebf366 | 789 | #reset-cells = <1>; |
7d740f87 SG |
790 | }; |
791 | ||
7b7d6727 | 792 | gpc: gpc@020dc000 { |
7d740f87 SG |
793 | compatible = "fsl,imx6q-gpc"; |
794 | reg = <0x020dc000 0x4000>; | |
b923ff6a MZ |
795 | interrupt-controller; |
796 | #interrupt-cells = <3>; | |
275c08b5 TK |
797 | interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, |
798 | <0 90 IRQ_TYPE_LEVEL_HIGH>; | |
b923ff6a | 799 | interrupt-parent = <&intc>; |
729c8881 PZ |
800 | pu-supply = <®_pu>; |
801 | clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, | |
802 | <&clks IMX6QDL_CLK_GPU3D_SHADER>, | |
803 | <&clks IMX6QDL_CLK_GPU2D_CORE>, | |
804 | <&clks IMX6QDL_CLK_GPU2D_AXI>, | |
805 | <&clks IMX6QDL_CLK_OPENVG_AXI>, | |
806 | <&clks IMX6QDL_CLK_VPU_AXI>; | |
807 | #power-domain-cells = <1>; | |
7d740f87 SG |
808 | }; |
809 | ||
df37e0c0 DA |
810 | gpr: iomuxc-gpr@020e0000 { |
811 | compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; | |
812 | reg = <0x020e0000 0x38>; | |
813 | }; | |
814 | ||
c56009b2 SG |
815 | iomuxc: iomuxc@020e0000 { |
816 | compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; | |
817 | reg = <0x020e0000 0x4000>; | |
c56009b2 SG |
818 | }; |
819 | ||
c519d57b | 820 | ldb: ldb { |
41c04342 ST |
821 | #address-cells = <1>; |
822 | #size-cells = <0>; | |
823 | compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; | |
824 | gpr = <&gpr>; | |
825 | status = "disabled"; | |
826 | ||
827 | lvds-channel@0 { | |
4520e692 PZ |
828 | #address-cells = <1>; |
829 | #size-cells = <0>; | |
41c04342 | 830 | reg = <0>; |
41c04342 | 831 | status = "disabled"; |
4520e692 PZ |
832 | |
833 | port@0 { | |
834 | reg = <0>; | |
835 | ||
836 | lvds0_mux_0: endpoint { | |
837 | remote-endpoint = <&ipu1_di0_lvds0>; | |
838 | }; | |
839 | }; | |
840 | ||
841 | port@1 { | |
842 | reg = <1>; | |
843 | ||
844 | lvds0_mux_1: endpoint { | |
845 | remote-endpoint = <&ipu1_di1_lvds0>; | |
846 | }; | |
847 | }; | |
41c04342 ST |
848 | }; |
849 | ||
850 | lvds-channel@1 { | |
4520e692 PZ |
851 | #address-cells = <1>; |
852 | #size-cells = <0>; | |
41c04342 | 853 | reg = <1>; |
41c04342 | 854 | status = "disabled"; |
4520e692 PZ |
855 | |
856 | port@0 { | |
857 | reg = <0>; | |
858 | ||
859 | lvds1_mux_0: endpoint { | |
860 | remote-endpoint = <&ipu1_di0_lvds1>; | |
861 | }; | |
862 | }; | |
863 | ||
864 | port@1 { | |
865 | reg = <1>; | |
866 | ||
867 | lvds1_mux_1: endpoint { | |
868 | remote-endpoint = <&ipu1_di1_lvds1>; | |
869 | }; | |
870 | }; | |
41c04342 ST |
871 | }; |
872 | }; | |
873 | ||
7b7d6727 | 874 | dcic1: dcic@020e4000 { |
7d740f87 | 875 | reg = <0x020e4000 0x4000>; |
275c08b5 | 876 | interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
877 | }; |
878 | ||
7b7d6727 | 879 | dcic2: dcic@020e8000 { |
7d740f87 | 880 | reg = <0x020e8000 0x4000>; |
275c08b5 | 881 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
882 | }; |
883 | ||
7b7d6727 | 884 | sdma: sdma@020ec000 { |
7d740f87 SG |
885 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
886 | reg = <0x020ec000 0x4000>; | |
275c08b5 | 887 | interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
888 | clocks = <&clks IMX6QDL_CLK_SDMA>, |
889 | <&clks IMX6QDL_CLK_SDMA>; | |
0e87e043 | 890 | clock-names = "ipg", "ahb"; |
fb72bb21 | 891 | #dma-cells = <3>; |
d6b9c591 | 892 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
7d740f87 SG |
893 | }; |
894 | }; | |
895 | ||
896 | aips-bus@02100000 { /* AIPS2 */ | |
897 | compatible = "fsl,aips-bus", "simple-bus"; | |
898 | #address-cells = <1>; | |
899 | #size-cells = <1>; | |
900 | reg = <0x02100000 0x100000>; | |
901 | ranges; | |
902 | ||
d462ce99 VM |
903 | crypto: caam@2100000 { |
904 | compatible = "fsl,sec-v4.0"; | |
905 | fsl,sec-era = <4>; | |
906 | #address-cells = <1>; | |
907 | #size-cells = <1>; | |
908 | reg = <0x2100000 0x10000>; | |
909 | ranges = <0 0x2100000 0x10000>; | |
d462ce99 VM |
910 | clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, |
911 | <&clks IMX6QDL_CLK_CAAM_ACLK>, | |
912 | <&clks IMX6QDL_CLK_CAAM_IPG>, | |
913 | <&clks IMX6QDL_CLK_EIM_SLOW>; | |
914 | clock-names = "mem", "aclk", "ipg", "emi_slow"; | |
915 | ||
916 | sec_jr0: jr0@1000 { | |
917 | compatible = "fsl,sec-v4.0-job-ring"; | |
918 | reg = <0x1000 0x1000>; | |
919 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; | |
920 | }; | |
921 | ||
922 | sec_jr1: jr1@2000 { | |
923 | compatible = "fsl,sec-v4.0-job-ring"; | |
924 | reg = <0x2000 0x1000>; | |
925 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; | |
926 | }; | |
7d740f87 SG |
927 | }; |
928 | ||
929 | aipstz@0217c000 { /* AIPSTZ2 */ | |
930 | reg = <0x0217c000 0x4000>; | |
931 | }; | |
932 | ||
7b7d6727 | 933 | usbotg: usb@02184000 { |
74bd88f7 RZ |
934 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
935 | reg = <0x02184000 0x200>; | |
275c08b5 | 936 | interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 937 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
74bd88f7 | 938 | fsl,usbphy = <&usbphy1>; |
28342c61 | 939 | fsl,usbmisc = <&usbmisc 0>; |
9493bf54 | 940 | ahb-burst-config = <0x0>; |
2b1a40e8 PC |
941 | tx-burst-size-dword = <0x10>; |
942 | rx-burst-size-dword = <0x10>; | |
74bd88f7 RZ |
943 | status = "disabled"; |
944 | }; | |
945 | ||
7b7d6727 | 946 | usbh1: usb@02184200 { |
74bd88f7 RZ |
947 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
948 | reg = <0x02184200 0x200>; | |
275c08b5 | 949 | interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 950 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
74bd88f7 | 951 | fsl,usbphy = <&usbphy2>; |
28342c61 | 952 | fsl,usbmisc = <&usbmisc 1>; |
3ec481ed | 953 | dr_mode = "host"; |
9493bf54 | 954 | ahb-burst-config = <0x0>; |
2b1a40e8 PC |
955 | tx-burst-size-dword = <0x10>; |
956 | rx-burst-size-dword = <0x10>; | |
74bd88f7 RZ |
957 | status = "disabled"; |
958 | }; | |
959 | ||
7b7d6727 | 960 | usbh2: usb@02184400 { |
74bd88f7 RZ |
961 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
962 | reg = <0x02184400 0x200>; | |
275c08b5 | 963 | interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 964 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
28342c61 | 965 | fsl,usbmisc = <&usbmisc 2>; |
3ec481ed | 966 | dr_mode = "host"; |
9493bf54 | 967 | ahb-burst-config = <0x0>; |
2b1a40e8 PC |
968 | tx-burst-size-dword = <0x10>; |
969 | rx-burst-size-dword = <0x10>; | |
74bd88f7 RZ |
970 | status = "disabled"; |
971 | }; | |
972 | ||
7b7d6727 | 973 | usbh3: usb@02184600 { |
74bd88f7 RZ |
974 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
975 | reg = <0x02184600 0x200>; | |
275c08b5 | 976 | interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 977 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
28342c61 | 978 | fsl,usbmisc = <&usbmisc 3>; |
3ec481ed | 979 | dr_mode = "host"; |
9493bf54 | 980 | ahb-burst-config = <0x0>; |
2b1a40e8 PC |
981 | tx-burst-size-dword = <0x10>; |
982 | rx-burst-size-dword = <0x10>; | |
74bd88f7 RZ |
983 | status = "disabled"; |
984 | }; | |
985 | ||
60984bdf | 986 | usbmisc: usbmisc@02184800 { |
28342c61 RZ |
987 | #index-cells = <1>; |
988 | compatible = "fsl,imx6q-usbmisc"; | |
989 | reg = <0x02184800 0x200>; | |
8888f651 | 990 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
28342c61 RZ |
991 | }; |
992 | ||
7b7d6727 | 993 | fec: ethernet@02188000 { |
7d740f87 SG |
994 | compatible = "fsl,imx6q-fec"; |
995 | reg = <0x02188000 0x4000>; | |
454cf8f5 TK |
996 | interrupts-extended = |
997 | <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, | |
998 | <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; | |
8888f651 SG |
999 | clocks = <&clks IMX6QDL_CLK_ENET>, |
1000 | <&clks IMX6QDL_CLK_ENET>, | |
1001 | <&clks IMX6QDL_CLK_ENET_REF>; | |
7629838c | 1002 | clock-names = "ipg", "ahb", "ptp"; |
7d740f87 SG |
1003 | status = "disabled"; |
1004 | }; | |
1005 | ||
1006 | mlb@0218c000 { | |
1007 | reg = <0x0218c000 0x4000>; | |
275c08b5 TK |
1008 | interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, |
1009 | <0 117 IRQ_TYPE_LEVEL_HIGH>, | |
1010 | <0 126 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
1011 | }; |
1012 | ||
7b7d6727 | 1013 | usdhc1: usdhc@02190000 { |
7d740f87 SG |
1014 | compatible = "fsl,imx6q-usdhc"; |
1015 | reg = <0x02190000 0x4000>; | |
275c08b5 | 1016 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1017 | clocks = <&clks IMX6QDL_CLK_USDHC1>, |
1018 | <&clks IMX6QDL_CLK_USDHC1>, | |
1019 | <&clks IMX6QDL_CLK_USDHC1>; | |
0e87e043 | 1020 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 1021 | bus-width = <4>; |
7d740f87 SG |
1022 | status = "disabled"; |
1023 | }; | |
1024 | ||
7b7d6727 | 1025 | usdhc2: usdhc@02194000 { |
7d740f87 SG |
1026 | compatible = "fsl,imx6q-usdhc"; |
1027 | reg = <0x02194000 0x4000>; | |
275c08b5 | 1028 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1029 | clocks = <&clks IMX6QDL_CLK_USDHC2>, |
1030 | <&clks IMX6QDL_CLK_USDHC2>, | |
1031 | <&clks IMX6QDL_CLK_USDHC2>; | |
0e87e043 | 1032 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 1033 | bus-width = <4>; |
7d740f87 SG |
1034 | status = "disabled"; |
1035 | }; | |
1036 | ||
7b7d6727 | 1037 | usdhc3: usdhc@02198000 { |
7d740f87 SG |
1038 | compatible = "fsl,imx6q-usdhc"; |
1039 | reg = <0x02198000 0x4000>; | |
275c08b5 | 1040 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1041 | clocks = <&clks IMX6QDL_CLK_USDHC3>, |
1042 | <&clks IMX6QDL_CLK_USDHC3>, | |
1043 | <&clks IMX6QDL_CLK_USDHC3>; | |
0e87e043 | 1044 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 1045 | bus-width = <4>; |
7d740f87 SG |
1046 | status = "disabled"; |
1047 | }; | |
1048 | ||
7b7d6727 | 1049 | usdhc4: usdhc@0219c000 { |
7d740f87 SG |
1050 | compatible = "fsl,imx6q-usdhc"; |
1051 | reg = <0x0219c000 0x4000>; | |
275c08b5 | 1052 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1053 | clocks = <&clks IMX6QDL_CLK_USDHC4>, |
1054 | <&clks IMX6QDL_CLK_USDHC4>, | |
1055 | <&clks IMX6QDL_CLK_USDHC4>; | |
0e87e043 | 1056 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 1057 | bus-width = <4>; |
7d740f87 SG |
1058 | status = "disabled"; |
1059 | }; | |
1060 | ||
7b7d6727 | 1061 | i2c1: i2c@021a0000 { |
7d740f87 SG |
1062 | #address-cells = <1>; |
1063 | #size-cells = <0>; | |
5bdfba29 | 1064 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 | 1065 | reg = <0x021a0000 0x4000>; |
275c08b5 | 1066 | interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 1067 | clocks = <&clks IMX6QDL_CLK_I2C1>; |
7d740f87 SG |
1068 | status = "disabled"; |
1069 | }; | |
1070 | ||
7b7d6727 | 1071 | i2c2: i2c@021a4000 { |
7d740f87 SG |
1072 | #address-cells = <1>; |
1073 | #size-cells = <0>; | |
5bdfba29 | 1074 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 | 1075 | reg = <0x021a4000 0x4000>; |
275c08b5 | 1076 | interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 1077 | clocks = <&clks IMX6QDL_CLK_I2C2>; |
7d740f87 SG |
1078 | status = "disabled"; |
1079 | }; | |
1080 | ||
7b7d6727 | 1081 | i2c3: i2c@021a8000 { |
7d740f87 SG |
1082 | #address-cells = <1>; |
1083 | #size-cells = <0>; | |
5bdfba29 | 1084 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 | 1085 | reg = <0x021a8000 0x4000>; |
275c08b5 | 1086 | interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 1087 | clocks = <&clks IMX6QDL_CLK_I2C3>; |
7d740f87 SG |
1088 | status = "disabled"; |
1089 | }; | |
1090 | ||
1091 | romcp@021ac000 { | |
1092 | reg = <0x021ac000 0x4000>; | |
1093 | }; | |
1094 | ||
7b7d6727 | 1095 | mmdc0: mmdc@021b0000 { /* MMDC0 */ |
7d740f87 SG |
1096 | compatible = "fsl,imx6q-mmdc"; |
1097 | reg = <0x021b0000 0x4000>; | |
1098 | }; | |
1099 | ||
7b7d6727 | 1100 | mmdc1: mmdc@021b4000 { /* MMDC1 */ |
7d740f87 SG |
1101 | reg = <0x021b4000 0x4000>; |
1102 | }; | |
1103 | ||
05e3f8e7 | 1104 | weim: weim@021b8000 { |
1be81ea5 JC |
1105 | #address-cells = <2>; |
1106 | #size-cells = <1>; | |
05e3f8e7 | 1107 | compatible = "fsl,imx6q-weim"; |
7d740f87 | 1108 | reg = <0x021b8000 0x4000>; |
275c08b5 | 1109 | interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 1110 | clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; |
1be81ea5 | 1111 | fsl,weim-cs-gpr = <&gpr>; |
116dad7d | 1112 | status = "disabled"; |
7d740f87 SG |
1113 | }; |
1114 | ||
3fe6373b SG |
1115 | ocotp: ocotp@021bc000 { |
1116 | compatible = "fsl,imx6q-ocotp", "syscon"; | |
7d740f87 | 1117 | reg = <0x021bc000 0x4000>; |
b8ecd889 | 1118 | clocks = <&clks IMX6QDL_CLK_IIM>; |
7d740f87 SG |
1119 | }; |
1120 | ||
7d740f87 SG |
1121 | tzasc@021d0000 { /* TZASC1 */ |
1122 | reg = <0x021d0000 0x4000>; | |
275c08b5 | 1123 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
1124 | }; |
1125 | ||
1126 | tzasc@021d4000 { /* TZASC2 */ | |
1127 | reg = <0x021d4000 0x4000>; | |
275c08b5 | 1128 | interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
1129 | }; |
1130 | ||
7b7d6727 | 1131 | audmux: audmux@021d8000 { |
f965cd55 | 1132 | compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; |
7d740f87 | 1133 | reg = <0x021d8000 0x4000>; |
f965cd55 | 1134 | status = "disabled"; |
7d740f87 SG |
1135 | }; |
1136 | ||
5e0c7cd4 | 1137 | mipi_csi: mipi@021dc000 { |
7d740f87 SG |
1138 | reg = <0x021dc000 0x4000>; |
1139 | }; | |
1140 | ||
4520e692 PZ |
1141 | mipi_dsi: mipi@021e0000 { |
1142 | #address-cells = <1>; | |
1143 | #size-cells = <0>; | |
7d740f87 | 1144 | reg = <0x021e0000 0x4000>; |
4520e692 PZ |
1145 | status = "disabled"; |
1146 | ||
70c2652c LY |
1147 | ports { |
1148 | #address-cells = <1>; | |
1149 | #size-cells = <0>; | |
1150 | ||
1151 | port@0 { | |
1152 | reg = <0>; | |
4520e692 | 1153 | |
70c2652c LY |
1154 | mipi_mux_0: endpoint { |
1155 | remote-endpoint = <&ipu1_di0_mipi>; | |
1156 | }; | |
4520e692 | 1157 | }; |
4520e692 | 1158 | |
70c2652c LY |
1159 | port@1 { |
1160 | reg = <1>; | |
4520e692 | 1161 | |
70c2652c LY |
1162 | mipi_mux_1: endpoint { |
1163 | remote-endpoint = <&ipu1_di1_mipi>; | |
1164 | }; | |
4520e692 PZ |
1165 | }; |
1166 | }; | |
7d740f87 SG |
1167 | }; |
1168 | ||
1169 | vdoa@021e4000 { | |
67c59006 | 1170 | compatible = "fsl,imx6q-vdoa"; |
7d740f87 | 1171 | reg = <0x021e4000 0x4000>; |
275c08b5 | 1172 | interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; |
67c59006 | 1173 | clocks = <&clks IMX6QDL_CLK_VDOA>; |
7d740f87 SG |
1174 | }; |
1175 | ||
0c456cfa | 1176 | uart2: serial@021e8000 { |
7d740f87 SG |
1177 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1178 | reg = <0x021e8000 0x4000>; | |
275c08b5 | 1179 | interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1180 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
1181 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 1182 | clock-names = "ipg", "per"; |
72a5cebf HS |
1183 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; |
1184 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1185 | status = "disabled"; |
1186 | }; | |
1187 | ||
0c456cfa | 1188 | uart3: serial@021ec000 { |
7d740f87 SG |
1189 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1190 | reg = <0x021ec000 0x4000>; | |
275c08b5 | 1191 | interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1192 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
1193 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 1194 | clock-names = "ipg", "per"; |
72a5cebf HS |
1195 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; |
1196 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1197 | status = "disabled"; |
1198 | }; | |
1199 | ||
0c456cfa | 1200 | uart4: serial@021f0000 { |
7d740f87 SG |
1201 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1202 | reg = <0x021f0000 0x4000>; | |
275c08b5 | 1203 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1204 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
1205 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 1206 | clock-names = "ipg", "per"; |
72a5cebf HS |
1207 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; |
1208 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1209 | status = "disabled"; |
1210 | }; | |
1211 | ||
0c456cfa | 1212 | uart5: serial@021f4000 { |
7d740f87 SG |
1213 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1214 | reg = <0x021f4000 0x4000>; | |
275c08b5 | 1215 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1216 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
1217 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 1218 | clock-names = "ipg", "per"; |
72a5cebf HS |
1219 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; |
1220 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1221 | status = "disabled"; |
1222 | }; | |
1223 | }; | |
91660d74 SH |
1224 | |
1225 | ipu1: ipu@02400000 { | |
4520e692 PZ |
1226 | #address-cells = <1>; |
1227 | #size-cells = <0>; | |
91660d74 SH |
1228 | compatible = "fsl,imx6q-ipu"; |
1229 | reg = <0x02400000 0x400000>; | |
275c08b5 TK |
1230 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, |
1231 | <0 5 IRQ_TYPE_LEVEL_HIGH>; | |
8888f651 SG |
1232 | clocks = <&clks IMX6QDL_CLK_IPU1>, |
1233 | <&clks IMX6QDL_CLK_IPU1_DI0>, | |
1234 | <&clks IMX6QDL_CLK_IPU1_DI1>; | |
91660d74 | 1235 | clock-names = "bus", "di0", "di1"; |
09ebf366 | 1236 | resets = <&src 2>; |
4520e692 | 1237 | |
c0470c38 PZ |
1238 | ipu1_csi0: port@0 { |
1239 | reg = <0>; | |
1240 | }; | |
1241 | ||
1242 | ipu1_csi1: port@1 { | |
1243 | reg = <1>; | |
1244 | }; | |
1245 | ||
4520e692 PZ |
1246 | ipu1_di0: port@2 { |
1247 | #address-cells = <1>; | |
1248 | #size-cells = <0>; | |
1249 | reg = <2>; | |
1250 | ||
416196cd | 1251 | ipu1_di0_disp0: disp0-endpoint { |
4520e692 PZ |
1252 | }; |
1253 | ||
416196cd | 1254 | ipu1_di0_hdmi: hdmi-endpoint { |
4520e692 PZ |
1255 | remote-endpoint = <&hdmi_mux_0>; |
1256 | }; | |
1257 | ||
416196cd | 1258 | ipu1_di0_mipi: mipi-endpoint { |
4520e692 PZ |
1259 | remote-endpoint = <&mipi_mux_0>; |
1260 | }; | |
1261 | ||
416196cd | 1262 | ipu1_di0_lvds0: lvds0-endpoint { |
4520e692 PZ |
1263 | remote-endpoint = <&lvds0_mux_0>; |
1264 | }; | |
1265 | ||
416196cd | 1266 | ipu1_di0_lvds1: lvds1-endpoint { |
4520e692 PZ |
1267 | remote-endpoint = <&lvds1_mux_0>; |
1268 | }; | |
1269 | }; | |
1270 | ||
1271 | ipu1_di1: port@3 { | |
1272 | #address-cells = <1>; | |
1273 | #size-cells = <0>; | |
1274 | reg = <3>; | |
1275 | ||
f255f89f | 1276 | ipu1_di1_disp1: disp1-endpoint { |
4520e692 PZ |
1277 | }; |
1278 | ||
416196cd | 1279 | ipu1_di1_hdmi: hdmi-endpoint { |
4520e692 PZ |
1280 | remote-endpoint = <&hdmi_mux_1>; |
1281 | }; | |
1282 | ||
416196cd | 1283 | ipu1_di1_mipi: mipi-endpoint { |
4520e692 PZ |
1284 | remote-endpoint = <&mipi_mux_1>; |
1285 | }; | |
1286 | ||
416196cd | 1287 | ipu1_di1_lvds0: lvds0-endpoint { |
4520e692 PZ |
1288 | remote-endpoint = <&lvds0_mux_1>; |
1289 | }; | |
1290 | ||
416196cd | 1291 | ipu1_di1_lvds1: lvds1-endpoint { |
4520e692 PZ |
1292 | remote-endpoint = <&lvds1_mux_1>; |
1293 | }; | |
1294 | }; | |
91660d74 | 1295 | }; |
7d740f87 SG |
1296 | }; |
1297 | }; |