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Commit | Line | Data |
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7d740f87 SG |
1 | /* |
2 | * Copyright 2011 Freescale Semiconductor, Inc. | |
3 | * Copyright 2011 Linaro Ltd. | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
8888f651 | 13 | #include <dt-bindings/clock/imx6qdl-clock.h> |
07134a36 LS |
14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
15 | ||
36dffd8f | 16 | #include "skeleton.dtsi" |
7d740f87 SG |
17 | |
18 | / { | |
19 | aliases { | |
22970070 | 20 | ethernet0 = &fec; |
5f8fbc2c LW |
21 | can0 = &can1; |
22 | can1 = &can2; | |
5230f8fe SG |
23 | gpio0 = &gpio1; |
24 | gpio1 = &gpio2; | |
25 | gpio2 = &gpio3; | |
26 | gpio3 = &gpio4; | |
27 | gpio4 = &gpio5; | |
28 | gpio5 = &gpio6; | |
29 | gpio6 = &gpio7; | |
80fa0584 SH |
30 | i2c0 = &i2c1; |
31 | i2c1 = &i2c2; | |
32 | i2c2 = &i2c3; | |
fb06d65c SH |
33 | mmc0 = &usdhc1; |
34 | mmc1 = &usdhc2; | |
35 | mmc2 = &usdhc3; | |
36 | mmc3 = &usdhc4; | |
80fa0584 SH |
37 | serial0 = &uart1; |
38 | serial1 = &uart2; | |
39 | serial2 = &uart3; | |
40 | serial3 = &uart4; | |
41 | serial4 = &uart5; | |
42 | spi0 = &ecspi1; | |
43 | spi1 = &ecspi2; | |
44 | spi2 = &ecspi3; | |
45 | spi3 = &ecspi4; | |
8189c51f PC |
46 | usbphy0 = &usbphy1; |
47 | usbphy1 = &usbphy2; | |
7d740f87 SG |
48 | }; |
49 | ||
7d740f87 SG |
50 | intc: interrupt-controller@00a01000 { |
51 | compatible = "arm,cortex-a9-gic"; | |
52 | #interrupt-cells = <3>; | |
7d740f87 SG |
53 | interrupt-controller; |
54 | reg = <0x00a01000 0x1000>, | |
55 | <0x00a00100 0x100>; | |
b923ff6a | 56 | interrupt-parent = <&intc>; |
7d740f87 SG |
57 | }; |
58 | ||
59 | clocks { | |
60 | #address-cells = <1>; | |
61 | #size-cells = <0>; | |
62 | ||
63 | ckil { | |
64 | compatible = "fsl,imx-ckil", "fixed-clock"; | |
4b2b4043 | 65 | #clock-cells = <0>; |
7d740f87 SG |
66 | clock-frequency = <32768>; |
67 | }; | |
68 | ||
69 | ckih1 { | |
70 | compatible = "fsl,imx-ckih1", "fixed-clock"; | |
4b2b4043 | 71 | #clock-cells = <0>; |
7d740f87 SG |
72 | clock-frequency = <0>; |
73 | }; | |
74 | ||
75 | osc { | |
76 | compatible = "fsl,imx-osc", "fixed-clock"; | |
4b2b4043 | 77 | #clock-cells = <0>; |
7d740f87 SG |
78 | clock-frequency = <24000000>; |
79 | }; | |
80 | }; | |
81 | ||
82 | soc { | |
83 | #address-cells = <1>; | |
84 | #size-cells = <1>; | |
85 | compatible = "simple-bus"; | |
b923ff6a | 86 | interrupt-parent = <&gpc>; |
7d740f87 SG |
87 | ranges; |
88 | ||
f30fb03d | 89 | dma_apbh: dma-apbh@00110000 { |
e5d0f9f5 HS |
90 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; |
91 | reg = <0x00110000 0x2000>; | |
275c08b5 TK |
92 | interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, |
93 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
94 | <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
95 | <0 13 IRQ_TYPE_LEVEL_HIGH>; | |
f30fb03d SG |
96 | interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; |
97 | #dma-cells = <1>; | |
98 | dma-channels = <4>; | |
8888f651 | 99 | clocks = <&clks IMX6QDL_CLK_APBH_DMA>; |
e5d0f9f5 HS |
100 | }; |
101 | ||
be4ccfce | 102 | gpmi: gpmi-nand@00112000 { |
0e87e043 SG |
103 | compatible = "fsl,imx6q-gpmi-nand"; |
104 | #address-cells = <1>; | |
105 | #size-cells = <1>; | |
106 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; | |
107 | reg-names = "gpmi-nand", "bch"; | |
275c08b5 | 108 | interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; |
c7aa12a6 | 109 | interrupt-names = "bch"; |
8888f651 SG |
110 | clocks = <&clks IMX6QDL_CLK_GPMI_IO>, |
111 | <&clks IMX6QDL_CLK_GPMI_APB>, | |
112 | <&clks IMX6QDL_CLK_GPMI_BCH>, | |
113 | <&clks IMX6QDL_CLK_GPMI_BCH_APB>, | |
114 | <&clks IMX6QDL_CLK_PER1_BCH>; | |
0e87e043 SG |
115 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", |
116 | "gpmi_bch_apb", "per1_bch"; | |
f30fb03d SG |
117 | dmas = <&dma_apbh 0>; |
118 | dma-names = "rx-tx"; | |
0e87e043 | 119 | status = "disabled"; |
cf922fa8 HS |
120 | }; |
121 | ||
ac4af82b LS |
122 | hdmi: hdmi@0120000 { |
123 | #address-cells = <1>; | |
124 | #size-cells = <0>; | |
125 | reg = <0x00120000 0x9000>; | |
126 | interrupts = <0 115 0x04>; | |
127 | gpr = <&gpr>; | |
128 | clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, | |
129 | <&clks IMX6QDL_CLK_HDMI_ISFR>; | |
130 | clock-names = "iahb", "isfr"; | |
131 | status = "disabled"; | |
132 | ||
133 | port@0 { | |
134 | reg = <0>; | |
135 | ||
136 | hdmi_mux_0: endpoint { | |
137 | remote-endpoint = <&ipu1_di0_hdmi>; | |
138 | }; | |
139 | }; | |
140 | ||
141 | port@1 { | |
142 | reg = <1>; | |
143 | ||
144 | hdmi_mux_1: endpoint { | |
145 | remote-endpoint = <&ipu1_di1_hdmi>; | |
146 | }; | |
147 | }; | |
148 | }; | |
149 | ||
7d740f87 | 150 | timer@00a00600 { |
58458e03 MZ |
151 | compatible = "arm,cortex-a9-twd-timer"; |
152 | reg = <0x00a00600 0x20>; | |
153 | interrupts = <1 13 0xf01>; | |
b923ff6a | 154 | interrupt-parent = <&intc>; |
8888f651 | 155 | clocks = <&clks IMX6QDL_CLK_TWD>; |
7d740f87 SG |
156 | }; |
157 | ||
158 | L2: l2-cache@00a02000 { | |
159 | compatible = "arm,pl310-cache"; | |
160 | reg = <0x00a02000 0x1000>; | |
275c08b5 | 161 | interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
162 | cache-unified; |
163 | cache-level = <2>; | |
5a5ca56e DB |
164 | arm,tag-latency = <4 2 3>; |
165 | arm,data-latency = <4 2 3>; | |
7d740f87 SG |
166 | }; |
167 | ||
3a57291f SC |
168 | pcie: pcie@0x01000000 { |
169 | compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; | |
fcd17303 LS |
170 | reg = <0x01ffc000 0x04000>, |
171 | <0x01f00000 0x80000>; | |
172 | reg-names = "dbi", "config"; | |
3a57291f SC |
173 | #address-cells = <3>; |
174 | #size-cells = <2>; | |
175 | device_type = "pci"; | |
176 | ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ | |
177 | 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ | |
178 | 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ | |
179 | num-lanes = <1>; | |
92a7eb7c LS |
180 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
181 | interrupt-names = "msi"; | |
07134a36 LS |
182 | #interrupt-cells = <1>; |
183 | interrupt-map-mask = <0 0 0 0x7>; | |
1a9fa190 LS |
184 | interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
185 | <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, | |
186 | <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
187 | <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; | |
8888f651 SG |
188 | clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, |
189 | <&clks IMX6QDL_CLK_LVDS1_GATE>, | |
190 | <&clks IMX6QDL_CLK_PCIE_REF_125M>; | |
92a7eb7c | 191 | clock-names = "pcie", "pcie_bus", "pcie_phy"; |
3a57291f SC |
192 | status = "disabled"; |
193 | }; | |
194 | ||
218abe6f DB |
195 | pmu { |
196 | compatible = "arm,cortex-a9-pmu"; | |
275c08b5 | 197 | interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; |
218abe6f DB |
198 | }; |
199 | ||
7d740f87 SG |
200 | aips-bus@02000000 { /* AIPS1 */ |
201 | compatible = "fsl,aips-bus", "simple-bus"; | |
202 | #address-cells = <1>; | |
203 | #size-cells = <1>; | |
204 | reg = <0x02000000 0x100000>; | |
205 | ranges; | |
206 | ||
207 | spba-bus@02000000 { | |
208 | compatible = "fsl,spba-bus", "simple-bus"; | |
209 | #address-cells = <1>; | |
210 | #size-cells = <1>; | |
211 | reg = <0x02000000 0x40000>; | |
212 | ranges; | |
213 | ||
7b7d6727 | 214 | spdif: spdif@02004000 { |
c9d96df2 | 215 | compatible = "fsl,imx35-spdif"; |
7d740f87 | 216 | reg = <0x02004000 0x4000>; |
275c08b5 | 217 | interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; |
c9d96df2 FE |
218 | dmas = <&sdma 14 18 0>, |
219 | <&sdma 15 18 0>; | |
220 | dma-names = "rx", "tx"; | |
8888f651 SG |
221 | clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>, |
222 | <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>, | |
223 | <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, | |
224 | <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, | |
225 | <&clks IMX6QDL_CLK_DUMMY>; | |
c9d96df2 FE |
226 | clock-names = "core", "rxtx0", |
227 | "rxtx1", "rxtx2", | |
228 | "rxtx3", "rxtx4", | |
229 | "rxtx5", "rxtx6", | |
230 | "rxtx7"; | |
231 | status = "disabled"; | |
7d740f87 SG |
232 | }; |
233 | ||
7b7d6727 | 234 | ecspi1: ecspi@02008000 { |
7d740f87 SG |
235 | #address-cells = <1>; |
236 | #size-cells = <0>; | |
237 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
238 | reg = <0x02008000 0x4000>; | |
275c08b5 | 239 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
240 | clocks = <&clks IMX6QDL_CLK_ECSPI1>, |
241 | <&clks IMX6QDL_CLK_ECSPI1>; | |
0e87e043 | 242 | clock-names = "ipg", "per"; |
b3810c3d FL |
243 | dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; |
244 | dma-names = "rx", "tx"; | |
7d740f87 SG |
245 | status = "disabled"; |
246 | }; | |
247 | ||
7b7d6727 | 248 | ecspi2: ecspi@0200c000 { |
7d740f87 SG |
249 | #address-cells = <1>; |
250 | #size-cells = <0>; | |
251 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
252 | reg = <0x0200c000 0x4000>; | |
275c08b5 | 253 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
254 | clocks = <&clks IMX6QDL_CLK_ECSPI2>, |
255 | <&clks IMX6QDL_CLK_ECSPI2>; | |
0e87e043 | 256 | clock-names = "ipg", "per"; |
b3810c3d FL |
257 | dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; |
258 | dma-names = "rx", "tx"; | |
7d740f87 SG |
259 | status = "disabled"; |
260 | }; | |
261 | ||
7b7d6727 | 262 | ecspi3: ecspi@02010000 { |
7d740f87 SG |
263 | #address-cells = <1>; |
264 | #size-cells = <0>; | |
265 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
266 | reg = <0x02010000 0x4000>; | |
275c08b5 | 267 | interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
268 | clocks = <&clks IMX6QDL_CLK_ECSPI3>, |
269 | <&clks IMX6QDL_CLK_ECSPI3>; | |
0e87e043 | 270 | clock-names = "ipg", "per"; |
b3810c3d FL |
271 | dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; |
272 | dma-names = "rx", "tx"; | |
7d740f87 SG |
273 | status = "disabled"; |
274 | }; | |
275 | ||
7b7d6727 | 276 | ecspi4: ecspi@02014000 { |
7d740f87 SG |
277 | #address-cells = <1>; |
278 | #size-cells = <0>; | |
279 | compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; | |
280 | reg = <0x02014000 0x4000>; | |
275c08b5 | 281 | interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
282 | clocks = <&clks IMX6QDL_CLK_ECSPI4>, |
283 | <&clks IMX6QDL_CLK_ECSPI4>; | |
0e87e043 | 284 | clock-names = "ipg", "per"; |
b3810c3d FL |
285 | dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; |
286 | dma-names = "rx", "tx"; | |
7d740f87 SG |
287 | status = "disabled"; |
288 | }; | |
289 | ||
0c456cfa | 290 | uart1: serial@02020000 { |
7d740f87 SG |
291 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
292 | reg = <0x02020000 0x4000>; | |
275c08b5 | 293 | interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
294 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
295 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 296 | clock-names = "ipg", "per"; |
72a5cebf HS |
297 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; |
298 | dma-names = "rx", "tx"; | |
7d740f87 SG |
299 | status = "disabled"; |
300 | }; | |
301 | ||
7b7d6727 | 302 | esai: esai@02024000 { |
97dae859 SW |
303 | #sound-dai-cells = <0>; |
304 | compatible = "fsl,imx35-esai"; | |
7d740f87 | 305 | reg = <0x02024000 0x4000>; |
275c08b5 | 306 | interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; |
97dae859 SW |
307 | clocks = <&clks IMX6QDL_CLK_ESAI_IPG>, |
308 | <&clks IMX6QDL_CLK_ESAI_MEM>, | |
309 | <&clks IMX6QDL_CLK_ESAI_EXTAL>, | |
310 | <&clks IMX6QDL_CLK_ESAI_IPG>, | |
311 | <&clks IMX6QDL_CLK_SPBA>; | |
312 | clock-names = "core", "mem", "extal", "fsys", "dma"; | |
313 | dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; | |
314 | dma-names = "rx", "tx"; | |
315 | status = "disabled"; | |
7d740f87 SG |
316 | }; |
317 | ||
b1a5da8e | 318 | ssi1: ssi@02028000 { |
6ff7f51e | 319 | #sound-dai-cells = <0>; |
98ea6ad2 | 320 | compatible = "fsl,imx6q-ssi", |
4c03527e | 321 | "fsl,imx51-ssi"; |
7d740f87 | 322 | reg = <0x02028000 0x4000>; |
275c08b5 | 323 | interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; |
935632e9 SW |
324 | clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, |
325 | <&clks IMX6QDL_CLK_SSI1>; | |
326 | clock-names = "ipg", "baud"; | |
5da826ab SG |
327 | dmas = <&sdma 37 1 0>, |
328 | <&sdma 38 1 0>; | |
329 | dma-names = "rx", "tx"; | |
b1a5da8e | 330 | fsl,fifo-depth = <15>; |
b1a5da8e | 331 | status = "disabled"; |
7d740f87 SG |
332 | }; |
333 | ||
b1a5da8e | 334 | ssi2: ssi@0202c000 { |
6ff7f51e | 335 | #sound-dai-cells = <0>; |
98ea6ad2 | 336 | compatible = "fsl,imx6q-ssi", |
4c03527e | 337 | "fsl,imx51-ssi"; |
7d740f87 | 338 | reg = <0x0202c000 0x4000>; |
275c08b5 | 339 | interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; |
935632e9 SW |
340 | clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, |
341 | <&clks IMX6QDL_CLK_SSI2>; | |
342 | clock-names = "ipg", "baud"; | |
5da826ab SG |
343 | dmas = <&sdma 41 1 0>, |
344 | <&sdma 42 1 0>; | |
345 | dma-names = "rx", "tx"; | |
b1a5da8e | 346 | fsl,fifo-depth = <15>; |
b1a5da8e | 347 | status = "disabled"; |
7d740f87 SG |
348 | }; |
349 | ||
b1a5da8e | 350 | ssi3: ssi@02030000 { |
6ff7f51e | 351 | #sound-dai-cells = <0>; |
98ea6ad2 | 352 | compatible = "fsl,imx6q-ssi", |
4c03527e | 353 | "fsl,imx51-ssi"; |
7d740f87 | 354 | reg = <0x02030000 0x4000>; |
275c08b5 | 355 | interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; |
935632e9 SW |
356 | clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, |
357 | <&clks IMX6QDL_CLK_SSI3>; | |
358 | clock-names = "ipg", "baud"; | |
5da826ab SG |
359 | dmas = <&sdma 45 1 0>, |
360 | <&sdma 46 1 0>; | |
361 | dma-names = "rx", "tx"; | |
b1a5da8e | 362 | fsl,fifo-depth = <15>; |
b1a5da8e | 363 | status = "disabled"; |
7d740f87 SG |
364 | }; |
365 | ||
7b7d6727 | 366 | asrc: asrc@02034000 { |
97dae859 | 367 | compatible = "fsl,imx53-asrc"; |
7d740f87 | 368 | reg = <0x02034000 0x4000>; |
275c08b5 | 369 | interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; |
97dae859 SW |
370 | clocks = <&clks IMX6QDL_CLK_ASRC_IPG>, |
371 | <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>, | |
372 | <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, | |
373 | <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, | |
374 | <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, | |
375 | <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>, | |
376 | <&clks IMX6QDL_CLK_SPBA>; | |
377 | clock-names = "mem", "ipg", "asrck_0", | |
378 | "asrck_1", "asrck_2", "asrck_3", "asrck_4", | |
379 | "asrck_5", "asrck_6", "asrck_7", "asrck_8", | |
380 | "asrck_9", "asrck_a", "asrck_b", "asrck_c", | |
381 | "asrck_d", "asrck_e", "asrck_f", "dma"; | |
382 | dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, | |
383 | <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; | |
384 | dma-names = "rxa", "rxb", "rxc", | |
385 | "txa", "txb", "txc"; | |
386 | fsl,asrc-rate = <48000>; | |
387 | fsl,asrc-width = <16>; | |
388 | status = "okay"; | |
7d740f87 SG |
389 | }; |
390 | ||
391 | spba@0203c000 { | |
392 | reg = <0x0203c000 0x4000>; | |
393 | }; | |
394 | }; | |
395 | ||
7b7d6727 | 396 | vpu: vpu@02040000 { |
a04a0b6f | 397 | compatible = "cnm,coda960"; |
7d740f87 | 398 | reg = <0x02040000 0x3c000>; |
b2faf1a1 PZ |
399 | interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, |
400 | <0 3 IRQ_TYPE_LEVEL_HIGH>; | |
a04a0b6f PZ |
401 | interrupt-names = "bit", "jpeg"; |
402 | clocks = <&clks IMX6QDL_CLK_VPU_AXI>, | |
c9997ba2 FE |
403 | <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; |
404 | clock-names = "per", "ahb"; | |
29eea64c | 405 | power-domains = <&gpc 1>; |
a04a0b6f PZ |
406 | resets = <&src 1>; |
407 | iram = <&ocram>; | |
7d740f87 SG |
408 | }; |
409 | ||
410 | aipstz@0207c000 { /* AIPSTZ1 */ | |
411 | reg = <0x0207c000 0x4000>; | |
412 | }; | |
413 | ||
7b7d6727 | 414 | pwm1: pwm@02080000 { |
33b38587 SH |
415 | #pwm-cells = <2>; |
416 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 | 417 | reg = <0x02080000 0x4000>; |
275c08b5 | 418 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
419 | clocks = <&clks IMX6QDL_CLK_IPG>, |
420 | <&clks IMX6QDL_CLK_PWM1>; | |
33b38587 | 421 | clock-names = "ipg", "per"; |
e2675266 | 422 | status = "disabled"; |
7d740f87 SG |
423 | }; |
424 | ||
7b7d6727 | 425 | pwm2: pwm@02084000 { |
33b38587 SH |
426 | #pwm-cells = <2>; |
427 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 | 428 | reg = <0x02084000 0x4000>; |
275c08b5 | 429 | interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
430 | clocks = <&clks IMX6QDL_CLK_IPG>, |
431 | <&clks IMX6QDL_CLK_PWM2>; | |
33b38587 | 432 | clock-names = "ipg", "per"; |
e2675266 | 433 | status = "disabled"; |
7d740f87 SG |
434 | }; |
435 | ||
7b7d6727 | 436 | pwm3: pwm@02088000 { |
33b38587 SH |
437 | #pwm-cells = <2>; |
438 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 | 439 | reg = <0x02088000 0x4000>; |
275c08b5 | 440 | interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
441 | clocks = <&clks IMX6QDL_CLK_IPG>, |
442 | <&clks IMX6QDL_CLK_PWM3>; | |
33b38587 | 443 | clock-names = "ipg", "per"; |
e2675266 | 444 | status = "disabled"; |
7d740f87 SG |
445 | }; |
446 | ||
7b7d6727 | 447 | pwm4: pwm@0208c000 { |
33b38587 SH |
448 | #pwm-cells = <2>; |
449 | compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; | |
7d740f87 | 450 | reg = <0x0208c000 0x4000>; |
275c08b5 | 451 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
452 | clocks = <&clks IMX6QDL_CLK_IPG>, |
453 | <&clks IMX6QDL_CLK_PWM4>; | |
33b38587 | 454 | clock-names = "ipg", "per"; |
e2675266 | 455 | status = "disabled"; |
7d740f87 SG |
456 | }; |
457 | ||
7b7d6727 | 458 | can1: flexcan@02090000 { |
0f225212 | 459 | compatible = "fsl,imx6q-flexcan"; |
7d740f87 | 460 | reg = <0x02090000 0x4000>; |
275c08b5 | 461 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
462 | clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, |
463 | <&clks IMX6QDL_CLK_CAN1_SERIAL>; | |
0f225212 | 464 | clock-names = "ipg", "per"; |
a1135337 | 465 | status = "disabled"; |
7d740f87 SG |
466 | }; |
467 | ||
7b7d6727 | 468 | can2: flexcan@02094000 { |
0f225212 | 469 | compatible = "fsl,imx6q-flexcan"; |
7d740f87 | 470 | reg = <0x02094000 0x4000>; |
275c08b5 | 471 | interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
472 | clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, |
473 | <&clks IMX6QDL_CLK_CAN2_SERIAL>; | |
0f225212 | 474 | clock-names = "ipg", "per"; |
a1135337 | 475 | status = "disabled"; |
7d740f87 SG |
476 | }; |
477 | ||
7b7d6727 | 478 | gpt: gpt@02098000 { |
97b108f9 | 479 | compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; |
7d740f87 | 480 | reg = <0x02098000 0x4000>; |
275c08b5 | 481 | interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 482 | clocks = <&clks IMX6QDL_CLK_GPT_IPG>, |
2b2244a3 AH |
483 | <&clks IMX6QDL_CLK_GPT_IPG_PER>, |
484 | <&clks IMX6QDL_CLK_GPT_3M>; | |
485 | clock-names = "ipg", "per", "osc_per"; | |
7d740f87 SG |
486 | }; |
487 | ||
4d191868 | 488 | gpio1: gpio@0209c000 { |
aeb27748 | 489 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 490 | reg = <0x0209c000 0x4000>; |
275c08b5 TK |
491 | interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, |
492 | <0 67 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
493 | gpio-controller; |
494 | #gpio-cells = <2>; | |
495 | interrupt-controller; | |
88cde8b7 | 496 | #interrupt-cells = <2>; |
7d740f87 SG |
497 | }; |
498 | ||
4d191868 | 499 | gpio2: gpio@020a0000 { |
aeb27748 | 500 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 501 | reg = <0x020a0000 0x4000>; |
275c08b5 TK |
502 | interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, |
503 | <0 69 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
504 | gpio-controller; |
505 | #gpio-cells = <2>; | |
506 | interrupt-controller; | |
88cde8b7 | 507 | #interrupt-cells = <2>; |
7d740f87 SG |
508 | }; |
509 | ||
4d191868 | 510 | gpio3: gpio@020a4000 { |
aeb27748 | 511 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 512 | reg = <0x020a4000 0x4000>; |
275c08b5 TK |
513 | interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, |
514 | <0 71 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
515 | gpio-controller; |
516 | #gpio-cells = <2>; | |
517 | interrupt-controller; | |
88cde8b7 | 518 | #interrupt-cells = <2>; |
7d740f87 SG |
519 | }; |
520 | ||
4d191868 | 521 | gpio4: gpio@020a8000 { |
aeb27748 | 522 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 523 | reg = <0x020a8000 0x4000>; |
275c08b5 TK |
524 | interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, |
525 | <0 73 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
526 | gpio-controller; |
527 | #gpio-cells = <2>; | |
528 | interrupt-controller; | |
88cde8b7 | 529 | #interrupt-cells = <2>; |
7d740f87 SG |
530 | }; |
531 | ||
4d191868 | 532 | gpio5: gpio@020ac000 { |
aeb27748 | 533 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 534 | reg = <0x020ac000 0x4000>; |
275c08b5 TK |
535 | interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, |
536 | <0 75 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
537 | gpio-controller; |
538 | #gpio-cells = <2>; | |
539 | interrupt-controller; | |
88cde8b7 | 540 | #interrupt-cells = <2>; |
7d740f87 SG |
541 | }; |
542 | ||
4d191868 | 543 | gpio6: gpio@020b0000 { |
aeb27748 | 544 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 545 | reg = <0x020b0000 0x4000>; |
275c08b5 TK |
546 | interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, |
547 | <0 77 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
548 | gpio-controller; |
549 | #gpio-cells = <2>; | |
550 | interrupt-controller; | |
88cde8b7 | 551 | #interrupt-cells = <2>; |
7d740f87 SG |
552 | }; |
553 | ||
4d191868 | 554 | gpio7: gpio@020b4000 { |
aeb27748 | 555 | compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; |
7d740f87 | 556 | reg = <0x020b4000 0x4000>; |
275c08b5 TK |
557 | interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, |
558 | <0 79 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
559 | gpio-controller; |
560 | #gpio-cells = <2>; | |
561 | interrupt-controller; | |
88cde8b7 | 562 | #interrupt-cells = <2>; |
7d740f87 SG |
563 | }; |
564 | ||
7b7d6727 | 565 | kpp: kpp@020b8000 { |
36d3a8f0 | 566 | compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; |
7d740f87 | 567 | reg = <0x020b8000 0x4000>; |
275c08b5 | 568 | interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 569 | clocks = <&clks IMX6QDL_CLK_IPG>; |
1b6f2368 | 570 | status = "disabled"; |
7d740f87 SG |
571 | }; |
572 | ||
7b7d6727 | 573 | wdog1: wdog@020bc000 { |
7d740f87 SG |
574 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
575 | reg = <0x020bc000 0x4000>; | |
275c08b5 | 576 | interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 577 | clocks = <&clks IMX6QDL_CLK_DUMMY>; |
7d740f87 SG |
578 | }; |
579 | ||
7b7d6727 | 580 | wdog2: wdog@020c0000 { |
7d740f87 SG |
581 | compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; |
582 | reg = <0x020c0000 0x4000>; | |
275c08b5 | 583 | interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 584 | clocks = <&clks IMX6QDL_CLK_DUMMY>; |
7d740f87 SG |
585 | status = "disabled"; |
586 | }; | |
587 | ||
0e87e043 | 588 | clks: ccm@020c4000 { |
7d740f87 SG |
589 | compatible = "fsl,imx6q-ccm"; |
590 | reg = <0x020c4000 0x4000>; | |
275c08b5 TK |
591 | interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, |
592 | <0 88 IRQ_TYPE_LEVEL_HIGH>; | |
0e87e043 | 593 | #clock-cells = <1>; |
7d740f87 SG |
594 | }; |
595 | ||
baa64151 DA |
596 | anatop: anatop@020c8000 { |
597 | compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; | |
7d740f87 | 598 | reg = <0x020c8000 0x1000>; |
275c08b5 TK |
599 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, |
600 | <0 54 IRQ_TYPE_LEVEL_HIGH>, | |
601 | <0 127 IRQ_TYPE_LEVEL_HIGH>; | |
a1e327e6 YCLP |
602 | |
603 | regulator-1p1@110 { | |
604 | compatible = "fsl,anatop-regulator"; | |
605 | regulator-name = "vdd1p1"; | |
606 | regulator-min-microvolt = <800000>; | |
607 | regulator-max-microvolt = <1375000>; | |
608 | regulator-always-on; | |
609 | anatop-reg-offset = <0x110>; | |
610 | anatop-vol-bit-shift = <8>; | |
611 | anatop-vol-bit-width = <5>; | |
612 | anatop-min-bit-val = <4>; | |
613 | anatop-min-voltage = <800000>; | |
614 | anatop-max-voltage = <1375000>; | |
615 | }; | |
616 | ||
617 | regulator-3p0@120 { | |
618 | compatible = "fsl,anatop-regulator"; | |
619 | regulator-name = "vdd3p0"; | |
620 | regulator-min-microvolt = <2800000>; | |
621 | regulator-max-microvolt = <3150000>; | |
622 | regulator-always-on; | |
623 | anatop-reg-offset = <0x120>; | |
624 | anatop-vol-bit-shift = <8>; | |
625 | anatop-vol-bit-width = <5>; | |
626 | anatop-min-bit-val = <0>; | |
627 | anatop-min-voltage = <2625000>; | |
628 | anatop-max-voltage = <3400000>; | |
629 | }; | |
630 | ||
631 | regulator-2p5@130 { | |
632 | compatible = "fsl,anatop-regulator"; | |
633 | regulator-name = "vdd2p5"; | |
634 | regulator-min-microvolt = <2000000>; | |
635 | regulator-max-microvolt = <2750000>; | |
636 | regulator-always-on; | |
637 | anatop-reg-offset = <0x130>; | |
638 | anatop-vol-bit-shift = <8>; | |
639 | anatop-vol-bit-width = <5>; | |
640 | anatop-min-bit-val = <0>; | |
641 | anatop-min-voltage = <2000000>; | |
642 | anatop-max-voltage = <2750000>; | |
643 | }; | |
644 | ||
96574a6d | 645 | reg_arm: regulator-vddcore@140 { |
a1e327e6 | 646 | compatible = "fsl,anatop-regulator"; |
118c98a6 | 647 | regulator-name = "vddarm"; |
a1e327e6 YCLP |
648 | regulator-min-microvolt = <725000>; |
649 | regulator-max-microvolt = <1450000>; | |
650 | regulator-always-on; | |
651 | anatop-reg-offset = <0x140>; | |
652 | anatop-vol-bit-shift = <0>; | |
653 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
654 | anatop-delay-reg-offset = <0x170>; |
655 | anatop-delay-bit-shift = <24>; | |
656 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
657 | anatop-min-bit-val = <1>; |
658 | anatop-min-voltage = <725000>; | |
659 | anatop-max-voltage = <1450000>; | |
660 | }; | |
661 | ||
96574a6d | 662 | reg_pu: regulator-vddpu@140 { |
a1e327e6 YCLP |
663 | compatible = "fsl,anatop-regulator"; |
664 | regulator-name = "vddpu"; | |
665 | regulator-min-microvolt = <725000>; | |
666 | regulator-max-microvolt = <1450000>; | |
40130d32 | 667 | regulator-enable-ramp-delay = <150>; |
a1e327e6 YCLP |
668 | anatop-reg-offset = <0x140>; |
669 | anatop-vol-bit-shift = <9>; | |
670 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
671 | anatop-delay-reg-offset = <0x170>; |
672 | anatop-delay-bit-shift = <26>; | |
673 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
674 | anatop-min-bit-val = <1>; |
675 | anatop-min-voltage = <725000>; | |
676 | anatop-max-voltage = <1450000>; | |
677 | }; | |
678 | ||
96574a6d | 679 | reg_soc: regulator-vddsoc@140 { |
a1e327e6 YCLP |
680 | compatible = "fsl,anatop-regulator"; |
681 | regulator-name = "vddsoc"; | |
682 | regulator-min-microvolt = <725000>; | |
683 | regulator-max-microvolt = <1450000>; | |
684 | regulator-always-on; | |
685 | anatop-reg-offset = <0x140>; | |
686 | anatop-vol-bit-shift = <18>; | |
687 | anatop-vol-bit-width = <5>; | |
46743dd6 AH |
688 | anatop-delay-reg-offset = <0x170>; |
689 | anatop-delay-bit-shift = <28>; | |
690 | anatop-delay-bit-width = <2>; | |
a1e327e6 YCLP |
691 | anatop-min-bit-val = <1>; |
692 | anatop-min-voltage = <725000>; | |
693 | anatop-max-voltage = <1450000>; | |
694 | }; | |
7d740f87 SG |
695 | }; |
696 | ||
3fe6373b SG |
697 | tempmon: tempmon { |
698 | compatible = "fsl,imx6q-tempmon"; | |
275c08b5 | 699 | interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; |
3fe6373b SG |
700 | fsl,tempmon = <&anatop>; |
701 | fsl,tempmon-data = <&ocotp>; | |
8888f651 | 702 | clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; |
3fe6373b SG |
703 | }; |
704 | ||
74bd88f7 RZ |
705 | usbphy1: usbphy@020c9000 { |
706 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
7d740f87 | 707 | reg = <0x020c9000 0x1000>; |
275c08b5 | 708 | interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 709 | clocks = <&clks IMX6QDL_CLK_USBPHY1>; |
76a38855 | 710 | fsl,anatop = <&anatop>; |
7d740f87 SG |
711 | }; |
712 | ||
74bd88f7 RZ |
713 | usbphy2: usbphy@020ca000 { |
714 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | |
7d740f87 | 715 | reg = <0x020ca000 0x1000>; |
275c08b5 | 716 | interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 717 | clocks = <&clks IMX6QDL_CLK_USBPHY2>; |
76a38855 | 718 | fsl,anatop = <&anatop>; |
7d740f87 SG |
719 | }; |
720 | ||
95d739b5 FL |
721 | snvs: snvs@020cc000 { |
722 | compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; | |
723 | reg = <0x020cc000 0x4000>; | |
c9250388 | 724 | |
95d739b5 | 725 | snvs_rtc: snvs-rtc-lp { |
c9250388 | 726 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
95d739b5 FL |
727 | regmap = <&snvs>; |
728 | offset = <0x34>; | |
275c08b5 TK |
729 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, |
730 | <0 20 IRQ_TYPE_LEVEL_HIGH>; | |
c9250388 | 731 | }; |
422b0676 | 732 | |
95d739b5 FL |
733 | snvs_poweroff: snvs-poweroff { |
734 | compatible = "syscon-poweroff"; | |
735 | regmap = <&snvs>; | |
736 | offset = <0x38>; | |
737 | mask = <0x60>; | |
422b0676 RG |
738 | status = "disabled"; |
739 | }; | |
7d740f87 SG |
740 | }; |
741 | ||
7b7d6727 | 742 | epit1: epit@020d0000 { /* EPIT1 */ |
7d740f87 | 743 | reg = <0x020d0000 0x4000>; |
275c08b5 | 744 | interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
745 | }; |
746 | ||
7b7d6727 | 747 | epit2: epit@020d4000 { /* EPIT2 */ |
7d740f87 | 748 | reg = <0x020d4000 0x4000>; |
275c08b5 | 749 | interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
750 | }; |
751 | ||
7b7d6727 | 752 | src: src@020d8000 { |
bd3d924d | 753 | compatible = "fsl,imx6q-src", "fsl,imx51-src"; |
7d740f87 | 754 | reg = <0x020d8000 0x4000>; |
275c08b5 TK |
755 | interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, |
756 | <0 96 IRQ_TYPE_LEVEL_HIGH>; | |
09ebf366 | 757 | #reset-cells = <1>; |
7d740f87 SG |
758 | }; |
759 | ||
7b7d6727 | 760 | gpc: gpc@020dc000 { |
7d740f87 SG |
761 | compatible = "fsl,imx6q-gpc"; |
762 | reg = <0x020dc000 0x4000>; | |
b923ff6a MZ |
763 | interrupt-controller; |
764 | #interrupt-cells = <3>; | |
275c08b5 TK |
765 | interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, |
766 | <0 90 IRQ_TYPE_LEVEL_HIGH>; | |
b923ff6a | 767 | interrupt-parent = <&intc>; |
729c8881 PZ |
768 | pu-supply = <®_pu>; |
769 | clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, | |
770 | <&clks IMX6QDL_CLK_GPU3D_SHADER>, | |
771 | <&clks IMX6QDL_CLK_GPU2D_CORE>, | |
772 | <&clks IMX6QDL_CLK_GPU2D_AXI>, | |
773 | <&clks IMX6QDL_CLK_OPENVG_AXI>, | |
774 | <&clks IMX6QDL_CLK_VPU_AXI>; | |
775 | #power-domain-cells = <1>; | |
7d740f87 SG |
776 | }; |
777 | ||
df37e0c0 DA |
778 | gpr: iomuxc-gpr@020e0000 { |
779 | compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; | |
780 | reg = <0x020e0000 0x38>; | |
781 | }; | |
782 | ||
c56009b2 SG |
783 | iomuxc: iomuxc@020e0000 { |
784 | compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; | |
785 | reg = <0x020e0000 0x4000>; | |
c56009b2 SG |
786 | }; |
787 | ||
41c04342 ST |
788 | ldb: ldb@020e0008 { |
789 | #address-cells = <1>; | |
790 | #size-cells = <0>; | |
791 | compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; | |
792 | gpr = <&gpr>; | |
793 | status = "disabled"; | |
794 | ||
795 | lvds-channel@0 { | |
4520e692 PZ |
796 | #address-cells = <1>; |
797 | #size-cells = <0>; | |
41c04342 | 798 | reg = <0>; |
41c04342 | 799 | status = "disabled"; |
4520e692 PZ |
800 | |
801 | port@0 { | |
802 | reg = <0>; | |
803 | ||
804 | lvds0_mux_0: endpoint { | |
805 | remote-endpoint = <&ipu1_di0_lvds0>; | |
806 | }; | |
807 | }; | |
808 | ||
809 | port@1 { | |
810 | reg = <1>; | |
811 | ||
812 | lvds0_mux_1: endpoint { | |
813 | remote-endpoint = <&ipu1_di1_lvds0>; | |
814 | }; | |
815 | }; | |
41c04342 ST |
816 | }; |
817 | ||
818 | lvds-channel@1 { | |
4520e692 PZ |
819 | #address-cells = <1>; |
820 | #size-cells = <0>; | |
41c04342 | 821 | reg = <1>; |
41c04342 | 822 | status = "disabled"; |
4520e692 PZ |
823 | |
824 | port@0 { | |
825 | reg = <0>; | |
826 | ||
827 | lvds1_mux_0: endpoint { | |
828 | remote-endpoint = <&ipu1_di0_lvds1>; | |
829 | }; | |
830 | }; | |
831 | ||
832 | port@1 { | |
833 | reg = <1>; | |
834 | ||
835 | lvds1_mux_1: endpoint { | |
836 | remote-endpoint = <&ipu1_di1_lvds1>; | |
837 | }; | |
838 | }; | |
41c04342 ST |
839 | }; |
840 | }; | |
841 | ||
7b7d6727 | 842 | dcic1: dcic@020e4000 { |
7d740f87 | 843 | reg = <0x020e4000 0x4000>; |
275c08b5 | 844 | interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
845 | }; |
846 | ||
7b7d6727 | 847 | dcic2: dcic@020e8000 { |
7d740f87 | 848 | reg = <0x020e8000 0x4000>; |
275c08b5 | 849 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
850 | }; |
851 | ||
7b7d6727 | 852 | sdma: sdma@020ec000 { |
7d740f87 SG |
853 | compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; |
854 | reg = <0x020ec000 0x4000>; | |
275c08b5 | 855 | interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
856 | clocks = <&clks IMX6QDL_CLK_SDMA>, |
857 | <&clks IMX6QDL_CLK_SDMA>; | |
0e87e043 | 858 | clock-names = "ipg", "ahb"; |
fb72bb21 | 859 | #dma-cells = <3>; |
d6b9c591 | 860 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
7d740f87 SG |
861 | }; |
862 | }; | |
863 | ||
864 | aips-bus@02100000 { /* AIPS2 */ | |
865 | compatible = "fsl,aips-bus", "simple-bus"; | |
866 | #address-cells = <1>; | |
867 | #size-cells = <1>; | |
868 | reg = <0x02100000 0x100000>; | |
869 | ranges; | |
870 | ||
d462ce99 VM |
871 | crypto: caam@2100000 { |
872 | compatible = "fsl,sec-v4.0"; | |
873 | fsl,sec-era = <4>; | |
874 | #address-cells = <1>; | |
875 | #size-cells = <1>; | |
876 | reg = <0x2100000 0x10000>; | |
877 | ranges = <0 0x2100000 0x10000>; | |
878 | interrupt-parent = <&intc>; | |
879 | clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, | |
880 | <&clks IMX6QDL_CLK_CAAM_ACLK>, | |
881 | <&clks IMX6QDL_CLK_CAAM_IPG>, | |
882 | <&clks IMX6QDL_CLK_EIM_SLOW>; | |
883 | clock-names = "mem", "aclk", "ipg", "emi_slow"; | |
884 | ||
885 | sec_jr0: jr0@1000 { | |
886 | compatible = "fsl,sec-v4.0-job-ring"; | |
887 | reg = <0x1000 0x1000>; | |
888 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; | |
889 | }; | |
890 | ||
891 | sec_jr1: jr1@2000 { | |
892 | compatible = "fsl,sec-v4.0-job-ring"; | |
893 | reg = <0x2000 0x1000>; | |
894 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; | |
895 | }; | |
7d740f87 SG |
896 | }; |
897 | ||
898 | aipstz@0217c000 { /* AIPSTZ2 */ | |
899 | reg = <0x0217c000 0x4000>; | |
900 | }; | |
901 | ||
7b7d6727 | 902 | usbotg: usb@02184000 { |
74bd88f7 RZ |
903 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
904 | reg = <0x02184000 0x200>; | |
275c08b5 | 905 | interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 906 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
74bd88f7 | 907 | fsl,usbphy = <&usbphy1>; |
28342c61 | 908 | fsl,usbmisc = <&usbmisc 0>; |
74bd88f7 RZ |
909 | status = "disabled"; |
910 | }; | |
911 | ||
7b7d6727 | 912 | usbh1: usb@02184200 { |
74bd88f7 RZ |
913 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
914 | reg = <0x02184200 0x200>; | |
275c08b5 | 915 | interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 916 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
74bd88f7 | 917 | fsl,usbphy = <&usbphy2>; |
28342c61 | 918 | fsl,usbmisc = <&usbmisc 1>; |
3ec481ed | 919 | dr_mode = "host"; |
74bd88f7 RZ |
920 | status = "disabled"; |
921 | }; | |
922 | ||
7b7d6727 | 923 | usbh2: usb@02184400 { |
74bd88f7 RZ |
924 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
925 | reg = <0x02184400 0x200>; | |
275c08b5 | 926 | interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 927 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
28342c61 | 928 | fsl,usbmisc = <&usbmisc 2>; |
3ec481ed | 929 | dr_mode = "host"; |
74bd88f7 RZ |
930 | status = "disabled"; |
931 | }; | |
932 | ||
7b7d6727 | 933 | usbh3: usb@02184600 { |
74bd88f7 RZ |
934 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; |
935 | reg = <0x02184600 0x200>; | |
275c08b5 | 936 | interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 937 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
28342c61 | 938 | fsl,usbmisc = <&usbmisc 3>; |
3ec481ed | 939 | dr_mode = "host"; |
74bd88f7 RZ |
940 | status = "disabled"; |
941 | }; | |
942 | ||
60984bdf | 943 | usbmisc: usbmisc@02184800 { |
28342c61 RZ |
944 | #index-cells = <1>; |
945 | compatible = "fsl,imx6q-usbmisc"; | |
946 | reg = <0x02184800 0x200>; | |
8888f651 | 947 | clocks = <&clks IMX6QDL_CLK_USBOH3>; |
28342c61 RZ |
948 | }; |
949 | ||
7b7d6727 | 950 | fec: ethernet@02188000 { |
7d740f87 SG |
951 | compatible = "fsl,imx6q-fec"; |
952 | reg = <0x02188000 0x4000>; | |
454cf8f5 TK |
953 | interrupts-extended = |
954 | <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, | |
955 | <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; | |
8888f651 SG |
956 | clocks = <&clks IMX6QDL_CLK_ENET>, |
957 | <&clks IMX6QDL_CLK_ENET>, | |
958 | <&clks IMX6QDL_CLK_ENET_REF>; | |
7629838c | 959 | clock-names = "ipg", "ahb", "ptp"; |
7d740f87 SG |
960 | status = "disabled"; |
961 | }; | |
962 | ||
963 | mlb@0218c000 { | |
964 | reg = <0x0218c000 0x4000>; | |
275c08b5 TK |
965 | interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, |
966 | <0 117 IRQ_TYPE_LEVEL_HIGH>, | |
967 | <0 126 IRQ_TYPE_LEVEL_HIGH>; | |
7d740f87 SG |
968 | }; |
969 | ||
7b7d6727 | 970 | usdhc1: usdhc@02190000 { |
7d740f87 SG |
971 | compatible = "fsl,imx6q-usdhc"; |
972 | reg = <0x02190000 0x4000>; | |
275c08b5 | 973 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
974 | clocks = <&clks IMX6QDL_CLK_USDHC1>, |
975 | <&clks IMX6QDL_CLK_USDHC1>, | |
976 | <&clks IMX6QDL_CLK_USDHC1>; | |
0e87e043 | 977 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 978 | bus-width = <4>; |
7d740f87 SG |
979 | status = "disabled"; |
980 | }; | |
981 | ||
7b7d6727 | 982 | usdhc2: usdhc@02194000 { |
7d740f87 SG |
983 | compatible = "fsl,imx6q-usdhc"; |
984 | reg = <0x02194000 0x4000>; | |
275c08b5 | 985 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
986 | clocks = <&clks IMX6QDL_CLK_USDHC2>, |
987 | <&clks IMX6QDL_CLK_USDHC2>, | |
988 | <&clks IMX6QDL_CLK_USDHC2>; | |
0e87e043 | 989 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 990 | bus-width = <4>; |
7d740f87 SG |
991 | status = "disabled"; |
992 | }; | |
993 | ||
7b7d6727 | 994 | usdhc3: usdhc@02198000 { |
7d740f87 SG |
995 | compatible = "fsl,imx6q-usdhc"; |
996 | reg = <0x02198000 0x4000>; | |
275c08b5 | 997 | interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
998 | clocks = <&clks IMX6QDL_CLK_USDHC3>, |
999 | <&clks IMX6QDL_CLK_USDHC3>, | |
1000 | <&clks IMX6QDL_CLK_USDHC3>; | |
0e87e043 | 1001 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 1002 | bus-width = <4>; |
7d740f87 SG |
1003 | status = "disabled"; |
1004 | }; | |
1005 | ||
7b7d6727 | 1006 | usdhc4: usdhc@0219c000 { |
7d740f87 SG |
1007 | compatible = "fsl,imx6q-usdhc"; |
1008 | reg = <0x0219c000 0x4000>; | |
275c08b5 | 1009 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1010 | clocks = <&clks IMX6QDL_CLK_USDHC4>, |
1011 | <&clks IMX6QDL_CLK_USDHC4>, | |
1012 | <&clks IMX6QDL_CLK_USDHC4>; | |
0e87e043 | 1013 | clock-names = "ipg", "ahb", "per"; |
c104b6a2 | 1014 | bus-width = <4>; |
7d740f87 SG |
1015 | status = "disabled"; |
1016 | }; | |
1017 | ||
7b7d6727 | 1018 | i2c1: i2c@021a0000 { |
7d740f87 SG |
1019 | #address-cells = <1>; |
1020 | #size-cells = <0>; | |
5bdfba29 | 1021 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 | 1022 | reg = <0x021a0000 0x4000>; |
275c08b5 | 1023 | interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 1024 | clocks = <&clks IMX6QDL_CLK_I2C1>; |
7d740f87 SG |
1025 | status = "disabled"; |
1026 | }; | |
1027 | ||
7b7d6727 | 1028 | i2c2: i2c@021a4000 { |
7d740f87 SG |
1029 | #address-cells = <1>; |
1030 | #size-cells = <0>; | |
5bdfba29 | 1031 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 | 1032 | reg = <0x021a4000 0x4000>; |
275c08b5 | 1033 | interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 1034 | clocks = <&clks IMX6QDL_CLK_I2C2>; |
7d740f87 SG |
1035 | status = "disabled"; |
1036 | }; | |
1037 | ||
7b7d6727 | 1038 | i2c3: i2c@021a8000 { |
7d740f87 SG |
1039 | #address-cells = <1>; |
1040 | #size-cells = <0>; | |
5bdfba29 | 1041 | compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
7d740f87 | 1042 | reg = <0x021a8000 0x4000>; |
275c08b5 | 1043 | interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 1044 | clocks = <&clks IMX6QDL_CLK_I2C3>; |
7d740f87 SG |
1045 | status = "disabled"; |
1046 | }; | |
1047 | ||
1048 | romcp@021ac000 { | |
1049 | reg = <0x021ac000 0x4000>; | |
1050 | }; | |
1051 | ||
7b7d6727 | 1052 | mmdc0: mmdc@021b0000 { /* MMDC0 */ |
7d740f87 SG |
1053 | compatible = "fsl,imx6q-mmdc"; |
1054 | reg = <0x021b0000 0x4000>; | |
1055 | }; | |
1056 | ||
7b7d6727 | 1057 | mmdc1: mmdc@021b4000 { /* MMDC1 */ |
7d740f87 SG |
1058 | reg = <0x021b4000 0x4000>; |
1059 | }; | |
1060 | ||
05e3f8e7 HS |
1061 | weim: weim@021b8000 { |
1062 | compatible = "fsl,imx6q-weim"; | |
7d740f87 | 1063 | reg = <0x021b8000 0x4000>; |
275c08b5 | 1064 | interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 | 1065 | clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; |
7d740f87 SG |
1066 | }; |
1067 | ||
3fe6373b SG |
1068 | ocotp: ocotp@021bc000 { |
1069 | compatible = "fsl,imx6q-ocotp", "syscon"; | |
7d740f87 SG |
1070 | reg = <0x021bc000 0x4000>; |
1071 | }; | |
1072 | ||
7d740f87 SG |
1073 | tzasc@021d0000 { /* TZASC1 */ |
1074 | reg = <0x021d0000 0x4000>; | |
275c08b5 | 1075 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
1076 | }; |
1077 | ||
1078 | tzasc@021d4000 { /* TZASC2 */ | |
1079 | reg = <0x021d4000 0x4000>; | |
275c08b5 | 1080 | interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
1081 | }; |
1082 | ||
7b7d6727 | 1083 | audmux: audmux@021d8000 { |
f965cd55 | 1084 | compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; |
7d740f87 | 1085 | reg = <0x021d8000 0x4000>; |
f965cd55 | 1086 | status = "disabled"; |
7d740f87 SG |
1087 | }; |
1088 | ||
5e0c7cd4 | 1089 | mipi_csi: mipi@021dc000 { |
7d740f87 SG |
1090 | reg = <0x021dc000 0x4000>; |
1091 | }; | |
1092 | ||
4520e692 PZ |
1093 | mipi_dsi: mipi@021e0000 { |
1094 | #address-cells = <1>; | |
1095 | #size-cells = <0>; | |
7d740f87 | 1096 | reg = <0x021e0000 0x4000>; |
4520e692 PZ |
1097 | status = "disabled"; |
1098 | ||
70c2652c LY |
1099 | ports { |
1100 | #address-cells = <1>; | |
1101 | #size-cells = <0>; | |
1102 | ||
1103 | port@0 { | |
1104 | reg = <0>; | |
4520e692 | 1105 | |
70c2652c LY |
1106 | mipi_mux_0: endpoint { |
1107 | remote-endpoint = <&ipu1_di0_mipi>; | |
1108 | }; | |
4520e692 | 1109 | }; |
4520e692 | 1110 | |
70c2652c LY |
1111 | port@1 { |
1112 | reg = <1>; | |
4520e692 | 1113 | |
70c2652c LY |
1114 | mipi_mux_1: endpoint { |
1115 | remote-endpoint = <&ipu1_di1_mipi>; | |
1116 | }; | |
4520e692 PZ |
1117 | }; |
1118 | }; | |
7d740f87 SG |
1119 | }; |
1120 | ||
1121 | vdoa@021e4000 { | |
1122 | reg = <0x021e4000 0x4000>; | |
275c08b5 | 1123 | interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; |
7d740f87 SG |
1124 | }; |
1125 | ||
0c456cfa | 1126 | uart2: serial@021e8000 { |
7d740f87 SG |
1127 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1128 | reg = <0x021e8000 0x4000>; | |
275c08b5 | 1129 | interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1130 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
1131 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 1132 | clock-names = "ipg", "per"; |
72a5cebf HS |
1133 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; |
1134 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1135 | status = "disabled"; |
1136 | }; | |
1137 | ||
0c456cfa | 1138 | uart3: serial@021ec000 { |
7d740f87 SG |
1139 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1140 | reg = <0x021ec000 0x4000>; | |
275c08b5 | 1141 | interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1142 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
1143 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 1144 | clock-names = "ipg", "per"; |
72a5cebf HS |
1145 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; |
1146 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1147 | status = "disabled"; |
1148 | }; | |
1149 | ||
0c456cfa | 1150 | uart4: serial@021f0000 { |
7d740f87 SG |
1151 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1152 | reg = <0x021f0000 0x4000>; | |
275c08b5 | 1153 | interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1154 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
1155 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 1156 | clock-names = "ipg", "per"; |
72a5cebf HS |
1157 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; |
1158 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1159 | status = "disabled"; |
1160 | }; | |
1161 | ||
0c456cfa | 1162 | uart5: serial@021f4000 { |
7d740f87 SG |
1163 | compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; |
1164 | reg = <0x021f4000 0x4000>; | |
275c08b5 | 1165 | interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; |
8888f651 SG |
1166 | clocks = <&clks IMX6QDL_CLK_UART_IPG>, |
1167 | <&clks IMX6QDL_CLK_UART_SERIAL>; | |
0e87e043 | 1168 | clock-names = "ipg", "per"; |
72a5cebf HS |
1169 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; |
1170 | dma-names = "rx", "tx"; | |
7d740f87 SG |
1171 | status = "disabled"; |
1172 | }; | |
1173 | }; | |
91660d74 SH |
1174 | |
1175 | ipu1: ipu@02400000 { | |
4520e692 PZ |
1176 | #address-cells = <1>; |
1177 | #size-cells = <0>; | |
91660d74 SH |
1178 | compatible = "fsl,imx6q-ipu"; |
1179 | reg = <0x02400000 0x400000>; | |
275c08b5 TK |
1180 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, |
1181 | <0 5 IRQ_TYPE_LEVEL_HIGH>; | |
8888f651 SG |
1182 | clocks = <&clks IMX6QDL_CLK_IPU1>, |
1183 | <&clks IMX6QDL_CLK_IPU1_DI0>, | |
1184 | <&clks IMX6QDL_CLK_IPU1_DI1>; | |
91660d74 | 1185 | clock-names = "bus", "di0", "di1"; |
09ebf366 | 1186 | resets = <&src 2>; |
4520e692 | 1187 | |
c0470c38 PZ |
1188 | ipu1_csi0: port@0 { |
1189 | reg = <0>; | |
1190 | }; | |
1191 | ||
1192 | ipu1_csi1: port@1 { | |
1193 | reg = <1>; | |
1194 | }; | |
1195 | ||
4520e692 PZ |
1196 | ipu1_di0: port@2 { |
1197 | #address-cells = <1>; | |
1198 | #size-cells = <0>; | |
1199 | reg = <2>; | |
1200 | ||
1201 | ipu1_di0_disp0: endpoint@0 { | |
1202 | }; | |
1203 | ||
1204 | ipu1_di0_hdmi: endpoint@1 { | |
1205 | remote-endpoint = <&hdmi_mux_0>; | |
1206 | }; | |
1207 | ||
1208 | ipu1_di0_mipi: endpoint@2 { | |
1209 | remote-endpoint = <&mipi_mux_0>; | |
1210 | }; | |
1211 | ||
1212 | ipu1_di0_lvds0: endpoint@3 { | |
1213 | remote-endpoint = <&lvds0_mux_0>; | |
1214 | }; | |
1215 | ||
1216 | ipu1_di0_lvds1: endpoint@4 { | |
1217 | remote-endpoint = <&lvds1_mux_0>; | |
1218 | }; | |
1219 | }; | |
1220 | ||
1221 | ipu1_di1: port@3 { | |
1222 | #address-cells = <1>; | |
1223 | #size-cells = <0>; | |
1224 | reg = <3>; | |
1225 | ||
1226 | ipu1_di0_disp1: endpoint@0 { | |
1227 | }; | |
1228 | ||
1229 | ipu1_di1_hdmi: endpoint@1 { | |
1230 | remote-endpoint = <&hdmi_mux_1>; | |
1231 | }; | |
1232 | ||
1233 | ipu1_di1_mipi: endpoint@2 { | |
1234 | remote-endpoint = <&mipi_mux_1>; | |
1235 | }; | |
1236 | ||
1237 | ipu1_di1_lvds0: endpoint@3 { | |
1238 | remote-endpoint = <&lvds0_mux_1>; | |
1239 | }; | |
1240 | ||
1241 | ipu1_di1_lvds1: endpoint@4 { | |
1242 | remote-endpoint = <&lvds1_mux_1>; | |
1243 | }; | |
1244 | }; | |
91660d74 | 1245 | }; |
7d740f87 SG |
1246 | }; |
1247 | }; |