]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - arch/arm/boot/dts/imx6sl.dtsi
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: dts: imx6qdl: add baud clock and clock-names for ssi
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / imx6sl.dtsi
CommitLineData
e29fe21c
SG		 1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
13088c23 10#include <dt-bindings/interrupt-controller/irq.h>
e29fe21c
SG		 11#include "skeleton.dtsi"
12#include "imx6sl-pinfunc.h"
13#include <dt-bindings/clock/imx6sl-clock.h>
14
15/ {
16 aliases {
22970070 17 ethernet0 = &fec;
e29fe21c
SG		 18 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 gpio3 = &gpio4;
22 gpio4 = &gpio5;
640a7f3f
FE		 23 serial0 = &uart1;
24 serial1 = &uart2;
25 serial2 = &uart3;
26 serial3 = &uart4;
27 serial4 = &uart5;
28 spi0 = &ecspi1;
29 spi1 = &ecspi2;
30 spi2 = &ecspi3;
31 spi3 = &ecspi4;
8189c51f
PC		 32 usbphy0 = &usbphy1;
33 usbphy1 = &usbphy2;
e29fe21c
SG		 34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu@0 {
41 compatible = "arm,cortex-a9";
42 device_type = "cpu";
43 reg = <0x0>;
44 next-level-cache = <&L2>;
b0d300d3
JT		 45 operating-points = <
46 /* kHz uV */
47 996000 1275000
48 792000 1175000
49 396000 975000
50 >;
51 fsl,soc-operating-points = <
52 /* ARM kHz SOC-PU uV */
53 996000 1225000
54 792000 1175000
55 396000 1175000
56 >;
57 clock-latency = <61036>; /* two CLK32 periods */
58 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
59 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
60 <&clks IMX6SL_CLK_PLL1_SYS>;
61 clock-names = "arm", "pll2_pfd2_396m", "step",
62 "pll1_sw", "pll1_sys";
63 arm-supply = <&reg_arm>;
64 pu-supply = <&reg_pu>;
65 soc-supply = <&reg_soc>;
e29fe21c
SG		 66 };
67 };
68
69 intc: interrupt-controller@00a01000 {
70 compatible = "arm,cortex-a9-gic";
71 #interrupt-cells = <3>;
e29fe21c
SG		 72 interrupt-controller;
73 reg = <0x00a01000 0x1000>,
74 <0x00a00100 0x100>;
75 };
76
77 clocks {
78 #address-cells = <1>;
79 #size-cells = <0>;
80
81 ckil {
82 compatible = "fixed-clock";
4b2b4043 83 #clock-cells = <0>;
e29fe21c
SG		 84 clock-frequency = <32768>;
85 };
86
87 osc {
88 compatible = "fixed-clock";
4b2b4043 89 #clock-cells = <0>;
e29fe21c
SG		 90 clock-frequency = <24000000>;
91 };
92 };
93
94 soc {
95 #address-cells = <1>;
96 #size-cells = <1>;
97 compatible = "simple-bus";
98 interrupt-parent = <&intc>;
99 ranges;
100
248f15a3
AH		 101 ocram: sram@00900000 {
102 compatible = "mmio-sram";
103 reg = <0x00900000 0x20000>;
104 clocks = <&clks IMX6SL_CLK_OCRAM>;
105 };
106
e29fe21c
SG		 107 L2: l2-cache@00a02000 {
108 compatible = "arm,pl310-cache";
109 reg = <0x00a02000 0x1000>;
13088c23 110 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 111 cache-unified;
112 cache-level = <2>;
113 arm,tag-latency = <4 2 3>;
114 arm,data-latency = <4 2 3>;
115 };
116
117 pmu {
118 compatible = "arm,cortex-a9-pmu";
13088c23 119 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 120 };
121
122 aips1: aips-bus@02000000 {
123 compatible = "fsl,aips-bus", "simple-bus";
124 #address-cells = <1>;
125 #size-cells = <1>;
126 reg = <0x02000000 0x100000>;
127 ranges;
128
129 spba: spba-bus@02000000 {
130 compatible = "fsl,spba-bus", "simple-bus";
131 #address-cells = <1>;
132 #size-cells = <1>;
133 reg = <0x02000000 0x40000>;
134 ranges;
135
136 spdif: spdif@02004000 {
137 reg = <0x02004000 0x4000>;
13088c23 138 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 139 };
140
141 ecspi1: ecspi@02008000 {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
145 reg = <0x02008000 0x4000>;
13088c23 146 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 147 clocks = <&clks IMX6SL_CLK_ECSPI1>,
148 <&clks IMX6SL_CLK_ECSPI1>;
149 clock-names = "ipg", "per";
150 status = "disabled";
151 };
152
153 ecspi2: ecspi@0200c000 {
154 #address-cells = <1>;
155 #size-cells = <0>;
156 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
157 reg = <0x0200c000 0x4000>;
13088c23 158 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 159 clocks = <&clks IMX6SL_CLK_ECSPI2>,
160 <&clks IMX6SL_CLK_ECSPI2>;
161 clock-names = "ipg", "per";
162 status = "disabled";
163 };
164
165 ecspi3: ecspi@02010000 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
169 reg = <0x02010000 0x4000>;
13088c23 170 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 171 clocks = <&clks IMX6SL_CLK_ECSPI3>,
172 <&clks IMX6SL_CLK_ECSPI3>;
173 clock-names = "ipg", "per";
174 status = "disabled";
175 };
176
177 ecspi4: ecspi@02014000 {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
181 reg = <0x02014000 0x4000>;
13088c23 182 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 183 clocks = <&clks IMX6SL_CLK_ECSPI4>,
184 <&clks IMX6SL_CLK_ECSPI4>;
185 clock-names = "ipg", "per";
186 status = "disabled";
187 };
188
189 uart5: serial@02018000 {
6eb85f91
HS		 190 compatible = "fsl,imx6sl-uart",
191 "fsl,imx6q-uart", "fsl,imx21-uart";
e29fe21c 192 reg = <0x02018000 0x4000>;
13088c23 193 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 194 clocks = <&clks IMX6SL_CLK_UART>,
195 <&clks IMX6SL_CLK_UART_SERIAL>;
196 clock-names = "ipg", "per";
72a5cebf
HS		 197 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
198 dma-names = "rx", "tx";
e29fe21c
SG		 199 status = "disabled";
200 };
201
202 uart1: serial@02020000 {
6eb85f91
HS		 203 compatible = "fsl,imx6sl-uart",
204 "fsl,imx6q-uart", "fsl,imx21-uart";
e29fe21c 205 reg = <0x02020000 0x4000>;
13088c23 206 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 207 clocks = <&clks IMX6SL_CLK_UART>,
208 <&clks IMX6SL_CLK_UART_SERIAL>;
209 clock-names = "ipg", "per";
72a5cebf
HS		 210 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
211 dma-names = "rx", "tx";
e29fe21c
SG		 212 status = "disabled";
213 };
214
215 uart2: serial@02024000 {
6eb85f91
HS		 216 compatible = "fsl,imx6sl-uart",
217 "fsl,imx6q-uart", "fsl,imx21-uart";
e29fe21c 218 reg = <0x02024000 0x4000>;
13088c23 219 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 220 clocks = <&clks IMX6SL_CLK_UART>,
221 <&clks IMX6SL_CLK_UART_SERIAL>;
222 clock-names = "ipg", "per";
72a5cebf
HS		 223 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
224 dma-names = "rx", "tx";
e29fe21c
SG		 225 status = "disabled";
226 };
227
228 ssi1: ssi@02028000 {
6ff7f51e 229 #sound-dai-cells = <0>;
98ea6ad2 230 compatible = "fsl,imx6sl-ssi",
4c03527e 231 "fsl,imx51-ssi";
e29fe21c 232 reg = <0x02028000 0x4000>;
13088c23 233 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c 234 clocks = <&clks IMX6SL_CLK_SSI1>;
5da826ab
SG		 235 dmas = <&sdma 37 1 0>,
236 <&sdma 38 1 0>;
237 dma-names = "rx", "tx";
e29fe21c
SG		 238 fsl,fifo-depth = <15>;
239 status = "disabled";
240 };
241
242 ssi2: ssi@0202c000 {
6ff7f51e 243 #sound-dai-cells = <0>;
98ea6ad2 244 compatible = "fsl,imx6sl-ssi",
4c03527e 245 "fsl,imx51-ssi";
e29fe21c 246 reg = <0x0202c000 0x4000>;
13088c23 247 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c 248 clocks = <&clks IMX6SL_CLK_SSI2>;
5da826ab
SG		 249 dmas = <&sdma 41 1 0>,
250 <&sdma 42 1 0>;
251 dma-names = "rx", "tx";
e29fe21c
SG		 252 fsl,fifo-depth = <15>;
253 status = "disabled";
254 };
255
256 ssi3: ssi@02030000 {
6ff7f51e 257 #sound-dai-cells = <0>;
98ea6ad2 258 compatible = "fsl,imx6sl-ssi",
4c03527e 259 "fsl,imx51-ssi";
e29fe21c 260 reg = <0x02030000 0x4000>;
13088c23 261 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c 262 clocks = <&clks IMX6SL_CLK_SSI3>;
5da826ab
SG		 263 dmas = <&sdma 45 1 0>,
264 <&sdma 46 1 0>;
265 dma-names = "rx", "tx";
e29fe21c
SG		 266 fsl,fifo-depth = <15>;
267 status = "disabled";
268 };
269
270 uart3: serial@02034000 {
6eb85f91
HS		 271 compatible = "fsl,imx6sl-uart",
272 "fsl,imx6q-uart", "fsl,imx21-uart";
e29fe21c 273 reg = <0x02034000 0x4000>;
13088c23 274 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 275 clocks = <&clks IMX6SL_CLK_UART>,
276 <&clks IMX6SL_CLK_UART_SERIAL>;
277 clock-names = "ipg", "per";
72a5cebf
HS		 278 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
279 dma-names = "rx", "tx";
e29fe21c
SG		 280 status = "disabled";
281 };
282
283 uart4: serial@02038000 {
6eb85f91
HS		 284 compatible = "fsl,imx6sl-uart",
285 "fsl,imx6q-uart", "fsl,imx21-uart";
e29fe21c 286 reg = <0x02038000 0x4000>;
13088c23 287 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 288 clocks = <&clks IMX6SL_CLK_UART>,
289 <&clks IMX6SL_CLK_UART_SERIAL>;
290 clock-names = "ipg", "per";
72a5cebf
HS		 291 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
292 dma-names = "rx", "tx";
e29fe21c
SG		 293 status = "disabled";
294 };
295 };
296
297 pwm1: pwm@02080000 {
298 #pwm-cells = <2>;
299 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
300 reg = <0x02080000 0x4000>;
13088c23 301 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 302 clocks = <&clks IMX6SL_CLK_PWM1>,
303 <&clks IMX6SL_CLK_PWM1>;
304 clock-names = "ipg", "per";
305 };
306
307 pwm2: pwm@02084000 {
308 #pwm-cells = <2>;
309 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
310 reg = <0x02084000 0x4000>;
13088c23 311 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 312 clocks = <&clks IMX6SL_CLK_PWM2>,
313 <&clks IMX6SL_CLK_PWM2>;
314 clock-names = "ipg", "per";
315 };
316
317 pwm3: pwm@02088000 {
318 #pwm-cells = <2>;
319 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
320 reg = <0x02088000 0x4000>;
13088c23 321 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 322 clocks = <&clks IMX6SL_CLK_PWM3>,
323 <&clks IMX6SL_CLK_PWM3>;
324 clock-names = "ipg", "per";
325 };
326
327 pwm4: pwm@0208c000 {
328 #pwm-cells = <2>;
329 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
330 reg = <0x0208c000 0x4000>;
13088c23 331 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 332 clocks = <&clks IMX6SL_CLK_PWM4>,
333 <&clks IMX6SL_CLK_PWM4>;
334 clock-names = "ipg", "per";
335 };
336
337 gpt: gpt@02098000 {
338 compatible = "fsl,imx6sl-gpt";
339 reg = <0x02098000 0x4000>;
13088c23 340 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 341 clocks = <&clks IMX6SL_CLK_GPT>,
342 <&clks IMX6SL_CLK_GPT_SERIAL>;
343 clock-names = "ipg", "per";
344 };
345
346 gpio1: gpio@0209c000 {
347 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
348 reg = <0x0209c000 0x4000>;
13088c23
TK		 349 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
350 <0 67 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 351 gpio-controller;
352 #gpio-cells = <2>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
355 };
356
357 gpio2: gpio@020a0000 {
358 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
359 reg = <0x020a0000 0x4000>;
13088c23
TK		 360 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
361 <0 69 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 362 gpio-controller;
363 #gpio-cells = <2>;
364 interrupt-controller;
365 #interrupt-cells = <2>;
366 };
367
368 gpio3: gpio@020a4000 {
369 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
370 reg = <0x020a4000 0x4000>;
13088c23
TK		 371 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
372 <0 71 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 373 gpio-controller;
374 #gpio-cells = <2>;
375 interrupt-controller;
376 #interrupt-cells = <2>;
377 };
378
379 gpio4: gpio@020a8000 {
380 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
381 reg = <0x020a8000 0x4000>;
13088c23
TK		 382 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
383 <0 73 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 384 gpio-controller;
385 #gpio-cells = <2>;
386 interrupt-controller;
387 #interrupt-cells = <2>;
388 };
389
390 gpio5: gpio@020ac000 {
391 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
392 reg = <0x020ac000 0x4000>;
13088c23
TK		 393 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
394 <0 75 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 395 gpio-controller;
396 #gpio-cells = <2>;
397 interrupt-controller;
398 #interrupt-cells = <2>;
399 };
400
401 kpp: kpp@020b8000 {
4291b645 402 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
e29fe21c 403 reg = <0x020b8000 0x4000>;
13088c23 404 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
4291b645 405 clocks = <&clks IMX6SL_CLK_DUMMY>;
1b6f2368 406 status = "disabled";
e29fe21c
SG		 407 };
408
409 wdog1: wdog@020bc000 {
410 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
411 reg = <0x020bc000 0x4000>;
13088c23 412 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 413 clocks = <&clks IMX6SL_CLK_DUMMY>;
414 };
415
416 wdog2: wdog@020c0000 {
417 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
418 reg = <0x020c0000 0x4000>;
13088c23 419 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 420 clocks = <&clks IMX6SL_CLK_DUMMY>;
421 status = "disabled";
422 };
423
424 clks: ccm@020c4000 {
425 compatible = "fsl,imx6sl-ccm";
426 reg = <0x020c4000 0x4000>;
13088c23
TK		 427 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
428 <0 88 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 429 #clock-cells = <1>;
430 };
431
432 anatop: anatop@020c8000 {
d8ce823f
SG		 433 compatible = "fsl,imx6sl-anatop",
434 "fsl,imx6q-anatop",
435 "syscon", "simple-bus";
e29fe21c 436 reg = <0x020c8000 0x1000>;
13088c23
TK		 437 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
438 <0 54 IRQ_TYPE_LEVEL_HIGH>,
439 <0 127 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 440
441 regulator-1p1@110 {
442 compatible = "fsl,anatop-regulator";
443 regulator-name = "vdd1p1";
444 regulator-min-microvolt = <800000>;
445 regulator-max-microvolt = <1375000>;
446 regulator-always-on;
447 anatop-reg-offset = <0x110>;
448 anatop-vol-bit-shift = <8>;
449 anatop-vol-bit-width = <5>;
450 anatop-min-bit-val = <4>;
451 anatop-min-voltage = <800000>;
452 anatop-max-voltage = <1375000>;
453 };
454
455 regulator-3p0@120 {
456 compatible = "fsl,anatop-regulator";
457 regulator-name = "vdd3p0";
458 regulator-min-microvolt = <2800000>;
459 regulator-max-microvolt = <3150000>;
460 regulator-always-on;
461 anatop-reg-offset = <0x120>;
462 anatop-vol-bit-shift = <8>;
463 anatop-vol-bit-width = <5>;
464 anatop-min-bit-val = <0>;
465 anatop-min-voltage = <2625000>;
466 anatop-max-voltage = <3400000>;
467 };
468
469 regulator-2p5@130 {
470 compatible = "fsl,anatop-regulator";
471 regulator-name = "vdd2p5";
472 regulator-min-microvolt = <2100000>;
473 regulator-max-microvolt = <2850000>;
474 regulator-always-on;
475 anatop-reg-offset = <0x130>;
476 anatop-vol-bit-shift = <8>;
477 anatop-vol-bit-width = <5>;
478 anatop-min-bit-val = <0>;
479 anatop-min-voltage = <2100000>;
480 anatop-max-voltage = <2850000>;
481 };
482
483 reg_arm: regulator-vddcore@140 {
484 compatible = "fsl,anatop-regulator";
118c98a6 485 regulator-name = "vddarm";
e29fe21c
SG		 486 regulator-min-microvolt = <725000>;
487 regulator-max-microvolt = <1450000>;
488 regulator-always-on;
489 anatop-reg-offset = <0x140>;
490 anatop-vol-bit-shift = <0>;
491 anatop-vol-bit-width = <5>;
492 anatop-delay-reg-offset = <0x170>;
493 anatop-delay-bit-shift = <24>;
494 anatop-delay-bit-width = <2>;
495 anatop-min-bit-val = <1>;
496 anatop-min-voltage = <725000>;
497 anatop-max-voltage = <1450000>;
498 };
499
500 reg_pu: regulator-vddpu@140 {
501 compatible = "fsl,anatop-regulator";
502 regulator-name = "vddpu";
503 regulator-min-microvolt = <725000>;
504 regulator-max-microvolt = <1450000>;
505 regulator-always-on;
506 anatop-reg-offset = <0x140>;
507 anatop-vol-bit-shift = <9>;
508 anatop-vol-bit-width = <5>;
509 anatop-delay-reg-offset = <0x170>;
510 anatop-delay-bit-shift = <26>;
511 anatop-delay-bit-width = <2>;
512 anatop-min-bit-val = <1>;
513 anatop-min-voltage = <725000>;
514 anatop-max-voltage = <1450000>;
515 };
516
517 reg_soc: regulator-vddsoc@140 {
518 compatible = "fsl,anatop-regulator";
519 regulator-name = "vddsoc";
520 regulator-min-microvolt = <725000>;
521 regulator-max-microvolt = <1450000>;
522 regulator-always-on;
523 anatop-reg-offset = <0x140>;
524 anatop-vol-bit-shift = <18>;
525 anatop-vol-bit-width = <5>;
526 anatop-delay-reg-offset = <0x170>;
527 anatop-delay-bit-shift = <28>;
528 anatop-delay-bit-width = <2>;
529 anatop-min-bit-val = <1>;
530 anatop-min-voltage = <725000>;
531 anatop-max-voltage = <1450000>;
532 };
533 };
534
2998b332
AH		 535 tempmon: tempmon {
536 compatible = "fsl,imx6q-tempmon";
537 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
538 fsl,tempmon = <&anatop>;
539 fsl,tempmon-data = <&ocotp>;
540 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
541 };
542
e29fe21c
SG		 543 usbphy1: usbphy@020c9000 {
544 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
545 reg = <0x020c9000 0x1000>;
13088c23 546 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c 547 clocks = <&clks IMX6SL_CLK_USBPHY1>;
76a38855 548 fsl,anatop = <&anatop>;
e29fe21c
SG		 549 };
550
551 usbphy2: usbphy@020ca000 {
552 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
553 reg = <0x020ca000 0x1000>;
13088c23 554 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c 555 clocks = <&clks IMX6SL_CLK_USBPHY2>;
76a38855 556 fsl,anatop = <&anatop>;
e29fe21c
SG		 557 };
558
559 snvs@020cc000 {
560 compatible = "fsl,sec-v4.0-mon", "simple-bus";
561 #address-cells = <1>;
562 #size-cells = <1>;
563 ranges = <0 0x020cc000 0x4000>;
564
565 snvs-rtc-lp@34 {
566 compatible = "fsl,sec-v4.0-mon-rtc-lp";
567 reg = <0x34 0x58>;
13088c23
TK		 568 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
569 <0 20 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 570 };
571 };
572
573 epit1: epit@020d0000 {
574 reg = <0x020d0000 0x4000>;
13088c23 575 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 576 };
577
578 epit2: epit@020d4000 {
579 reg = <0x020d4000 0x4000>;
13088c23 580 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 581 };
582
583 src: src@020d8000 {
584 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
585 reg = <0x020d8000 0x4000>;
13088c23
TK		 586 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
587 <0 96 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 588 #reset-cells = <1>;
589 };
590
591 gpc: gpc@020dc000 {
592 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
593 reg = <0x020dc000 0x4000>;
13088c23 594 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 595 };
596
e03d10f9 597 gpr: iomuxc-gpr@020e0000 {
5f7adc97
SG		 598 compatible = "fsl,imx6sl-iomuxc-gpr",
599 "fsl,imx6q-iomuxc-gpr", "syscon";
e03d10f9
FD		 600 reg = <0x020e0000 0x38>;
601 };
e29fe21c
SG		 602
603 iomuxc: iomuxc@020e0000 {
604 compatible = "fsl,imx6sl-iomuxc";
605 reg = <0x020e0000 0x4000>;
e29fe21c
SG		 606 };
607
608 csi: csi@020e4000 {
609 reg = <0x020e4000 0x4000>;
13088c23 610 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 611 };
612
613 spdc: spdc@020e8000 {
614 reg = <0x020e8000 0x4000>;
13088c23 615 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 616 };
617
618 sdma: sdma@020ec000 {
811e7685 619 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
e29fe21c 620 reg = <0x020ec000 0x4000>;
13088c23 621 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 622 clocks = <&clks IMX6SL_CLK_SDMA>,
623 <&clks IMX6SL_CLK_SDMA>;
624 clock-names = "ipg", "ahb";
fb72bb21 625 #dma-cells = <3>;
44a26877
SG		 626 /* imx6sl reuses imx6q sdma firmware */
627 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
e29fe21c
SG		 628 };
629
630 pxp: pxp@020f0000 {
631 reg = <0x020f0000 0x4000>;
13088c23 632 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 633 };
634
635 epdc: epdc@020f4000 {
636 reg = <0x020f4000 0x4000>;
13088c23 637 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 638 };
639
640 lcdif: lcdif@020f8000 {
e99b077b 641 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
e29fe21c 642 reg = <0x020f8000 0x4000>;
13088c23 643 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
e99b077b
FE		 644 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
645 <&clks IMX6SL_CLK_LCDIF_AXI>,
646 <&clks IMX6SL_CLK_DUMMY>;
647 clock-names = "pix", "axi", "disp_axi";
648 status = "disabled";
e29fe21c
SG		 649 };
650
651 dcp: dcp@020fc000 {
652 reg = <0x020fc000 0x4000>;
13088c23 653 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 654 };
655 };
656
657 aips2: aips-bus@02100000 {
658 compatible = "fsl,aips-bus", "simple-bus";
659 #address-cells = <1>;
660 #size-cells = <1>;
661 reg = <0x02100000 0x100000>;
662 ranges;
663
664 usbotg1: usb@02184000 {
665 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
666 reg = <0x02184000 0x200>;
13088c23 667 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 668 clocks = <&clks IMX6SL_CLK_USBOH3>;
669 fsl,usbphy = <&usbphy1>;
670 fsl,usbmisc = <&usbmisc 0>;
671 status = "disabled";
672 };
673
674 usbotg2: usb@02184200 {
675 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
676 reg = <0x02184200 0x200>;
13088c23 677 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 678 clocks = <&clks IMX6SL_CLK_USBOH3>;
679 fsl,usbphy = <&usbphy2>;
680 fsl,usbmisc = <&usbmisc 1>;
681 status = "disabled";
682 };
683
684 usbh: usb@02184400 {
685 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
686 reg = <0x02184400 0x200>;
13088c23 687 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 688 clocks = <&clks IMX6SL_CLK_USBOH3>;
689 fsl,usbmisc = <&usbmisc 2>;
690 status = "disabled";
691 };
692
693 usbmisc: usbmisc@02184800 {
694 #index-cells = <1>;
695 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
696 reg = <0x02184800 0x200>;
697 clocks = <&clks IMX6SL_CLK_USBOH3>;
698 };
699
700 fec: ethernet@02188000 {
701 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
702 reg = <0x02188000 0x4000>;
13088c23 703 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
8c562a1e 704 clocks = <&clks IMX6SL_CLK_ENET>,
e29fe21c
SG		 705 <&clks IMX6SL_CLK_ENET_REF>;
706 clock-names = "ipg", "ahb";
707 status = "disabled";
708 };
709
710 usdhc1: usdhc@02190000 {
711 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
712 reg = <0x02190000 0x4000>;
13088c23 713 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 714 clocks = <&clks IMX6SL_CLK_USDHC1>,
715 <&clks IMX6SL_CLK_USDHC1>,
716 <&clks IMX6SL_CLK_USDHC1>;
717 clock-names = "ipg", "ahb", "per";
718 bus-width = <4>;
719 status = "disabled";
720 };
721
722 usdhc2: usdhc@02194000 {
723 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
724 reg = <0x02194000 0x4000>;
13088c23 725 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 726 clocks = <&clks IMX6SL_CLK_USDHC2>,
727 <&clks IMX6SL_CLK_USDHC2>,
728 <&clks IMX6SL_CLK_USDHC2>;
729 clock-names = "ipg", "ahb", "per";
730 bus-width = <4>;
731 status = "disabled";
732 };
733
734 usdhc3: usdhc@02198000 {
735 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
736 reg = <0x02198000 0x4000>;
13088c23 737 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 738 clocks = <&clks IMX6SL_CLK_USDHC3>,
739 <&clks IMX6SL_CLK_USDHC3>,
740 <&clks IMX6SL_CLK_USDHC3>;
741 clock-names = "ipg", "ahb", "per";
742 bus-width = <4>;
743 status = "disabled";
744 };
745
746 usdhc4: usdhc@0219c000 {
747 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
748 reg = <0x0219c000 0x4000>;
13088c23 749 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 750 clocks = <&clks IMX6SL_CLK_USDHC4>,
751 <&clks IMX6SL_CLK_USDHC4>,
752 <&clks IMX6SL_CLK_USDHC4>;
753 clock-names = "ipg", "ahb", "per";
754 bus-width = <4>;
755 status = "disabled";
756 };
757
758 i2c1: i2c@021a0000 {
759 #address-cells = <1>;
760 #size-cells = <0>;
761 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
762 reg = <0x021a0000 0x4000>;
13088c23 763 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 764 clocks = <&clks IMX6SL_CLK_I2C1>;
765 status = "disabled";
766 };
767
768 i2c2: i2c@021a4000 {
769 #address-cells = <1>;
770 #size-cells = <0>;
771 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
772 reg = <0x021a4000 0x4000>;
13088c23 773 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 774 clocks = <&clks IMX6SL_CLK_I2C2>;
775 status = "disabled";
776 };
777
778 i2c3: i2c@021a8000 {
779 #address-cells = <1>;
780 #size-cells = <0>;
781 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
782 reg = <0x021a8000 0x4000>;
13088c23 783 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 784 clocks = <&clks IMX6SL_CLK_I2C3>;
785 status = "disabled";
786 };
787
788 mmdc: mmdc@021b0000 {
789 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
790 reg = <0x021b0000 0x4000>;
791 };
792
793 rngb: rngb@021b4000 {
794 reg = <0x021b4000 0x4000>;
13088c23 795 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 796 };
797
798 weim: weim@021b8000 {
799 reg = <0x021b8000 0x4000>;
13088c23 800 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
e29fe21c
SG		 801 };
802
803 ocotp: ocotp@021bc000 {
2998b332 804 compatible = "fsl,imx6sl-ocotp", "syscon";
e29fe21c
SG		 805 reg = <0x021bc000 0x4000>;
806 };
807
808 audmux: audmux@021d8000 {
809 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
810 reg = <0x021d8000 0x4000>;
811 status = "disabled";
812 };
813 };
814 };
815};
ubuntu-bionic-kernel mirror