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amd-xgbe: Use proper Rx flow control register
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / imx6sx-sdb.dts
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d2daa2f7
SG		 1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
4014a4f7
AH		 11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
d2daa2f7
SG		 13#include "imx6sx.dtsi"
14
15/ {
16 model = "Freescale i.MX6 SoloX SDB Board";
17 compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
18
19 chosen {
20 stdout-path = &uart1;
21 };
22
23 memory {
24 reg = <0x80000000 0x40000000>;
25 };
26
31ffdbc8
FE		 27 backlight {
28 compatible = "pwm-backlight";
29 pwms = <&pwm3 0 5000000>;
30 brightness-levels = <0 4 8 16 32 64 128 255>;
31 default-brightness-level = <6>;
32 };
33
4014a4f7
AH		 34 gpio-keys {
35 compatible = "gpio-keys";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_gpio_keys>;
38
39 volume-up {
40 label = "Volume Up";
41 gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_VOLUMEUP>;
43 };
44
45 volume-down {
46 label = "Volume Down";
47 gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
48 linux,code = <KEY_VOLUMEDOWN>;
49 };
50 };
51
d2daa2f7
SG		 52 regulators {
53 compatible = "simple-bus";
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 vcc_sd3: regulator@0 {
58 compatible = "regulator-fixed";
59 reg = <0>;
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_vcc_sd3>;
62 regulator-name = "VCC_SD3";
63 regulator-min-microvolt = <3000000>;
64 regulator-max-microvolt = <3000000>;
65 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
66 enable-active-high;
67 };
960fefff
FE		 68
69 reg_usb_otg1_vbus: regulator@1 {
70 compatible = "regulator-fixed";
71 reg = <1>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_usb_otg1>;
74 regulator-name = "usb_otg1_vbus";
75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <5000000>;
77 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
78 enable-active-high;
79 };
80
81 reg_usb_otg2_vbus: regulator@2 {
82 compatible = "regulator-fixed";
83 reg = <2>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_usb_otg2>;
86 regulator-name = "usb_otg2_vbus";
87 regulator-min-microvolt = <5000000>;
88 regulator-max-microvolt = <5000000>;
89 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
90 enable-active-high;
91 };
9c86ae8c
FE		 92
93 reg_psu_5v: regulator@3 {
94 compatible = "regulator-fixed";
95 reg = <3>;
96 regulator-name = "PSU-5V0";
97 regulator-min-microvolt = <5000000>;
98 regulator-max-microvolt = <5000000>;
99 };
31ffdbc8
FE		 100
101 reg_lcd_3v3: regulator@4 {
102 compatible = "regulator-fixed";
103 reg = <4>;
104 regulator-name = "lcd-3v3";
105 gpio = <&gpio3 27 0>;
106 enable-active-high;
107 };
9863aba5
FD		 108
109 reg_peri_3v3: regulator@5 {
110 compatible = "regulator-fixed";
111 reg = <5>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_peri_3v3>;
114 regulator-name = "peri_3v3";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
118 enable-active-high;
119 regulator-always-on;
120 };
121
122 reg_enet_3v3: regulator@6 {
123 compatible = "regulator-fixed";
124 reg = <6>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_enet_3v3>;
127 regulator-name = "enet_3v3";
128 regulator-min-microvolt = <3300000>;
129 regulator-max-microvolt = <3300000>;
130 gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
131 };
9c86ae8c
FE		 132 };
133
134 sound {
135 compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
136 model = "wm8962-audio";
137 ssi-controller = <&ssi2>;
138 audio-codec = <&codec>;
139 audio-routing =
140 "Headphone Jack", "HPOUTL",
141 "Headphone Jack", "HPOUTR",
142 "Ext Spk", "SPKOUTL",
143 "Ext Spk", "SPKOUTR",
144 "AMIC", "MICBIAS",
145 "IN3R", "AMIC";
146 mux-int-port = <2>;
147 mux-ext-port = <6>;
d2daa2f7
SG		 148 };
149};
150
9c86ae8c
FE		 151&audmux {
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_audmux>;
154 status = "okay";
155};
156
d2daa2f7
SG		 157&fec1 {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_enet1>;
9863aba5
FD		 160 phy-supply = <&reg_enet_3v3>;
161 phy-mode = "rgmii";
3d125f9c 162 phy-handle = <&ethphy1>;
9863aba5 163 status = "okay";
3d125f9c
SA		 164
165 mdio {
166 #address-cells = <1>;
167 #size-cells = <0>;
168
169 ethphy1: ethernet-phy@0 {
170 reg = <0>;
171 };
172
173 ethphy2: ethernet-phy@1 {
174 reg = <1>;
175 };
176 };
9863aba5
FD		 177};
178
179&fec2 {
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_enet2>;
d2daa2f7 182 phy-mode = "rgmii";
3d125f9c 183 phy-handle = <&ethphy2>;
d2daa2f7
SG		 184 status = "okay";
185};
186
b3d8e11f
FE		 187&i2c1 {
188 clock-frequency = <100000>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_i2c1>;
191 status = "okay";
192
193 pmic: pfuze100@08 {
194 compatible = "fsl,pfuze100";
195 reg = <0x08>;
196
197 regulators {
198 sw1a_reg: sw1ab {
199 regulator-min-microvolt = <300000>;
200 regulator-max-microvolt = <1875000>;
201 regulator-boot-on;
202 regulator-always-on;
203 regulator-ramp-delay = <6250>;
204 };
205
206 sw1c_reg: sw1c {
207 regulator-min-microvolt = <300000>;
208 regulator-max-microvolt = <1875000>;
209 regulator-boot-on;
210 regulator-always-on;
211 regulator-ramp-delay = <6250>;
212 };
213
214 sw2_reg: sw2 {
215 regulator-min-microvolt = <800000>;
216 regulator-max-microvolt = <3300000>;
217 regulator-boot-on;
218 regulator-always-on;
219 };
220
221 sw3a_reg: sw3a {
222 regulator-min-microvolt = <400000>;
223 regulator-max-microvolt = <1975000>;
224 regulator-boot-on;
225 regulator-always-on;
226 };
227
228 sw3b_reg: sw3b {
229 regulator-min-microvolt = <400000>;
230 regulator-max-microvolt = <1975000>;
231 regulator-boot-on;
232 regulator-always-on;
233 };
234
235 sw4_reg: sw4 {
236 regulator-min-microvolt = <800000>;
237 regulator-max-microvolt = <3300000>;
238 };
239
240 swbst_reg: swbst {
241 regulator-min-microvolt = <5000000>;
242 regulator-max-microvolt = <5150000>;
243 };
244
245 snvs_reg: vsnvs {
246 regulator-min-microvolt = <1000000>;
247 regulator-max-microvolt = <3000000>;
248 regulator-boot-on;
249 regulator-always-on;
250 };
251
252 vref_reg: vrefddr {
253 regulator-boot-on;
254 regulator-always-on;
255 };
256
257 vgen1_reg: vgen1 {
258 regulator-min-microvolt = <800000>;
259 regulator-max-microvolt = <1550000>;
260 regulator-always-on;
261 };
262
263 vgen2_reg: vgen2 {
264 regulator-min-microvolt = <800000>;
265 regulator-max-microvolt = <1550000>;
266 };
267
268 vgen3_reg: vgen3 {
269 regulator-min-microvolt = <1800000>;
270 regulator-max-microvolt = <3300000>;
271 regulator-always-on;
272 };
273
274 vgen4_reg: vgen4 {
275 regulator-min-microvolt = <1800000>;
276 regulator-max-microvolt = <3300000>;
277 regulator-always-on;
278 };
279
280 vgen5_reg: vgen5 {
281 regulator-min-microvolt = <1800000>;
282 regulator-max-microvolt = <3300000>;
283 regulator-always-on;
284 };
285
286 vgen6_reg: vgen6 {
287 regulator-min-microvolt = <1800000>;
288 regulator-max-microvolt = <3300000>;
289 regulator-always-on;
290 };
291 };
292 };
293};
294
9c86ae8c
FE		 295&i2c4 {
296 clock-frequency = <100000>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_i2c4>;
299 status = "okay";
300
301 codec: wm8962@1a {
302 compatible = "wlf,wm8962";
303 reg = <0x1a>;
304 clocks = <&clks IMX6SX_CLK_AUDIO>;
305 DCVDD-supply = <&vgen4_reg>;
306 DBVDD-supply = <&vgen4_reg>;
307 AVDD-supply = <&vgen4_reg>;
308 CPVDD-supply = <&vgen4_reg>;
309 MICVDD-supply = <&vgen3_reg>;
310 PLLVDD-supply = <&vgen4_reg>;
311 SPKVDD1-supply = <&reg_psu_5v>;
312 SPKVDD2-supply = <&reg_psu_5v>;
313 };
314};
315
31ffdbc8
FE		 316&lcdif1 {
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_lcd>;
319 lcd-supply = <&reg_lcd_3v3>;
320 display = <&display0>;
321 status = "okay";
322
323 display0: display0 {
324 bits-per-pixel = <16>;
325 bus-width = <24>;
326
327 display-timings {
328 native-mode = <&timing0>;
329 timing0: timing0 {
330 clock-frequency = <33500000>;
331 hactive = <800>;
332 vactive = <480>;
333 hback-porch = <89>;
334 hfront-porch = <164>;
335 vback-porch = <23>;
336 vfront-porch = <10>;
337 hsync-len = <10>;
338 vsync-len = <10>;
339 hsync-active = <0>;
340 vsync-active = <0>;
341 de-active = <1>;
342 pixelclk-active = <0>;
343 };
344 };
345 };
346};
347
348&pwm3 {
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_pwm3>;
351 status = "okay";
352};
353
422b0676
RG		 354&snvs_poweroff {
355 status = "okay";
356};
357
9c86ae8c
FE		 358&ssi2 {
359 status = "okay";
360};
361
d2daa2f7
SG		 362&uart1 {
363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_uart1>;
365 status = "okay";
366};
367
368&uart5 { /* for bluetooth */
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_uart5>;
371 fsl,uart-has-rtscts;
372 status = "okay";
373};
374
960fefff
FE		 375&usbotg1 {
376 vbus-supply = <&reg_usb_otg1_vbus>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&pinctrl_usb_otg1_id>;
379 status = "okay";
380};
381
382&usbotg2 {
383 vbus-supply = <&reg_usb_otg2_vbus>;
384 dr_mode = "host";
385 status = "okay";
386};
387
d2daa2f7
SG		 388&usdhc2 {
389 pinctrl-names = "default";
390 pinctrl-0 = <&pinctrl_usdhc2>;
391 non-removable;
392 no-1-8-v;
393 keep-power-in-suspend;
394 enable-sdio-wakeup;
395 status = "okay";
396};
397
398&usdhc3 {
399 pinctrl-names = "default", "state_100mhz", "state_200mhz";
400 pinctrl-0 = <&pinctrl_usdhc3>;
401 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
402 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
403 bus-width = <8>;
404 cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
405 wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
406 keep-power-in-suspend;
407 enable-sdio-wakeup;
408 vmmc-supply = <&vcc_sd3>;
409 status = "okay";
410};
411
412&usdhc4 {
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_usdhc4>;
415 cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
416 wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
417 status = "okay";
418};
419
420&iomuxc {
421 imx6x-sdb {
9c86ae8c
FE		 422 pinctrl_audmux: audmuxgrp {
423 fsl,pins = <
424 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
425 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
426 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
427 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
428 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
429 >;
430 };
431
d2daa2f7
SG		 432 pinctrl_enet1: enet1grp {
433 fsl,pins = <
434 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
435 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
436 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
437 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
438 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
439 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
440 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
441 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
442 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
443 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
444 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
445 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
446 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
447 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
9863aba5
FD		 448 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
449 >;
450 };
451
452 pinctrl_enet_3v3: enet3v3grp {
453 fsl,pins = <
454 MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
455 >;
456 };
457
458 pinctrl_enet2: enet2grp {
459 fsl,pins = <
460 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
461 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
462 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
463 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
464 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
465 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
466 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
467 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
468 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
469 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
470 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
471 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
d2daa2f7
SG		 472 >;
473 };
474
4014a4f7
AH		 475 pinctrl_gpio_keys: gpio_keysgrp {
476 fsl,pins = <
477 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
478 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
479 >;
480 };
481
b3d8e11f
FE		 482 pinctrl_i2c1: i2c1grp {
483 fsl,pins = <
484 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
485 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
486 >;
487 };
488
9c86ae8c
FE		 489 pinctrl_i2c4: i2c4grp {
490 fsl,pins = <
491 MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
492 MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
493 >;
494 };
495
31ffdbc8
FE		 496 pinctrl_lcd: lcdgrp {
497 fsl,pins = <
498 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
499 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
500 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
501 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
502 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
503 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
504 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
505 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
506 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
507 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
508 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
509 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
510 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
511 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
512 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
513 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
514 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
515 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
516 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
517 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
518 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
519 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
520 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
521 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
522 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
523 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
524 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
525 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
526 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
527 >;
528 };
529
9863aba5
FD		 530 pinctrl_peri_3v3: peri3v3grp {
531 fsl,pins = <
532 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
533 >;
534 };
535
31ffdbc8
FE		 536 pinctrl_pwm3: pwm3grp-1 {
537 fsl,pins = <
538 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
539 >;
540 };
541
d2daa2f7
SG		 542 pinctrl_vcc_sd3: vccsd3grp {
543 fsl,pins = <
544 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
545 >;
546 };
547
548 pinctrl_uart1: uart1grp {
549 fsl,pins = <
550 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
551 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
552 >;
553 };
554
555 pinctrl_uart5: uart5grp {
556 fsl,pins = <
557 MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
558 MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
559 MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
560 MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
561 >;
562 };
563
960fefff
FE		 564 pinctrl_usb_otg1: usbotg1grp {
565 fsl,pins = <
566 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
567 >;
568 };
569
570 pinctrl_usb_otg1_id: usbotg1idgrp {
571 fsl,pins = <
572 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
573 >;
574 };
575
576 pinctrl_usb_otg2: usbot2ggrp {
577 fsl,pins = <
578 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
579 >;
580 };
581
d2daa2f7
SG		 582 pinctrl_usdhc2: usdhc2grp {
583 fsl,pins = <
584 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
585 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
586 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
587 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
588 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
589 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
590 >;
591 };
592
593 pinctrl_usdhc3: usdhc3grp {
594 fsl,pins = <
595 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
596 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
597 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
598 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
599 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
600 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
601 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
602 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
603 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
604 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
605 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
606 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
607 >;
608 };
609
610 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
611 fsl,pins = <
612 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
613 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
614 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
615 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
616 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
617 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
618 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
619 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
620 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
621 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
622 >;
623 };
624
625 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
626 fsl,pins = <
627 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
628 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
629 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
630 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
631 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
632 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
633 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
634 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
635 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
636 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
637 >;
638 };
639
640 pinctrl_usdhc4: usdhc4grp {
641 fsl,pins = <
642 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
643 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
644 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
645 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
646 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
647 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
648 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
649 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
650 >;
651 };
652 };
653};
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