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b1d17f68 SG |
1 | /* |
2 | * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <dt-bindings/clock/imx6sx-clock.h> | |
10 | #include <dt-bindings/gpio/gpio.h> | |
11 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
12 | #include "imx6sx-pinfunc.h" | |
13 | #include "skeleton.dtsi" | |
14 | ||
15 | / { | |
16 | aliases { | |
17 | can0 = &flexcan1; | |
18 | can1 = &flexcan2; | |
19 | ethernet0 = &fec1; | |
20 | ethernet1 = &fec2; | |
21 | gpio0 = &gpio1; | |
22 | gpio1 = &gpio2; | |
23 | gpio2 = &gpio3; | |
24 | gpio3 = &gpio4; | |
25 | gpio4 = &gpio5; | |
26 | gpio5 = &gpio6; | |
27 | gpio6 = &gpio7; | |
28 | i2c0 = &i2c1; | |
29 | i2c1 = &i2c2; | |
30 | i2c2 = &i2c3; | |
31 | i2c3 = &i2c4; | |
32 | mmc0 = &usdhc1; | |
33 | mmc1 = &usdhc2; | |
34 | mmc2 = &usdhc3; | |
35 | mmc3 = &usdhc4; | |
36 | serial0 = &uart1; | |
37 | serial1 = &uart2; | |
38 | serial2 = &uart3; | |
39 | serial3 = &uart4; | |
40 | serial4 = &uart5; | |
41 | serial5 = &uart6; | |
42 | spi0 = &ecspi1; | |
43 | spi1 = &ecspi2; | |
44 | spi2 = &ecspi3; | |
45 | spi3 = &ecspi4; | |
46 | spi4 = &ecspi5; | |
47 | usbphy0 = &usbphy1; | |
48 | usbphy1 = &usbphy2; | |
49 | }; | |
50 | ||
51 | cpus { | |
52 | #address-cells = <1>; | |
53 | #size-cells = <0>; | |
54 | ||
55 | cpu0: cpu@0 { | |
56 | compatible = "arm,cortex-a9"; | |
57 | device_type = "cpu"; | |
58 | reg = <0>; | |
59 | next-level-cache = <&L2>; | |
60 | operating-points = < | |
61 | /* kHz uV */ | |
62 | 996000 1250000 | |
63 | 792000 1175000 | |
64 | 396000 1075000 | |
65 | >; | |
66 | fsl,soc-operating-points = < | |
67 | /* ARM kHz SOC uV */ | |
68 | 996000 1175000 | |
69 | 792000 1175000 | |
70 | 396000 1175000 | |
71 | >; | |
72 | clock-latency = <61036>; /* two CLK32 periods */ | |
73 | clocks = <&clks IMX6SX_CLK_ARM>, | |
74 | <&clks IMX6SX_CLK_PLL2_PFD2>, | |
75 | <&clks IMX6SX_CLK_STEP>, | |
76 | <&clks IMX6SX_CLK_PLL1_SW>, | |
77 | <&clks IMX6SX_CLK_PLL1_SYS>; | |
78 | clock-names = "arm", "pll2_pfd2_396m", "step", | |
79 | "pll1_sw", "pll1_sys"; | |
80 | arm-supply = <®_arm>; | |
81 | soc-supply = <®_soc>; | |
82 | }; | |
83 | }; | |
84 | ||
85 | intc: interrupt-controller@00a01000 { | |
86 | compatible = "arm,cortex-a9-gic"; | |
87 | #interrupt-cells = <3>; | |
88 | interrupt-controller; | |
89 | reg = <0x00a01000 0x1000>, | |
90 | <0x00a00100 0x100>; | |
91 | }; | |
92 | ||
93 | clocks { | |
94 | #address-cells = <1>; | |
95 | #size-cells = <0>; | |
96 | ||
97 | ckil: clock@0 { | |
98 | compatible = "fixed-clock"; | |
99 | reg = <0>; | |
100 | #clock-cells = <0>; | |
101 | clock-frequency = <32768>; | |
102 | clock-output-names = "ckil"; | |
103 | }; | |
104 | ||
105 | osc: clock@1 { | |
106 | compatible = "fixed-clock"; | |
107 | reg = <1>; | |
108 | #clock-cells = <0>; | |
109 | clock-frequency = <24000000>; | |
110 | clock-output-names = "osc"; | |
111 | }; | |
112 | ||
113 | ipp_di0: clock@2 { | |
114 | compatible = "fixed-clock"; | |
115 | reg = <2>; | |
116 | #clock-cells = <0>; | |
117 | clock-frequency = <0>; | |
118 | clock-output-names = "ipp_di0"; | |
119 | }; | |
120 | ||
121 | ipp_di1: clock@3 { | |
122 | compatible = "fixed-clock"; | |
123 | reg = <3>; | |
124 | #clock-cells = <0>; | |
125 | clock-frequency = <0>; | |
126 | clock-output-names = "ipp_di1"; | |
127 | }; | |
128 | }; | |
129 | ||
130 | soc { | |
131 | #address-cells = <1>; | |
132 | #size-cells = <1>; | |
133 | compatible = "simple-bus"; | |
134 | interrupt-parent = <&intc>; | |
135 | ranges; | |
136 | ||
137 | pmu { | |
138 | compatible = "arm,cortex-a9-pmu"; | |
139 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; | |
140 | }; | |
141 | ||
142 | ocram: sram@00900000 { | |
143 | compatible = "mmio-sram"; | |
144 | reg = <0x00900000 0x20000>; | |
145 | clocks = <&clks IMX6SX_CLK_OCRAM>; | |
146 | }; | |
147 | ||
148 | L2: l2-cache@00a02000 { | |
149 | compatible = "arm,pl310-cache"; | |
150 | reg = <0x00a02000 0x1000>; | |
151 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; | |
152 | cache-unified; | |
153 | cache-level = <2>; | |
154 | arm,tag-latency = <4 2 3>; | |
155 | arm,data-latency = <4 2 3>; | |
156 | }; | |
157 | ||
158 | dma_apbh: dma-apbh@01804000 { | |
159 | compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; | |
160 | reg = <0x01804000 0x2000>; | |
161 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
162 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
163 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
164 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
165 | interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; | |
166 | #dma-cells = <1>; | |
167 | dma-channels = <4>; | |
168 | clocks = <&clks IMX6SX_CLK_APBH_DMA>; | |
169 | }; | |
170 | ||
171 | gpmi: gpmi-nand@01806000{ | |
172 | compatible = "fsl,imx6sx-gpmi-nand"; | |
173 | #address-cells = <1>; | |
174 | #size-cells = <1>; | |
175 | reg = <0x01806000 0x2000>, <0x01808000 0x4000>; | |
176 | reg-names = "gpmi-nand", "bch"; | |
177 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
178 | interrupt-names = "bch"; | |
179 | clocks = <&clks IMX6SX_CLK_GPMI_IO>, | |
180 | <&clks IMX6SX_CLK_GPMI_APB>, | |
181 | <&clks IMX6SX_CLK_GPMI_BCH>, | |
182 | <&clks IMX6SX_CLK_GPMI_BCH_APB>, | |
183 | <&clks IMX6SX_CLK_PER1_BCH>; | |
184 | clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", | |
185 | "gpmi_bch_apb", "per1_bch"; | |
186 | dmas = <&dma_apbh 0>; | |
187 | dma-names = "rx-tx"; | |
188 | status = "disabled"; | |
189 | }; | |
190 | ||
191 | aips1: aips-bus@02000000 { | |
192 | compatible = "fsl,aips-bus", "simple-bus"; | |
193 | #address-cells = <1>; | |
194 | #size-cells = <1>; | |
195 | reg = <0x02000000 0x100000>; | |
196 | ranges; | |
197 | ||
198 | spba-bus@02000000 { | |
199 | compatible = "fsl,spba-bus", "simple-bus"; | |
200 | #address-cells = <1>; | |
201 | #size-cells = <1>; | |
202 | reg = <0x02000000 0x40000>; | |
203 | ranges; | |
204 | ||
205 | spdif: spdif@02004000 { | |
206 | compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; | |
207 | reg = <0x02004000 0x4000>; | |
208 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
209 | dmas = <&sdma 14 18 0>, | |
210 | <&sdma 15 18 0>; | |
211 | dma-names = "rx", "tx"; | |
212 | clocks = <&clks IMX6SX_CLK_SPDIF>, | |
213 | <&clks IMX6SX_CLK_OSC>, | |
214 | <&clks IMX6SX_CLK_SPDIF>, | |
215 | <&clks 0>, <&clks 0>, <&clks 0>, | |
216 | <&clks IMX6SX_CLK_IPG>, | |
217 | <&clks 0>, <&clks 0>, | |
218 | <&clks IMX6SX_CLK_SPBA>; | |
219 | clock-names = "core", "rxtx0", | |
220 | "rxtx1", "rxtx2", | |
221 | "rxtx3", "rxtx4", | |
222 | "rxtx5", "rxtx6", | |
223 | "rxtx7", "dma"; | |
224 | status = "disabled"; | |
225 | }; | |
226 | ||
227 | ecspi1: ecspi@02008000 { | |
228 | #address-cells = <1>; | |
229 | #size-cells = <0>; | |
230 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; | |
231 | reg = <0x02008000 0x4000>; | |
232 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; | |
233 | clocks = <&clks IMX6SX_CLK_ECSPI1>, | |
234 | <&clks IMX6SX_CLK_ECSPI1>; | |
235 | clock-names = "ipg", "per"; | |
236 | status = "disabled"; | |
237 | }; | |
238 | ||
239 | ecspi2: ecspi@0200c000 { | |
240 | #address-cells = <1>; | |
241 | #size-cells = <0>; | |
242 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; | |
243 | reg = <0x0200c000 0x4000>; | |
244 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
245 | clocks = <&clks IMX6SX_CLK_ECSPI2>, | |
246 | <&clks IMX6SX_CLK_ECSPI2>; | |
247 | clock-names = "ipg", "per"; | |
248 | status = "disabled"; | |
249 | }; | |
250 | ||
251 | ecspi3: ecspi@02010000 { | |
252 | #address-cells = <1>; | |
253 | #size-cells = <0>; | |
254 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; | |
255 | reg = <0x02010000 0x4000>; | |
256 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
257 | clocks = <&clks IMX6SX_CLK_ECSPI3>, | |
258 | <&clks IMX6SX_CLK_ECSPI3>; | |
259 | clock-names = "ipg", "per"; | |
260 | status = "disabled"; | |
261 | }; | |
262 | ||
263 | ecspi4: ecspi@02014000 { | |
264 | #address-cells = <1>; | |
265 | #size-cells = <0>; | |
266 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; | |
267 | reg = <0x02014000 0x4000>; | |
268 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
269 | clocks = <&clks IMX6SX_CLK_ECSPI4>, | |
270 | <&clks IMX6SX_CLK_ECSPI4>; | |
271 | clock-names = "ipg", "per"; | |
272 | status = "disabled"; | |
273 | }; | |
274 | ||
275 | uart1: serial@02020000 { | |
276 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; | |
277 | reg = <0x02020000 0x4000>; | |
278 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
279 | clocks = <&clks IMX6SX_CLK_UART_IPG>, | |
280 | <&clks IMX6SX_CLK_UART_SERIAL>; | |
281 | clock-names = "ipg", "per"; | |
282 | dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; | |
283 | dma-names = "rx", "tx"; | |
284 | status = "disabled"; | |
285 | }; | |
286 | ||
287 | esai: esai@02024000 { | |
288 | reg = <0x02024000 0x4000>; | |
289 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; | |
290 | clocks = <&clks IMX6SX_CLK_ESAI_IPG>, | |
291 | <&clks IMX6SX_CLK_ESAI_MEM>, | |
292 | <&clks IMX6SX_CLK_ESAI_EXTAL>, | |
293 | <&clks IMX6SX_CLK_ESAI_IPG>, | |
294 | <&clks IMX6SX_CLK_SPBA>; | |
295 | clock-names = "core", "mem", "extal", | |
296 | "fsys", "dma"; | |
297 | status = "disabled"; | |
298 | }; | |
299 | ||
300 | ssi1: ssi@02028000 { | |
6ff7f51e | 301 | #sound-dai-cells = <0>; |
4c03527e | 302 | compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; |
b1d17f68 SG |
303 | reg = <0x02028000 0x4000>; |
304 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
305 | clocks = <&clks IMX6SX_CLK_SSI1_IPG>, | |
306 | <&clks IMX6SX_CLK_SSI1>; | |
307 | clock-names = "ipg", "baud"; | |
308 | dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; | |
309 | dma-names = "rx", "tx"; | |
3a462a62 | 310 | fsl,fifo-depth = <15>; |
b1d17f68 SG |
311 | status = "disabled"; |
312 | }; | |
313 | ||
314 | ssi2: ssi@0202c000 { | |
6ff7f51e | 315 | #sound-dai-cells = <0>; |
4c03527e | 316 | compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; |
b1d17f68 SG |
317 | reg = <0x0202c000 0x4000>; |
318 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; | |
319 | clocks = <&clks IMX6SX_CLK_SSI2_IPG>, | |
320 | <&clks IMX6SX_CLK_SSI2>; | |
321 | clock-names = "ipg", "baud"; | |
322 | dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; | |
323 | dma-names = "rx", "tx"; | |
3a462a62 | 324 | fsl,fifo-depth = <15>; |
b1d17f68 SG |
325 | status = "disabled"; |
326 | }; | |
327 | ||
328 | ssi3: ssi@02030000 { | |
6ff7f51e | 329 | #sound-dai-cells = <0>; |
4c03527e | 330 | compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; |
b1d17f68 SG |
331 | reg = <0x02030000 0x4000>; |
332 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; | |
333 | clocks = <&clks IMX6SX_CLK_SSI3_IPG>, | |
334 | <&clks IMX6SX_CLK_SSI3>; | |
335 | clock-names = "ipg", "baud"; | |
336 | dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; | |
337 | dma-names = "rx", "tx"; | |
3a462a62 | 338 | fsl,fifo-depth = <15>; |
b1d17f68 SG |
339 | status = "disabled"; |
340 | }; | |
341 | ||
342 | asrc: asrc@02034000 { | |
343 | reg = <0x02034000 0x4000>; | |
344 | interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; | |
345 | clocks = <&clks IMX6SX_CLK_ASRC_MEM>, | |
346 | <&clks IMX6SX_CLK_ASRC_IPG>, | |
347 | <&clks IMX6SX_CLK_SPDIF>, | |
348 | <&clks IMX6SX_CLK_SPBA>; | |
349 | clock-names = "mem", "ipg", "asrck", "dma"; | |
350 | dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, | |
351 | <&sdma 19 20 1>, <&sdma 20 20 1>, | |
352 | <&sdma 21 20 1>, <&sdma 22 20 1>; | |
353 | dma-names = "rxa", "rxb", "rxc", | |
354 | "txa", "txb", "txc"; | |
355 | status = "okay"; | |
356 | }; | |
357 | }; | |
358 | ||
359 | pwm1: pwm@02080000 { | |
360 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; | |
361 | reg = <0x02080000 0x4000>; | |
362 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
363 | clocks = <&clks IMX6SX_CLK_PWM1>, | |
364 | <&clks IMX6SX_CLK_PWM1>; | |
365 | clock-names = "ipg", "per"; | |
366 | #pwm-cells = <2>; | |
367 | }; | |
368 | ||
369 | pwm2: pwm@02084000 { | |
370 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; | |
371 | reg = <0x02084000 0x4000>; | |
372 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
373 | clocks = <&clks IMX6SX_CLK_PWM2>, | |
374 | <&clks IMX6SX_CLK_PWM2>; | |
375 | clock-names = "ipg", "per"; | |
376 | #pwm-cells = <2>; | |
377 | }; | |
378 | ||
379 | pwm3: pwm@02088000 { | |
380 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; | |
381 | reg = <0x02088000 0x4000>; | |
382 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
383 | clocks = <&clks IMX6SX_CLK_PWM3>, | |
384 | <&clks IMX6SX_CLK_PWM3>; | |
385 | clock-names = "ipg", "per"; | |
386 | #pwm-cells = <2>; | |
387 | }; | |
388 | ||
389 | pwm4: pwm@0208c000 { | |
390 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; | |
391 | reg = <0x0208c000 0x4000>; | |
392 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
393 | clocks = <&clks IMX6SX_CLK_PWM4>, | |
394 | <&clks IMX6SX_CLK_PWM4>; | |
395 | clock-names = "ipg", "per"; | |
396 | #pwm-cells = <2>; | |
397 | }; | |
398 | ||
399 | flexcan1: can@02090000 { | |
400 | compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; | |
401 | reg = <0x02090000 0x4000>; | |
402 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; | |
403 | clocks = <&clks IMX6SX_CLK_CAN1_IPG>, | |
404 | <&clks IMX6SX_CLK_CAN1_SERIAL>; | |
405 | clock-names = "ipg", "per"; | |
406 | status = "disabled"; | |
407 | }; | |
408 | ||
409 | flexcan2: can@02094000 { | |
410 | compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; | |
411 | reg = <0x02094000 0x4000>; | |
412 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; | |
413 | clocks = <&clks IMX6SX_CLK_CAN2_IPG>, | |
414 | <&clks IMX6SX_CLK_CAN2_SERIAL>; | |
415 | clock-names = "ipg", "per"; | |
416 | status = "disabled"; | |
417 | }; | |
418 | ||
419 | gpt: gpt@02098000 { | |
420 | compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt"; | |
421 | reg = <0x02098000 0x4000>; | |
422 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
423 | clocks = <&clks IMX6SX_CLK_GPT_BUS>, | |
2b2244a3 | 424 | <&clks IMX6SX_CLK_GPT_3M>; |
b1d17f68 SG |
425 | clock-names = "ipg", "per"; |
426 | }; | |
427 | ||
428 | gpio1: gpio@0209c000 { | |
429 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; | |
430 | reg = <0x0209c000 0x4000>; | |
431 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, | |
432 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
433 | gpio-controller; | |
434 | #gpio-cells = <2>; | |
435 | interrupt-controller; | |
436 | #interrupt-cells = <2>; | |
437 | }; | |
438 | ||
439 | gpio2: gpio@020a0000 { | |
440 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; | |
441 | reg = <0x020a0000 0x4000>; | |
442 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
443 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
444 | gpio-controller; | |
445 | #gpio-cells = <2>; | |
446 | interrupt-controller; | |
447 | #interrupt-cells = <2>; | |
448 | }; | |
449 | ||
450 | gpio3: gpio@020a4000 { | |
451 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; | |
452 | reg = <0x020a4000 0x4000>; | |
453 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, | |
454 | <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
455 | gpio-controller; | |
456 | #gpio-cells = <2>; | |
457 | interrupt-controller; | |
458 | #interrupt-cells = <2>; | |
459 | }; | |
460 | ||
461 | gpio4: gpio@020a8000 { | |
462 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; | |
463 | reg = <0x020a8000 0x4000>; | |
464 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, | |
465 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
466 | gpio-controller; | |
467 | #gpio-cells = <2>; | |
468 | interrupt-controller; | |
469 | #interrupt-cells = <2>; | |
470 | }; | |
471 | ||
472 | gpio5: gpio@020ac000 { | |
473 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; | |
474 | reg = <0x020ac000 0x4000>; | |
475 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, | |
476 | <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
477 | gpio-controller; | |
478 | #gpio-cells = <2>; | |
479 | interrupt-controller; | |
480 | #interrupt-cells = <2>; | |
481 | }; | |
482 | ||
483 | gpio6: gpio@020b0000 { | |
484 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; | |
485 | reg = <0x020b0000 0x4000>; | |
486 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, | |
487 | <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
488 | gpio-controller; | |
489 | #gpio-cells = <2>; | |
490 | interrupt-controller; | |
491 | #interrupt-cells = <2>; | |
492 | }; | |
493 | ||
494 | gpio7: gpio@020b4000 { | |
495 | compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; | |
496 | reg = <0x020b4000 0x4000>; | |
497 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, | |
498 | <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; | |
499 | gpio-controller; | |
500 | #gpio-cells = <2>; | |
501 | interrupt-controller; | |
502 | #interrupt-cells = <2>; | |
503 | }; | |
504 | ||
505 | kpp: kpp@020b8000 { | |
506 | compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; | |
507 | reg = <0x020b8000 0x4000>; | |
508 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | |
509 | clocks = <&clks IMX6SX_CLK_DUMMY>; | |
510 | status = "disabled"; | |
511 | }; | |
512 | ||
513 | wdog1: wdog@020bc000 { | |
514 | compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; | |
515 | reg = <0x020bc000 0x4000>; | |
516 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
517 | clocks = <&clks IMX6SX_CLK_DUMMY>; | |
518 | }; | |
519 | ||
520 | wdog2: wdog@020c0000 { | |
521 | compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; | |
522 | reg = <0x020c0000 0x4000>; | |
523 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
524 | clocks = <&clks IMX6SX_CLK_DUMMY>; | |
525 | status = "disabled"; | |
526 | }; | |
527 | ||
528 | clks: ccm@020c4000 { | |
529 | compatible = "fsl,imx6sx-ccm"; | |
530 | reg = <0x020c4000 0x4000>; | |
531 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
532 | <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
533 | #clock-cells = <1>; | |
534 | clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; | |
535 | clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; | |
536 | }; | |
537 | ||
538 | anatop: anatop@020c8000 { | |
539 | compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", | |
540 | "syscon", "simple-bus"; | |
541 | reg = <0x020c8000 0x1000>; | |
542 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
543 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
544 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; | |
545 | ||
546 | regulator-1p1@110 { | |
547 | compatible = "fsl,anatop-regulator"; | |
548 | regulator-name = "vdd1p1"; | |
549 | regulator-min-microvolt = <800000>; | |
550 | regulator-max-microvolt = <1375000>; | |
551 | regulator-always-on; | |
552 | anatop-reg-offset = <0x110>; | |
553 | anatop-vol-bit-shift = <8>; | |
554 | anatop-vol-bit-width = <5>; | |
555 | anatop-min-bit-val = <4>; | |
556 | anatop-min-voltage = <800000>; | |
557 | anatop-max-voltage = <1375000>; | |
558 | }; | |
559 | ||
560 | regulator-3p0@120 { | |
561 | compatible = "fsl,anatop-regulator"; | |
562 | regulator-name = "vdd3p0"; | |
563 | regulator-min-microvolt = <2800000>; | |
564 | regulator-max-microvolt = <3150000>; | |
565 | regulator-always-on; | |
566 | anatop-reg-offset = <0x120>; | |
567 | anatop-vol-bit-shift = <8>; | |
568 | anatop-vol-bit-width = <5>; | |
569 | anatop-min-bit-val = <0>; | |
570 | anatop-min-voltage = <2625000>; | |
571 | anatop-max-voltage = <3400000>; | |
572 | }; | |
573 | ||
574 | regulator-2p5@130 { | |
575 | compatible = "fsl,anatop-regulator"; | |
576 | regulator-name = "vdd2p5"; | |
577 | regulator-min-microvolt = <2100000>; | |
578 | regulator-max-microvolt = <2875000>; | |
579 | regulator-always-on; | |
580 | anatop-reg-offset = <0x130>; | |
581 | anatop-vol-bit-shift = <8>; | |
582 | anatop-vol-bit-width = <5>; | |
583 | anatop-min-bit-val = <0>; | |
584 | anatop-min-voltage = <2100000>; | |
585 | anatop-max-voltage = <2875000>; | |
586 | }; | |
587 | ||
588 | reg_arm: regulator-vddcore@140 { | |
589 | compatible = "fsl,anatop-regulator"; | |
f78a5975 | 590 | regulator-name = "vddarm"; |
b1d17f68 SG |
591 | regulator-min-microvolt = <725000>; |
592 | regulator-max-microvolt = <1450000>; | |
593 | regulator-always-on; | |
594 | anatop-reg-offset = <0x140>; | |
595 | anatop-vol-bit-shift = <0>; | |
596 | anatop-vol-bit-width = <5>; | |
597 | anatop-delay-reg-offset = <0x170>; | |
598 | anatop-delay-bit-shift = <24>; | |
599 | anatop-delay-bit-width = <2>; | |
600 | anatop-min-bit-val = <1>; | |
601 | anatop-min-voltage = <725000>; | |
602 | anatop-max-voltage = <1450000>; | |
603 | }; | |
604 | ||
605 | reg_pcie: regulator-vddpcie@140 { | |
606 | compatible = "fsl,anatop-regulator"; | |
607 | regulator-name = "vddpcie"; | |
608 | regulator-min-microvolt = <725000>; | |
609 | regulator-max-microvolt = <1450000>; | |
610 | anatop-reg-offset = <0x140>; | |
611 | anatop-vol-bit-shift = <9>; | |
612 | anatop-vol-bit-width = <5>; | |
613 | anatop-delay-reg-offset = <0x170>; | |
614 | anatop-delay-bit-shift = <26>; | |
615 | anatop-delay-bit-width = <2>; | |
616 | anatop-min-bit-val = <1>; | |
617 | anatop-min-voltage = <725000>; | |
618 | anatop-max-voltage = <1450000>; | |
619 | }; | |
620 | ||
621 | reg_soc: regulator-vddsoc@140 { | |
622 | compatible = "fsl,anatop-regulator"; | |
623 | regulator-name = "vddsoc"; | |
624 | regulator-min-microvolt = <725000>; | |
625 | regulator-max-microvolt = <1450000>; | |
626 | regulator-always-on; | |
627 | anatop-reg-offset = <0x140>; | |
628 | anatop-vol-bit-shift = <18>; | |
629 | anatop-vol-bit-width = <5>; | |
630 | anatop-delay-reg-offset = <0x170>; | |
631 | anatop-delay-bit-shift = <28>; | |
632 | anatop-delay-bit-width = <2>; | |
633 | anatop-min-bit-val = <1>; | |
634 | anatop-min-voltage = <725000>; | |
635 | anatop-max-voltage = <1450000>; | |
636 | }; | |
637 | }; | |
638 | ||
639 | tempmon: tempmon { | |
640 | compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; | |
641 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; | |
642 | fsl,tempmon = <&anatop>; | |
643 | fsl,tempmon-data = <&ocotp>; | |
644 | clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; | |
645 | }; | |
646 | ||
647 | usbphy1: usbphy@020c9000 { | |
648 | compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; | |
649 | reg = <0x020c9000 0x1000>; | |
650 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; | |
651 | clocks = <&clks IMX6SX_CLK_USBPHY1>; | |
652 | fsl,anatop = <&anatop>; | |
653 | }; | |
654 | ||
655 | usbphy2: usbphy@020ca000 { | |
656 | compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; | |
657 | reg = <0x020ca000 0x1000>; | |
658 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
659 | clocks = <&clks IMX6SX_CLK_USBPHY2>; | |
660 | fsl,anatop = <&anatop>; | |
661 | }; | |
662 | ||
663 | snvs: snvs@020cc000 { | |
664 | compatible = "fsl,sec-v4.0-mon", "simple-bus"; | |
665 | #address-cells = <1>; | |
666 | #size-cells = <1>; | |
667 | ranges = <0 0x020cc000 0x4000>; | |
668 | ||
669 | snvs-rtc-lp@34 { | |
670 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; | |
671 | reg = <0x34 0x58>; | |
672 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
673 | }; | |
674 | }; | |
675 | ||
676 | epit1: epit@020d0000 { | |
677 | reg = <0x020d0000 0x4000>; | |
678 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
679 | }; | |
680 | ||
681 | epit2: epit@020d4000 { | |
682 | reg = <0x020d4000 0x4000>; | |
683 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
684 | }; | |
685 | ||
686 | src: src@020d8000 { | |
687 | compatible = "fsl,imx6sx-src", "fsl,imx51-src"; | |
688 | reg = <0x020d8000 0x4000>; | |
689 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, | |
690 | <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
691 | #reset-cells = <1>; | |
692 | }; | |
693 | ||
694 | gpc: gpc@020dc000 { | |
695 | compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; | |
696 | reg = <0x020dc000 0x4000>; | |
697 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
698 | }; | |
699 | ||
700 | iomuxc: iomuxc@020e0000 { | |
701 | compatible = "fsl,imx6sx-iomuxc"; | |
702 | reg = <0x020e0000 0x4000>; | |
703 | }; | |
704 | ||
705 | gpr: iomuxc-gpr@020e4000 { | |
77e0d1cc AH |
706 | compatible = "fsl,imx6sx-iomuxc-gpr", |
707 | "fsl,imx6q-iomuxc-gpr", "syscon"; | |
b1d17f68 SG |
708 | reg = <0x020e4000 0x4000>; |
709 | }; | |
710 | ||
711 | sdma: sdma@020ec000 { | |
811e7685 | 712 | compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; |
b1d17f68 SG |
713 | reg = <0x020ec000 0x4000>; |
714 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; | |
715 | clocks = <&clks IMX6SX_CLK_SDMA>, | |
716 | <&clks IMX6SX_CLK_SDMA>; | |
717 | clock-names = "ipg", "ahb"; | |
718 | #dma-cells = <3>; | |
aeb88538 FE |
719 | /* imx6sx reuses imx6q sdma firmware */ |
720 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; | |
b1d17f68 SG |
721 | }; |
722 | }; | |
723 | ||
724 | aips2: aips-bus@02100000 { | |
725 | compatible = "fsl,aips-bus", "simple-bus"; | |
726 | #address-cells = <1>; | |
727 | #size-cells = <1>; | |
728 | reg = <0x02100000 0x100000>; | |
729 | ranges; | |
730 | ||
731 | usbotg1: usb@02184000 { | |
732 | compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; | |
733 | reg = <0x02184000 0x200>; | |
734 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
735 | clocks = <&clks IMX6SX_CLK_USBOH3>; | |
736 | fsl,usbphy = <&usbphy1>; | |
737 | fsl,usbmisc = <&usbmisc 0>; | |
738 | fsl,anatop = <&anatop>; | |
739 | status = "disabled"; | |
740 | }; | |
741 | ||
742 | usbotg2: usb@02184200 { | |
743 | compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; | |
744 | reg = <0x02184200 0x200>; | |
745 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
746 | clocks = <&clks IMX6SX_CLK_USBOH3>; | |
747 | fsl,usbphy = <&usbphy2>; | |
748 | fsl,usbmisc = <&usbmisc 1>; | |
749 | status = "disabled"; | |
750 | }; | |
751 | ||
752 | usbh: usb@02184400 { | |
753 | compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; | |
754 | reg = <0x02184400 0x200>; | |
755 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
756 | clocks = <&clks IMX6SX_CLK_USBOH3>; | |
757 | fsl,usbmisc = <&usbmisc 2>; | |
758 | phy_type = "hsic"; | |
759 | fsl,anatop = <&anatop>; | |
760 | status = "disabled"; | |
761 | }; | |
762 | ||
763 | usbmisc: usbmisc@02184800 { | |
764 | #index-cells = <1>; | |
b29f4fa1 | 765 | compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; |
b1d17f68 SG |
766 | reg = <0x02184800 0x200>; |
767 | clocks = <&clks IMX6SX_CLK_USBOH3>; | |
768 | }; | |
769 | ||
770 | fec1: ethernet@02188000 { | |
771 | compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; | |
772 | reg = <0x02188000 0x4000>; | |
773 | interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
774 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; | |
775 | clocks = <&clks IMX6SX_CLK_ENET>, | |
776 | <&clks IMX6SX_CLK_ENET_AHB>, | |
777 | <&clks IMX6SX_CLK_ENET_PTP>, | |
778 | <&clks IMX6SX_CLK_ENET_REF>, | |
779 | <&clks IMX6SX_CLK_ENET_PTP>; | |
780 | clock-names = "ipg", "ahb", "ptp", | |
781 | "enet_clk_ref", "enet_out"; | |
0afdfe95 FL |
782 | fsl,num-tx-queues=<3>; |
783 | fsl,num-rx-queues=<3>; | |
b1d17f68 SG |
784 | status = "disabled"; |
785 | }; | |
786 | ||
787 | mlb: mlb@0218c000 { | |
788 | reg = <0x0218c000 0x4000>; | |
789 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
790 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
791 | <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; | |
792 | clocks = <&clks IMX6SX_CLK_MLB>; | |
793 | status = "disabled"; | |
794 | }; | |
795 | ||
796 | usdhc1: usdhc@02190000 { | |
797 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; | |
798 | reg = <0x02190000 0x4000>; | |
799 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
800 | clocks = <&clks IMX6SX_CLK_USDHC1>, | |
801 | <&clks IMX6SX_CLK_USDHC1>, | |
802 | <&clks IMX6SX_CLK_USDHC1>; | |
803 | clock-names = "ipg", "ahb", "per"; | |
804 | bus-width = <4>; | |
805 | status = "disabled"; | |
806 | }; | |
807 | ||
808 | usdhc2: usdhc@02194000 { | |
809 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; | |
810 | reg = <0x02194000 0x4000>; | |
811 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
812 | clocks = <&clks IMX6SX_CLK_USDHC2>, | |
813 | <&clks IMX6SX_CLK_USDHC2>, | |
814 | <&clks IMX6SX_CLK_USDHC2>; | |
815 | clock-names = "ipg", "ahb", "per"; | |
816 | bus-width = <4>; | |
817 | status = "disabled"; | |
818 | }; | |
819 | ||
820 | usdhc3: usdhc@02198000 { | |
821 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; | |
822 | reg = <0x02198000 0x4000>; | |
823 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
824 | clocks = <&clks IMX6SX_CLK_USDHC3>, | |
825 | <&clks IMX6SX_CLK_USDHC3>, | |
826 | <&clks IMX6SX_CLK_USDHC3>; | |
827 | clock-names = "ipg", "ahb", "per"; | |
828 | bus-width = <4>; | |
829 | status = "disabled"; | |
830 | }; | |
831 | ||
832 | usdhc4: usdhc@0219c000 { | |
833 | compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; | |
834 | reg = <0x0219c000 0x4000>; | |
835 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
836 | clocks = <&clks IMX6SX_CLK_USDHC4>, | |
837 | <&clks IMX6SX_CLK_USDHC4>, | |
838 | <&clks IMX6SX_CLK_USDHC4>; | |
839 | clock-names = "ipg", "ahb", "per"; | |
840 | bus-width = <4>; | |
841 | status = "disabled"; | |
842 | }; | |
843 | ||
844 | i2c1: i2c@021a0000 { | |
845 | #address-cells = <1>; | |
846 | #size-cells = <0>; | |
847 | compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; | |
848 | reg = <0x021a0000 0x4000>; | |
849 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
850 | clocks = <&clks IMX6SX_CLK_I2C1>; | |
851 | status = "disabled"; | |
852 | }; | |
853 | ||
854 | i2c2: i2c@021a4000 { | |
855 | #address-cells = <1>; | |
856 | #size-cells = <0>; | |
857 | compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; | |
858 | reg = <0x021a4000 0x4000>; | |
859 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
860 | clocks = <&clks IMX6SX_CLK_I2C2>; | |
861 | status = "disabled"; | |
862 | }; | |
863 | ||
864 | i2c3: i2c@021a8000 { | |
865 | #address-cells = <1>; | |
866 | #size-cells = <0>; | |
867 | compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; | |
868 | reg = <0x021a8000 0x4000>; | |
869 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
870 | clocks = <&clks IMX6SX_CLK_I2C3>; | |
871 | status = "disabled"; | |
872 | }; | |
873 | ||
874 | mmdc: mmdc@021b0000 { | |
875 | compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; | |
876 | reg = <0x021b0000 0x4000>; | |
877 | }; | |
878 | ||
879 | fec2: ethernet@021b4000 { | |
880 | compatible = "fsl,imx6sx-fec"; | |
881 | reg = <0x021b4000 0x4000>; | |
882 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, | |
883 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
884 | clocks = <&clks IMX6SX_CLK_ENET>, | |
885 | <&clks IMX6SX_CLK_ENET_AHB>, | |
886 | <&clks IMX6SX_CLK_ENET_PTP>, | |
887 | <&clks IMX6SX_CLK_ENET2_REF_125M>, | |
888 | <&clks IMX6SX_CLK_ENET_PTP>; | |
889 | clock-names = "ipg", "ahb", "ptp", | |
890 | "enet_clk_ref", "enet_out"; | |
891 | status = "disabled"; | |
892 | }; | |
893 | ||
894 | weim: weim@021b8000 { | |
895 | compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; | |
896 | reg = <0x021b8000 0x4000>; | |
897 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
898 | clocks = <&clks IMX6SX_CLK_EIM_SLOW>; | |
899 | }; | |
900 | ||
901 | ocotp: ocotp@021bc000 { | |
902 | compatible = "fsl,imx6sx-ocotp", "syscon"; | |
903 | reg = <0x021bc000 0x4000>; | |
904 | clocks = <&clks IMX6SX_CLK_OCOTP>; | |
905 | }; | |
906 | ||
907 | sai1: sai@021d4000 { | |
908 | compatible = "fsl,imx6sx-sai"; | |
909 | reg = <0x021d4000 0x4000>; | |
910 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
911 | clocks = <&clks IMX6SX_CLK_SAI1_IPG>, | |
912 | <&clks IMX6SX_CLK_SAI1>, | |
913 | <&clks 0>, <&clks 0>; | |
914 | clock-names = "bus", "mclk1", "mclk2", "mclk3"; | |
915 | dma-names = "rx", "tx"; | |
916 | dmas = <&sdma 31 23 0>, <&sdma 32 23 0>; | |
917 | dma-source = <&gpr 0 15 0 16>; | |
918 | status = "disabled"; | |
919 | }; | |
920 | ||
921 | audmux: audmux@021d8000 { | |
922 | compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; | |
923 | reg = <0x021d8000 0x4000>; | |
924 | status = "disabled"; | |
925 | }; | |
926 | ||
927 | sai2: sai@021dc000 { | |
928 | compatible = "fsl,imx6sx-sai"; | |
929 | reg = <0x021dc000 0x4000>; | |
930 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
931 | clocks = <&clks IMX6SX_CLK_SAI2_IPG>, | |
932 | <&clks IMX6SX_CLK_SAI2>, | |
933 | <&clks 0>, <&clks 0>; | |
934 | clock-names = "bus", "mclk1", "mclk2", "mclk3"; | |
935 | dma-names = "rx", "tx"; | |
936 | dmas = <&sdma 33 23 0>, <&sdma 34 23 0>; | |
937 | dma-source = <&gpr 0 17 0 18>; | |
938 | status = "disabled"; | |
939 | }; | |
940 | ||
941 | qspi1: qspi@021e0000 { | |
942 | #address-cells = <1>; | |
943 | #size-cells = <0>; | |
944 | compatible = "fsl,imx6sx-qspi"; | |
945 | reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; | |
946 | reg-names = "QuadSPI", "QuadSPI-memory"; | |
947 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; | |
948 | clocks = <&clks IMX6SX_CLK_QSPI1>, | |
949 | <&clks IMX6SX_CLK_QSPI1>; | |
950 | clock-names = "qspi_en", "qspi"; | |
951 | status = "disabled"; | |
952 | }; | |
953 | ||
954 | qspi2: qspi@021e4000 { | |
955 | #address-cells = <1>; | |
956 | #size-cells = <0>; | |
957 | compatible = "fsl,imx6sx-qspi"; | |
958 | reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>; | |
959 | reg-names = "QuadSPI", "QuadSPI-memory"; | |
960 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; | |
961 | clocks = <&clks IMX6SX_CLK_QSPI2>, | |
962 | <&clks IMX6SX_CLK_QSPI2>; | |
963 | clock-names = "qspi_en", "qspi"; | |
964 | status = "disabled"; | |
965 | }; | |
966 | ||
967 | uart2: serial@021e8000 { | |
968 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; | |
969 | reg = <0x021e8000 0x4000>; | |
970 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
971 | clocks = <&clks IMX6SX_CLK_UART_IPG>, | |
972 | <&clks IMX6SX_CLK_UART_SERIAL>; | |
973 | clock-names = "ipg", "per"; | |
974 | dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; | |
975 | dma-names = "rx", "tx"; | |
976 | status = "disabled"; | |
977 | }; | |
978 | ||
979 | uart3: serial@021ec000 { | |
980 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; | |
981 | reg = <0x021ec000 0x4000>; | |
982 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
983 | clocks = <&clks IMX6SX_CLK_UART_IPG>, | |
984 | <&clks IMX6SX_CLK_UART_SERIAL>; | |
985 | clock-names = "ipg", "per"; | |
986 | dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; | |
987 | dma-names = "rx", "tx"; | |
988 | status = "disabled"; | |
989 | }; | |
990 | ||
991 | uart4: serial@021f0000 { | |
992 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; | |
993 | reg = <0x021f0000 0x4000>; | |
994 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
995 | clocks = <&clks IMX6SX_CLK_UART_IPG>, | |
996 | <&clks IMX6SX_CLK_UART_SERIAL>; | |
997 | clock-names = "ipg", "per"; | |
998 | dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; | |
999 | dma-names = "rx", "tx"; | |
1000 | status = "disabled"; | |
1001 | }; | |
1002 | ||
1003 | uart5: serial@021f4000 { | |
1004 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; | |
1005 | reg = <0x021f4000 0x4000>; | |
1006 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
1007 | clocks = <&clks IMX6SX_CLK_UART_IPG>, | |
1008 | <&clks IMX6SX_CLK_UART_SERIAL>; | |
1009 | clock-names = "ipg", "per"; | |
1010 | dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; | |
1011 | dma-names = "rx", "tx"; | |
1012 | status = "disabled"; | |
1013 | }; | |
1014 | ||
1015 | i2c4: i2c@021f8000 { | |
1016 | #address-cells = <1>; | |
1017 | #size-cells = <0>; | |
1018 | compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; | |
1019 | reg = <0x021f8000 0x4000>; | |
1020 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
1021 | clocks = <&clks IMX6SX_CLK_I2C4>; | |
1022 | status = "disabled"; | |
1023 | }; | |
1024 | }; | |
1025 | ||
1026 | aips3: aips-bus@02200000 { | |
1027 | compatible = "fsl,aips-bus", "simple-bus"; | |
1028 | #address-cells = <1>; | |
1029 | #size-cells = <1>; | |
1030 | reg = <0x02200000 0x100000>; | |
1031 | ranges; | |
1032 | ||
1033 | spba-bus@02200000 { | |
1034 | compatible = "fsl,spba-bus", "simple-bus"; | |
1035 | #address-cells = <1>; | |
1036 | #size-cells = <1>; | |
1037 | reg = <0x02240000 0x40000>; | |
1038 | ranges; | |
1039 | ||
1040 | csi1: csi@02214000 { | |
1041 | reg = <0x02214000 0x4000>; | |
1042 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
1043 | clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, | |
1044 | <&clks IMX6SX_CLK_CSI>, | |
1045 | <&clks IMX6SX_CLK_DCIC1>; | |
1046 | clock-names = "disp-axi", "csi_mclk", "dcic"; | |
1047 | status = "disabled"; | |
1048 | }; | |
1049 | ||
1050 | pxp: pxp@02218000 { | |
1051 | reg = <0x02218000 0x4000>; | |
1052 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
1053 | clocks = <&clks IMX6SX_CLK_PXP_AXI>, | |
1054 | <&clks IMX6SX_CLK_DISPLAY_AXI>; | |
1055 | clock-names = "pxp-axi", "disp-axi"; | |
1056 | status = "disabled"; | |
1057 | }; | |
1058 | ||
1059 | csi2: csi@0221c000 { | |
1060 | reg = <0x0221c000 0x4000>; | |
1061 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
1062 | clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, | |
1063 | <&clks IMX6SX_CLK_CSI>, | |
1064 | <&clks IMX6SX_CLK_DCIC2>; | |
1065 | clock-names = "disp-axi", "csi_mclk", "dcic"; | |
1066 | status = "disabled"; | |
1067 | }; | |
1068 | ||
1069 | lcdif1: lcdif@02220000 { | |
8c78c407 | 1070 | compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; |
b1d17f68 SG |
1071 | reg = <0x02220000 0x4000>; |
1072 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
1073 | clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, | |
1074 | <&clks IMX6SX_CLK_LCDIF_APB>, | |
1075 | <&clks IMX6SX_CLK_DISPLAY_AXI>; | |
1076 | clock-names = "pix", "axi", "disp_axi"; | |
1077 | status = "disabled"; | |
1078 | }; | |
1079 | ||
1080 | lcdif2: lcdif@02224000 { | |
8c78c407 | 1081 | compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; |
b1d17f68 SG |
1082 | reg = <0x02224000 0x4000>; |
1083 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
1084 | clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, | |
1085 | <&clks IMX6SX_CLK_LCDIF_APB>, | |
1086 | <&clks IMX6SX_CLK_DISPLAY_AXI>; | |
1087 | clock-names = "pix", "axi", "disp_axi"; | |
1088 | status = "disabled"; | |
1089 | }; | |
1090 | ||
1091 | vadc: vadc@02228000 { | |
1092 | reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; | |
1093 | reg-names = "vadc-vafe", "vadc-vdec"; | |
1094 | clocks = <&clks IMX6SX_CLK_VADC>, | |
1095 | <&clks IMX6SX_CLK_CSI>; | |
1096 | clock-names = "vadc", "csi"; | |
1097 | status = "disabled"; | |
1098 | }; | |
1099 | }; | |
1100 | ||
1101 | adc1: adc@02280000 { | |
1102 | compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; | |
1103 | reg = <0x02280000 0x4000>; | |
1104 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
1105 | clocks = <&clks IMX6SX_CLK_IPG>; | |
1106 | clock-names = "adc"; | |
1107 | status = "disabled"; | |
1108 | }; | |
1109 | ||
1110 | adc2: adc@02284000 { | |
1111 | compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; | |
1112 | reg = <0x02284000 0x4000>; | |
1113 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
1114 | clocks = <&clks IMX6SX_CLK_IPG>; | |
1115 | clock-names = "adc"; | |
1116 | status = "disabled"; | |
1117 | }; | |
1118 | ||
1119 | wdog3: wdog@02288000 { | |
1120 | compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; | |
1121 | reg = <0x02288000 0x4000>; | |
1122 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
1123 | clocks = <&clks IMX6SX_CLK_DUMMY>; | |
1124 | status = "disabled"; | |
1125 | }; | |
1126 | ||
1127 | ecspi5: ecspi@0228c000 { | |
1128 | #address-cells = <1>; | |
1129 | #size-cells = <0>; | |
1130 | compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; | |
1131 | reg = <0x0228c000 0x4000>; | |
1132 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; | |
1133 | clocks = <&clks IMX6SX_CLK_ECSPI5>, | |
1134 | <&clks IMX6SX_CLK_ECSPI5>; | |
1135 | clock-names = "ipg", "per"; | |
1136 | status = "disabled"; | |
1137 | }; | |
1138 | ||
1139 | uart6: serial@022a0000 { | |
1140 | compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; | |
1141 | reg = <0x022a0000 0x4000>; | |
1142 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
1143 | clocks = <&clks IMX6SX_CLK_UART_IPG>, | |
1144 | <&clks IMX6SX_CLK_UART_SERIAL>; | |
1145 | clock-names = "ipg", "per"; | |
1146 | dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; | |
1147 | dma-names = "rx", "tx"; | |
1148 | status = "disabled"; | |
1149 | }; | |
1150 | ||
1151 | pwm5: pwm@022a4000 { | |
1152 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; | |
1153 | reg = <0x022a4000 0x4000>; | |
1154 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
1155 | clocks = <&clks IMX6SX_CLK_PWM5>, | |
1156 | <&clks IMX6SX_CLK_PWM5>; | |
1157 | clock-names = "ipg", "per"; | |
1158 | #pwm-cells = <2>; | |
1159 | }; | |
1160 | ||
1161 | pwm6: pwm@022a8000 { | |
1162 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; | |
1163 | reg = <0x022a8000 0x4000>; | |
1164 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
1165 | clocks = <&clks IMX6SX_CLK_PWM6>, | |
1166 | <&clks IMX6SX_CLK_PWM6>; | |
1167 | clock-names = "ipg", "per"; | |
1168 | #pwm-cells = <2>; | |
1169 | }; | |
1170 | ||
1171 | pwm7: pwm@022ac000 { | |
1172 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; | |
1173 | reg = <0x022ac000 0x4000>; | |
1174 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
1175 | clocks = <&clks IMX6SX_CLK_PWM7>, | |
1176 | <&clks IMX6SX_CLK_PWM7>; | |
1177 | clock-names = "ipg", "per"; | |
1178 | #pwm-cells = <2>; | |
1179 | }; | |
1180 | ||
1181 | pwm8: pwm@0022b0000 { | |
1182 | compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; | |
1183 | reg = <0x0022b0000 0x4000>; | |
1184 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
1185 | clocks = <&clks IMX6SX_CLK_PWM8>, | |
1186 | <&clks IMX6SX_CLK_PWM8>; | |
1187 | clock-names = "ipg", "per"; | |
1188 | #pwm-cells = <2>; | |
1189 | }; | |
1190 | }; | |
1191 | ||
1192 | pcie: pcie@0x08000000 { | |
1193 | compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; | |
1194 | reg = <0x08ffc000 0x4000>; /* DBI */ | |
1195 | #address-cells = <3>; | |
1196 | #size-cells = <2>; | |
1197 | device_type = "pci"; | |
1198 | /* configuration space */ | |
1199 | ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000 | |
1200 | /* downstream I/O */ | |
1201 | 0x81000000 0 0 0x08f80000 0 0x00010000 | |
1202 | /* non-prefetchable memory */ | |
1203 | 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; | |
1204 | num-lanes = <1>; | |
1205 | interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; | |
1206 | clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>, | |
1207 | <&clks IMX6SX_CLK_PCIE_AXI>, | |
1208 | <&clks IMX6SX_CLK_LVDS1_OUT>, | |
1209 | <&clks IMX6SX_CLK_DISPLAY_AXI>; | |
1210 | clock-names = "pcie_ref_125m", "pcie_axi", | |
1211 | "lvds_gate", "display_axi"; | |
1212 | status = "disabled"; | |
1213 | }; | |
1214 | }; | |
1215 | }; |